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use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---------------------------------------------------------------------------------------
entity ice_pro is
EOC:in std_logic;
ALE,SC,OE,txd:out std_logic:='0';
end ice_pro;
signal clk_sig,clk_sig0,mux_sig,txd_temp:std_logic:='0';
begin
-----------------------------------------------------------------------------------------
p0:process(clk)
variable cnt2:integer:=0;
begin
if rising_edge(clk) then
if(cnt2=200)then
clk_sig0<= not(clk_sig0);
cnt2:=1;
else
cnt2:= cnt2 + 1;
end if;
end if;
end process;
----------------------------------------------------------
p1:process(clk_sig0,st)
variable cnt0:integer:=-1;
begin
if (reset='0') then
if rising_edge(clk_sig0) then
st<=nst;
if (cnt0=1) then
ALE<='1';
cnt0:=cnt0+1;
SC<='1';
cnt0:=cnt0+1;
ALE<='0';
SC<='0';
cnt0:=cnt0+1;
else
cnt0:=cnt0+1;
end if;
case st is
when 0|9=>
if EOC='1' then
nst<=st;
OE<='0';
else
nst<=st+1;
OE<='0';
end if;
when 1|10=>
if EOC='0' then
nst<=st;
OE<='0';
else
nst<=st+1;
OE<='0' ;
end if;
when 2|11=>
OE<='1';
nst<=st+1;
when 3=>
data_in_out1<=data_in;
nst<=st+1;
when 4=>
OE<='0';
chan_sel<="111";
nst<=st+1;
when 5|14=>
OE<='0';
nst<=st+1;
when 6|15=>
OE<='0';
nst<=st+1;
when 7|16=>
OE<='0';
nst<=st+1;
when 8=>
OE<='0';
cnt0:=-1;
nst<=st+1;
when 12=>
data_in_out2<=data_in;
nst<=st+1;
when 13=>
OE<='0';
chan_sel<="000";
nst<=st+1;
when 17=>
OE<='0';
cnt0:=-1;
nst<=0;
when others=>
nst<=0;
end case;
end if;
end if;
end process;
-------------------------------------------------------------------------------------------
p2:process(clk)
variable cnt2:integer:=0;
begin
if rising_edge(clk) then
if(cnt2=208)then
clk_sig<= not(clk_sig);
cnt2:=1;
else
cnt2:= cnt2 + 1;
end if;
end if;
end process;
-------------------------------------------------------------------------------
p3:process(clk_sig)
variable cnt3:integer:=0;
variable cnt4:integer:=1;
begin
if rising_edge(clk_sig)then
if (cnt3>7) then
mux_sig<='1';
if(cnt3=8) then
cnt3:=cnt3+1;
end if;
if (cnt4=1)then
sdata<="000000000";
cnt3:=0;
mux_sig<='0';
cnt4:=cnt4+1;
elsif (cnt4=2)then
sdata<="000000000";
cnt3:=0;
mux_sig<='0';
cnt4:=cnt4+1;
elsif (cnt4=3)then
sdata<="000000000";
cnt3:=0;
mux_sig<='0';
cnt4:=cnt4+1;
elsif (cnt4=4)then
sdata<="000000000";
cnt3:=0;
mux_sig<='0';
cnt4:=1;
end if;
else
cnt3:=cnt3+1;
end if;
else
mux_sig<='0';
end if;
case mux_sig is
when '0'=>txd_temp<=sdata(0);
when '1'=>txd_temp<='1';
end case;
end if;
end process;
txd<=txd_temp;
---------------------------------------------------------------------
end Behavioral;