ECE357: Introduction to VLSI CAD

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Prof. Hai Zhou

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Electrical Engineering & Computer Science

w w Northwestern University

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Logistics

• Time & Location: MWF 11-11:50 TECH L160

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• Instructor: Hai Zhou haizhou@ece.northwestern.edu

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• Office: L461
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• Office Hours: W 3-5P
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• Teaching Assistant: Chuan Lin
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• Texts:
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VLSI Physical Design Automation: Theory & Practice, Sait
& Youssef, World Scientific, 1999.

• Reference:
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 c o m
An Introduction to VLSI Physical Design, Sarrafzadeh &
Wong, McGraw Hill, 1996.

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• Grading: Participation-10% Project-30% Midterm-30%
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Homework-30%

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late: -40% per day
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• Homework must be turned in before class on each due date,

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• Course homepage:
www.ece.northwestern.edu/~haizhou/ece357

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What can you expect from the course

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• Understand modern VLSI design flows (but not the details
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of tools)
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• Understand the physical design problem

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• Familiar with the stages and basic algorithms in physical
design
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problems
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• Improve your capability to design algorithms to solve

• Improve your capability to think and reason

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What do I expect from you

• Active and critical participation

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yours
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– speed me up or slow me down if my pace mismatches

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– “Your role is not one of sponges, but one of whetstones;

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only then the spark of intellectual excitement can

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continue to jump over”

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• Read the textbook

• Do your homeworks
– You can discuss homework with your classmates, but
need to write down solutions independently
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VLSI (Very Large Scale Integrated) chips

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• VLSI chips are everywhere

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– computers
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– commercial electronics: TV sets, DVD, VCR, ...

– automobiles
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– voice and data communication networks

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• VLSI chips are artifacts
– they are produced according to our will ...

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Design: the most challenging human activity

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• Design is a process of creating a structure to fulfill a

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requirement

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• Brain power is the scarcest resource

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– Delegate as much as possible to computers–CAD

• Avoid two extreme views:

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– Everything manual: impossible–millions of gates
– Everything computer: impossible either

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Design is always difficult

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A main task of a designer is to manage complexity
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• Silicon complexity: physical effects no longer be ignored
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– resistive and cross-coupled interconnects; signal
integrity; weak and faster gates

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– reliability; manufacturability
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• System complexity: more functionality in less time
– gap between design and fabrication capabilities
– desire for system-on-chip (SOC)

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CAD: A tale of two designs

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• Target–hardware design
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– How to create a structure on silicon to implement a
function
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• Aid–software design (programming)
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– How to create an algorithm to solve a design problem

• Be conscious of their similarities and differences

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Emphasis of the course

• Design flow
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– Understand how design process is decomposed into
many stages
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– What are the problems need to be solved in each stage
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• Algorithms
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– Understand how an algorithm solves a design problem
– Consider the possibility to extend it

• Be conscious and try to improve problem solving skills

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Basics of MOS Devices

• The most popular VLSI technology: MOS

(Metal-Oxide-Semiconductor).

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• CMOS (Complementary MOS) dominates nMOS and

regularity, etc. o r
pMOS, due to CMOS’s lower power dissipation, high

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• Physical structure of MOS transistors and their schematic

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icons: nMOS, pMOS.
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• Layout of basic devices:
– CMOS inverter
– CMOS NAND gate
– CMOS NOR gate
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MOS Transistors gate
drain source
conductor (polysilicon)

insulator (SiO2)
gate

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n n
drain

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substrate
source

p−substrate
n−transistor
diffusion

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The nMOS switch passes "0" well.

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gate

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conductor (polysilicon)

insulator (SiO2)
gate

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drain

substrate
source

n−substrate diffusion
schematic icon
p−transistor
The pMOS switch passes "1" well.

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A CMOS Inverter
Metal Metal−diffusion contact
A B
VDD pMOS transistor

c o m1 0

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nMOS transistor
. 0 1
Polysilicon

o r VDD
A B
t u w p−channel (pMOS)

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Diffusion
A B

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GND
w n−channel (nMOS)

GND

layout

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A CMOS NAND Gate
A B C

VDD
Metal 0
0

c
0 1

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1 1m
Diffusion

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1
1. 0 1
1 0
Polysilicon

w or VDD

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C
A

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A C

w w B

GND
w GND
layout

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A CMOS NOR Gate
Metal A B C

VDD
0
0
0 1

c o
1 0 m
Polysilicon

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1
1
0 0
1 0

B
w or VDD

tu
A C

w j. n A
C B

GND w w Diffusion

GND
layout

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Current VLSI design phases

• Synthesis (i.e. specification → implementation)

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1. High level synthesis (459 VLSI Algorithmics)

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2. Logic synthesis (459 VLSI Algorithmics)
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3. Physical design (This course)
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• Analysis (implementation → semantics)

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– Verification (design verification, implementation

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verification)
– Analysis (timing, function, noise, etc.)
– Design rule checking, LVS (Layout Vs. Schematic)

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Physical Design

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• Physical design converts a structural description into a
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geometric description.
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• Physical design cycle:
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1. Circuit partitioning
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2. Floorplanning
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3. placement, and pin assignment
4. Routing (global and detailed)
5. Compaction

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Design Styles
Issues of
VLSI circuits

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Performance Area

o r Cost Time−to−market

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Full custom Standard cell Gate array FPGA CPLD SPLD SSI

Performance, Area efficiency, Cost, Flexibility

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Full Custom Design Style

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Data path

ld . over−the−cell

or
PLA routing
I/O

ROM/RAM
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via

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Controller (contact)

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w w A/D converter
Random logic

pins I/O pads

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Standard Cell Design Style

D A B
C

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B B

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A

D C

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D o A

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B

w w Cell A Cell B
library cells

Cell C Cell D Feedthrough Cell

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Gate Array Design Style

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I/O pads

pins

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prefabricated customized
transistor

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wiring
array

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FPGA Design Style

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logic
blocks

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tracks

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switches
Prefabricated all chip components

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SSI/SPLD Design Style
x1 y1 x2 y2 x3 y3 x4 y4

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74LS86 74LS02 74LS00

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x1 Vcc Vcc Vcc

c
y1 x3

x2
y2
y3

x4

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y4

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GND GND GND
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F= i=1 xi yi

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F
(a) 4−bit comparator. (b) SSI implementation.

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x1
y1
x2
y2
x3
y3

w . AND array
x1 y1 x2 y2

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y4

OR array
x3
y3
x4
y4

F
(c) SPLD (PLA) implementation. (d) Gate array implementation.

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 c o m
Comparisons of Design Styles
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Full Standard
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Gate

Cell size
Cell type
custom
variable
variable
t
cell

u
fixed height∗
variable warray
fixed
fixed
FPGA
fixed
programmable
SPLD
fixed
programmable
Cell placement
Interconnections
variable

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variable
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variable
fixed
variable
fixed
programmable
fixed
programmable

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* Uneven height cells are also used.

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Comparisons of Design Styles
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Full

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Standard
. Gate

Fabrication time
Packing density
custom
− − −
+++
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− −
++
array
+
+
FPGA
+++
− −
SPLD
++
− − −
Unit cost in large quantity
Unit cost in small quantity
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+++
− − −w ++
− −
+
+
− −
+++
−
+

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Easy design and simulation − − − − − − ++ +
Easy design change

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Accuracy of timing simulation
Chip speed
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− − −
−
+++
− −

++
−
+
−
−
++
+
−
++
+
−−

+ desirable
− not desirable
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Design-Style Trade-offs
4
10
Full

c o m custom

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3

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custom

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2

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Turnaround
Time
(Days)
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w . SPLD’s
CPLD’s
FPGA’s

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SSI’s optimal
solution

2 3 4 5 6 7
1 10 10 10 10 10 10 10

Logic Capacity (Gates)

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Algorithms 101

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• Algorithm: a finite step-by-step procedure to solve a
problem
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• Requirements:
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– Unambiguity: can even be followed by a machine
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– Basic: each step is among a given primitives
– Finite: it will terminate for every possible input

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A game

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• An ECE major is sitting on the Northwestern beach and

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gets thirsty, she knows that there is an ice-cream booth
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along the shore of Lake Michigan but does not know
where–not even north or south. How can she find the

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booth in the shortest distance?

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• Primitives: walking a distance, turning around, etc.

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A first solution
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• Select a direction, say north, and keep going until find the
booth
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• Suppose the booth is to the south, she will never stop... of

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course, with the assumption she follows a straight line, not
lake shore or on earth

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Another solution

• Set the place she is sitting as the origin

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• Search to south 1 yard, if not find, turn to north

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• Search to north 1 yard, if not find, turn to south

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• Search to south 2 yard, if not find, turn to north

• Search to north 2 yard, if not find, turn to south

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• ... (follow the above pattern in geometric sequence 1, 2, 4,
8, ...)

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 OR
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• n = −1;
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• While (not find) do
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– n = n + 1;

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– Search to south 2n, and turn;

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– Search to north 2n, and turn;

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Correctness proof

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• Each time when the while loop is finished, the range from
south 2n to north 2n is searched. Based on the fact that

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the booth is at a constant distance x from the origin, it will

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be within a range from south 2N to north 2N for some N .

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With n to increment in each loop, we will find the booth in
finite time.
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• Is this the fastest (or shortest) way to find the booth?

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Analysis of algorithm

• Observation: the traveled distance depends on where is the

booth
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• Suppose the distance between the booth and the origin is x

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2n−1 < x
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• When the algorithm stops, we should have 2n ≥ x but

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• The distance traveled is

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3 · 2n + 2(2 · 2n−1 + 2 · 2n−2 + · · · + 2) ≤ 7 · 2n

• which is smaller than 14x

• We know that the lower bound is x, can we do better?

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Complexity of an algorithm

• Two resources: running time and storage

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input size
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• They are dependent on inputs: expressed as functions of

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– Why input size: lower bound (at least read it once)

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• Big-Oh notation: f (n) = O(g(n)) if there exist constants n0
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and c such that for all n > n0, f (n) ≤ c · g(n).
– Make our life easy: is it 13x instead of 14x in our game
– The solution is asymptotically optimal for our game

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Time complexity of an algorithm

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• Run-time comparison: 1000 MIPS (Yr: 200x), 1 instr. /op.
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Time
500
Big-Oh
O(1)
n = 10
5 × 10−7 sec
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n = 100
5 × 10−7 sec
n = 103
5 × 10−7 sec
n = 106
5 × 10−7 sec
3n
n log n
O(n)
O(n log n)
3 × 10−8 sec

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3 × 10−8 sec w
3 × 10−7 sec
2 × 10−7 sec
3 × 10−6 sec
3 × 10−6 sec
0.003 sec
0.006 sec

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n2 O(n2 ) 1 × 10−7 sec 1 × 10−5 sec 0.001 sec 16.7 min
n3
2n
n!
O(n3 )
O(2n )
O(n!)
w . 1 × 10−6 sec
1 × 10−6 sec
0.003 sec
0.001 sec
3 × 1017 cent.
-
1 sec
-
-
3 × 105 cent.
-
-

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• Polynomial-time complexity: O(p(n)), where n is the input
size and p(n) is a polynomial function of n.

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Complexity of a problem

• Given a problem, what is the running time of the fastest

algorithm for it?
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• Upper bound: easy–find an algorithm with less time

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• Lower bound: hard–every algorithm requires more time

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• P: set of problems solvable in polynomial time

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• NP(Nondeterministic P): set of problems whose solution

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can be proved in polynomial time

• Millennium open problem: NP 6= P?

– Fact: there are a set of problems in NP resisting any
polynomial solution for a long time (40 years)
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NP-complete and NP-hard

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• Cook 1970: If the problem of boolean satisfiability can be

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solved in poly. time, so can all problems in NP.

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• Such a problem with this property is called NP-hard.

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• If a NP-hard problem is in NP, it is called NP-complete.
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• Karp 1971: Many other problems resisting poly. solutions
are NP-complete.

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How to deal with a hard problem

• Prove the problem is NP-complete:

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poly. time)
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1. The problem is in NP (i.e. solution can be proved in

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2. It is NP-hard (by polynomial reducing a NP-complete
problem to it)
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• Solve NP-hard problems:
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– Exponential algorithm (feasible only when the problem
size is small)
∗ Pseudo-polynomial time algorithms
– Restriction: work on a subset of the input space
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 c o m
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– Approximation algorithms: get a provable
close-to-optimal solution
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– Heuristics: get a as good as possible solution
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– Randomized algorithm: get the solution with high
probability
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Algorithmic Paradigms

• Divide and conquer: divide a problem into sub-problems,

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solve sub-problems, and combine them to construct a
solution.

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– Greedy algorithm: optimal solutions to sub-problems will
give optimal solution to the whole problem.

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– Dynamic programming: solutions to a larger problem are

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constructed from a set of solutions to its sub-problems.

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• Mathematical programming: a system of optimizing an

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objective function under constraints functions.

• Simulated annealing: an adaptive, iterative,

non-deterministic algorithm that allows “uphill” moves to
escape from local optima.
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 c o m
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• Branch and bound: a search technique with pruning.

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• Exhaustive search: search the entire solution space.

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