Overview Ways of specifying circuits

! Last lecture ! Schematics

" Incompletely specified functions " Structural description
" Design examples " Describe circuit as interconnected elements
" k-maps for POS minimization # Build complex circuits using hierarchy
# Large circuits are unreadable
! Today
" Verilog ! HDLs
# Structural constructs " Hardware description languages
# Describing combinational circuits # Not programming languages
# Parallel languages tailored to digital design
" Synthesize code to produce a circuit

CSE370, Lecture 8 1 CSE370, Lecture 8 2

Hardware description languages (HDLs) Verilog versus VHDL

! Abel (~1983) ! Both IEEE standard languages
" Developed by Data-I/O
" Targeted to PLDs
! Most tools support both
" Limited capabilities (can do state machines)
! Verilog is simpler
! Verilog (~1985) " Less syntax, fewer constructs

" Developed by Gateway (now part of Cadence)

! VHDL is more structured
" Similar to C
" Can be better for large, complex systems
" Moved to public domain in 1990
" Better modularization

! VHDL (~1987)
" DoD sponsored
" Similar to Ada

CSE370, Lecture 8 3 CSE370, Lecture 8 4

Simulation versus synthesis Simulation versus synthesis (cont)

! Simulation ! Simulation
" Execute a design to verify correctness " Models what a circuit does
# Multiply is *, ignoring implementation options
! Synthesis " Can include static timing
" Generate a netlist from HDL code " Allows you to test design options

! Synthesis
HDL synthesis circuit " Converts your code to a netlist
description
# Can simulate synthesized design
" Tools map your netlist to hardware
execution simulation ! Verilog and VHDL simulate and synthesize
" CSE370: Learn simulation
functional functional/timing " CSE467: Learn synthesis
validation validation

CSE370, Lecture 8 5 CSE370, Lecture 8 6

Simulation Levels of abstraction
! You provide an environment ! Verilog supports 4 description levels
" Using non-circuit constructs " Switch
# Read files, print, control simulation " Gate
structural
" Using Verilog simulation code " Dataflow
# A test fixture Note: We will ignore behavioral
" Algorithmic
timing and test benches
until next Verilog lecture ! Can mix & match levels in a design

Simulation ! Designs that combine dataflow and algorithmic

constructs and synthesis are called RTL
Test Fixture Circuit Description " Register Transfer Level
(Specification) (Synthesizeable)

CSE370, Lecture 8 7 CSE370, Lecture 8 8

Structural versus behavioral Verilog Verilog tips

! Structural ! Do not write C-code
" Describe explicit circuit elements " Think hardware, not algorithms
" Describe explicit connections between elements # Verilog is inherently parallel
# Connections between logic gates # Compilers dont map algorithms to circuits well
" Just like schematics, but using text
! Do describe hardware circuits
! Behavioral " First draw a dataflow diagram

" Describe circuit as algorithms/programs " Then start coding

# What a component does
# Input/output behavior ! References
" Many possible circuits could have same behavior " Tutorial and reference manual are here:

# Different implementations of a Boolean function " http://www.cs.washington.edu/education/courses/370/03sp/h

tml/compinfo.html

CSE370, Lecture 8 9 CSE370, Lecture 8 10

Basic building blocks: Modules Modules are circuit components

" Instanced into a design A
AND2 " Module has ports A
AND2
OR2 OR2
# Never called g1
E # External connections g1
E

" Illegal to nest module defs.

B 1
3
g3 X # A,B,C,X,Y in example B 1
3
g3 X
" Port types
" Modules execute in parallel NOT NOT
C Y # input C Y
" Names are case sensitive 2 g2
# output 2 g2
" // for comments # inout (tristate)
" Name cant begin with a number // first simple example " Use assign statements for
" Use wires for connections module smpl (X,Y,A,B,C); Boolean expressions // previous example as a
# and & // Boolean expression
" and, or, not are keywords input A,B,C;
module smpl2 (X,Y,A,B,C);
output X,Y; # or |
" All keywords are lower case # not ~
input A,B,C;
wire E
" Gate declarations (and, or, etc) and g1(E,A,B);
output X,Y;
assign X = (A&B)|~C;
# List outputs first not g2(Y,C);
assign Y = ~C;
# Inputs second or g3(X,E,Y);
endmodule
endmodule
CSE370, Lecture 8 11 CSE370, Lecture 8 12
Structural Verilog Behavioral Verilog
module xor_gate (out,a,b); ! Describe circuit behavior A Sum
input a,b; " Not implementation B Adder
8 basic gates (keywords): Cout
output out; Cin
wire abar, bbar, t1, t2; and, or, nand, nor
not inva (abar,a);
buf, not, xor, xnor
not invb (bbar,b); module full_addr (Sum,Cout,A,B,Cin);
and and1 (t1,abar,b); input A, B, Cin;
and and2 (t2,bbar,a); output Sum, Cout;
or or1 (out,t1,t2); assign {Cout, Sum} = A + B + Cin;
endmodule endmodule
NOT AND2
abar
a t1
4 and1
inva b 6
OR2 {Cout, Sum} is a concatenation
or1 out
8
NOT AND2
bbar
b
5 and2
invb a 7 t2
CSE370, Lecture 8 13 CSE370, Lecture 8 14

Behavioral 4-bit adder Data types

module add4 (SUM, OVER, A, B); ! Values on a wire
" 0, 1, x (dont care), z (tristate or unconnected)
input [3:0] A;
input [3:0] B;
output [3:0] SUM; ! Vectors
output OVER;
" A[3:0] vector of 4 bits: A[3], A[2], A[1], A[0]
assign {OVER, SUM[3:0]} = A[3:0] + B[3:0];
endmodule # Unsigned integer value
# Indices must be constants
[3:0] A is a 4-wire bus labeled A " Concatenating bits/vectors
Bit 3 is the MSB # e.g. sign extend
Bit 0 is the LSB $B[7:0] = {A[3], A[3], A[3], A[3], A[3:0]};
$B[7:0] = {4{A[3]}, A[3:0]};
Can also write [0:3] A Buses are implicitly connected " Style: Use a[7:0] = b[7:0] + c;
Bit 0 is the MSB If you write BUS[3:2], BUS[1:0] Not a = b + c;
Bit 3 is the LSB They become part of BUS[3:0]
" Legal syntax: C = &A[6:7]; // logical and of bits 6 and 7 of A
CSE370, Lecture 8 15 CSE370, Lecture 8 16

Numbers Operators
! Format: <sign><size><base format><number>

! 14
" Decimal number
! 4b11
" 4-bit 2s complement binary of 0011 (is 1101)
! 12b0000_0100_0110
" 12 bit binary number (_ is ignored)
! 3h046
" 3-digit (12-bit) hexadecimal number
! Verilog values are unsigned
" C[4:0] = A[3:0] + B[3:0];
# if A = 0110 (6) and B = 1010(6), then C = 10000 (not 00000) Similar to C operators
# B is zero-padded, not sign-extended

CSE370, Lecture 8 17 CSE370, Lecture 8 18

 Continuous assignment
! Assignment is continuously evaluated
" Corresponds to a logic gate
" Assignments execute in parallel
assign A = X | (Y & ~Z);
assign B[3:0] = 4'b01XX;
assign C[15:0] = 4'h00ff;
assign #3 {Cout, Sum[3:0]} = A[3:0] + B[3:0] + Cin;
Gate delay (used by simulator)
Boolean operators
(~ for bit-wise negation)
bits can assume four values
(0, 1, X, Z)
variables can be n-bits wide
(MSB:LSB)
arithmetic operator
multiple assignment (concatenation)
Example: A comparator
module Compare1 (Equal, Alarger, Blarger, A, B);
input A, B;
output Equal, Alarger, Blarger;
assign Equal = (A & B) | (~A & ~B);
assign Alarger = (A & ~B);
assign Blarger = (~A & B);
endmodule
Top-down design and bottom-up design are both okay
module ordering doesnt matter
because modules execute in parallel

CSE370, Lecture 8 19 CSE370, Lecture 8 20

Comparator example (cont) Functions

// Make a 4-bit comparator from 4 1-bit comparators ! Use functions for complex combinational logic
module Compare4(Equal, Alarger, Blarger, A4, B4);
input [3:0] A4, B4;
module and_gate (out, in1, in2);
output Equal, Alarger, Blarger; input in1, in2;
wire e0, e1, e2, e3, Al0, Al1, Al2, Al3, B10, Bl1, Bl2, Bl3; output out;

Compare1 cp0(e0, Al0, Bl0, A4[0], B4[0]); assign out = myfunction(in1, in2);
Compare1 cp1(e1, Al1, Bl1, A4[1], B4[1]); function myfunction;
Compare1 cp2(e2, Al2, Bl2, A4[2], B4[2]); input in1, in2;
Compare1 cp3(e3, Al3, Bl3, A4[3], B4[3], ); begin
myfunction = in1 & in2;
assign Equal = (e0 & e1 & e2 & e3);
assign Alarger = (Al3 | (Al2 & e3) | end
(Al1 & e3 & e2) | endfunction Benefit:
(Al0 & e3 & e2 & e1));
Functions force a result
assign Blarger = (~Alarger & ~Equal); endmodule
endmodule Compiler will fail if function
does not generate a result
CSE370, Lecture 8 21 CSE370, Lecture 8 22

Overview Summary of two-level combinational-logic

! Last lecture ! Logic functions and truth tables
" Verilog
" AND, OR, Buf, NOT, NAND, NOR, XOR, XNOR
" Minimal set
# Structural constructs
# Describing combinational circuits ! Axioms and theorems of Boolean algebra
" Proofs by re-writing
! Today " Proofs by perfect induction (fill in truth table)
" Summary of 2-level combinational logic
" Class example: A 4-bit prime-number detector
! Gate logic
" Networks of Boolean functions
" Quiz
" NAND/NOR conversion and de Morgans theorem
! Canonical forms
" Two-level forms
" Incompletely specified functions (dont cares)
! Simplification
" Two-level simplification (K-maps)
CSE370, Lecture 8 23 CSE370, Lecture 8 24
Solving combinational design problems
! Step 1: Understand the problem
" Identify the inputs and outputs
" Draw a truth table

! Step 2: Simplify the logic

" Draw a K-map
" Write a simplified Boolean expression
# SOP or POS
# Use dont cares

! Step 3: Implement the design

" Logic gates and/or Verilog

CSE370, Lecture 8 25