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Power MOSFETs
Outline
Construction of power MOSFETs
Physical operations of MOSFETs
Power MOSFET switching Characteristics
Factors limiting operating specfications of MOSFETs
COOLMOS
PSPICE and other simulation models for MOSFETs
contact to source
source
diffusion
conductor
field
oxide
gate
oxide
gate
width
N+ N+ N+ N+
P P
N-
gate N+
conductor
N+ N+ N+ N+
P (body) P (body)
N- parasitic i channel
(drift region) BJT
D length
integral
N+ diode
drain
boddy-source short
Oxide
N+ N+
Gate
P Channel
P conductor
length Trench-gate MOSFET
Parasitic BJT Integral
N- ID
ID diode Newest geometry. Lowest
N+ on-state resistance.
Drain
gate oxide
gate source
N+ N+ P
V-groove MOSFET.
P
First practical power
N MOSFET.
i
N+
D Higher on-state
resistance.
drain
VG S 3
linearized
V
GS2
VG S 1
v
V GS
v
V
GS
<V
GS(th) BV
DS GS(th)
DSS
D D
G
G
N-channel P-channel
MOSFET MOSFET
S S
+ +
N N
ionized P
depletion layer
acceptors
P boundary inversion layer
ionized with free electrons
N acceptors
electron
drift velocity
Mobility also decreases because large
8 x 1 06
values of VGS increase free electron
cm/sec density.
In MOSFET channel, J = q n n E
Mobilty decreases, especially via carrier-
= q n v n ; velocity v n = n E
carrier scattering leead to linear transfer
curve in power devices instead of square
Velocity saturation means that the law transfer curve of logic level MOSFETs.
mobility n inversely proportional to
electric field E.
Copyright by John Wiley & Sons 2003
MOSFETs - 7
Channel-to-Source Voltage Drop
P
Smaller Vox corresponds to a smaller
N channel thickness. Hence reduction in
N+ channel thickness as drain is
approached from the source.
Io
r
D DS(on)
F
R
G
Cgd
+ G
V
GG
C
gs
S
Buck converter using power MOSFET.
D
MOSFET equivalent circuit valid for
on-state (triode) region operation.
C
gd
G I = f(V )
D GS
C
gs
MOSFET equivalent circuit valid for off-
S state (cutoff) and active region operation.
Copyright by John Wiley & Sons 2003
MOSFETs - 10
MOSFET Capacitances Determining Switching Speed
gate
source
C gs C
gd
C
N+ gd2
N+ P idealization
C
P gd
Cd s
N actual
C gd1
drain-body
N+ depletion layer
v
v = v 200 V DS
GS DS
drain
C gd C
bridge
G D
+V -
C gs Cd s b
S C gd
G D
C iss
S
C oss
S
C iss = C gs + C gd
C oss = C gd + C d s
Copyright by John Wiley & Sons 2003
MOSFETs - 12
Turn-on Equivalent Circuits for MOSFET Buck Converter
Vi n Vi n
Equi val ent ci r cui t Equivalent cir cuit
dur i ng td(on). dur ing tr i .
D I o
F D I o
F
C
DC C
R C gd1 DC
G R C gd1
G
+
V i
G +
GG C V
gs i
GG G C
gs
Vi n
Equi val ent ci r cui t Equivalent cir cuit
V
dur i ng tfv1. in
dur ing tfv2.
I o I o r
DS(on)
R
G
R Cg d 1
G +
V i C
G gs
+ GG C gd2
V i
GG G
v (t)
GS
V
G S , Io
t = R (C + C )
G gd2 gs
V
GS(th)
i (t)
G
t
Charge on C
Charge on C + Cg d gd
gs
V in
t
fv2
Free-wheeling diode
assumed to be ideal.
v (t)
DS
i (t)
(no reverse recovery
D
current).
Io
t
t ri V t
d(on) t fv1 DS(on)
Q gate g (V - V )
Q Q m gs t
on p
Vgs V + I /gm
Q t D1
(Vt+ID1/gm) T1
V
Qon = ![Cgs(Vgs)!+!Cgd(Vgs)]!Vgs!dVgs
t
t
Vgs,off Vgs,off V
gs,on
Vds,on I
d
! I
Qp = !Cgd(Vds)!Vds dVds D1
t
Vd
V
Vgs,on ds
QT = Qon + Qp + ![Cgs(Vgs)!+!Cgd(Vgs)]!Vgs!dVgs
V
V ds,on
(Vt+ID1/gm) d
t
Copyright by John Wiley & Sons 2003
MOSFETs - 15
Turn-on Waveforms with Non-ideal Free-wheeling Diode
Vi n
Io i D (t)
F
Io + I rr
I rr t
C gd1
I rr R
G
i (t)
D +
t rr V i
Io
GG G Cgs
t t
ri
t
Copyright by John Wiley & Sons 2003
MOSFETs - 16
MOSFET-based Buck Converter Turn-off Waveforms
t 2= R (C
G gd2
+ C )
gs
v (t)
GS t1= R (C + C )
G gd1 gs Assume ideal fr ee-
V
GG V V
GS(th)
w heeling diode.
G S , Io
Essentially the
t inver se of the tur n- on
i (t)
G
pr ocess.
t
d(off)
v (t)
DS Model quanitatively
i (t)
D using the same
I o
V
in equivalent cir cuits as
for tur n- on. Simply
use cor r ect dr iving
t voltages and initial
t
rv2
t rv1 t fi conditions
Cg d
+ N+ G
N parasitic
BJT
P P
Cg d
N
+
N S
dVDS
drain
Large positive Cgd
dt
could turn on parasitic BJT.
D
L+
Turn-on of T+ and reverse recovery of Df- will
D
F+ dv DS
produce large positive Cgd in bridge circuit.
T+ I o dt
D
L- Parasitic BJT in T- likely to have been in reverse
active mode when Df- was carrying current. Thus
DF - stored charge already in base which will increase
T-
dv DS
likeyhood of BJT turn-on when positive Cgd is
dt
generated.
Copyright by John Wiley & Sons 2003
MOSFETs - 18
Maximum Gate-Source Voltage
V GS(max) = maxi mum per mi ssi bl e gate-
sour ce vol tage.
+ +
N N N
P P
+
N
drain region
resistance
+
N
drain
Rd
MOSFETs can be easily
paralleled because of Q
1
positive temperature G
coefficient of rDS(on).
log ( i )
D
I
DM No distinction betw een
-5
FBSOA and RBSOA. SOA
10 sec
is squar e.
10 - 4 sec
Tj , m a x FB = for w ar d bias.
10
-3
sec
V GS 0.
RB = r ever se bias.
DC
V GS 0.
BV
DSS
No second br eakdow n.
log ( v )
DS
N+ N+ N+ N+
+ +
P P
Conventional
vertically oriented
N-
power MOSFET
N+
drain
source
gate
cond
uctor
COOLMOS structure
N+ N+ N+ N+
P P (composite buffer structure,
b b
W super-junction MOSFET,
P N P super multi-resurf
MOSFET)
b b b
Vertical P and N regions of
width b doped at same
N+ density (Na = Nd)
drain
Copyright by John Wiley & Sons 2003
MOSFETs - 24
COOLMOS Operation in Blocking State
source
gate
cond COOLMOS structure partially
uctor
depleted.
N+ N+ N+ N+
P P
b b Arrows indicate direction of
depletion layer growth as device
N -
P
turns off.
V1
P
+ Note n-type drift region and
N+
adjacent p-type stripes deplete
drain uniformly along entire vertical
length.
source
gate
cond
COOLMOS structure at edge
uctor of full depletion with applied
N+ N+ N+ N+ voltage Vc. Depletion layer
P P
b b
N reaches to middle of vertical P
and N regions at b/2.
Ec Ec -
P P
Vc Using step junction formalism,
+ Vc = (q b2 Nd)/(4 e) = b Ec,max/2
N+
Keep Ec,max EBD/2. Thus
drain Nd ( e EBD)/(q b)
N+ N+ N+ N+
P P P
b N b
Ev Ev
Ev
P -
P
V
Ec Ec
+
N+
drain
V > Vc
For applied voltages V > Vc, vertically oriented electric field Ev begins to grow in depletion region.
Ev spatially uniform since space charge compensated for by Ec. Ev V/W for V >> Vc.
Doping level Nd in n-type drift region can be much greater than in drift region of conventional
VDMOS drift region of similar BVBD capability.
source
gate
cond
uctor
On-state specific resistance ARon [-cm2]
N+ N+ Ro n N+ N+
P P much less than comparable VDMOS
b b because of higher drift region doping.
P P -
V1 COOLMOS conduction losses much
N
less than comparable VDMOS.
+
N+
drain
ID R
L
For more complete analysis see: Antonio G.M. Strollo and Ettore Napoli, Optimal ON-Resistance
Versus Breakdown Voltage Tradeoff in Superjunction Power Device: A Novel Analytical Model, IEEE
Trans. On Electron Devices,Vol. 48, No. 9, pp 2161-2167, (Sept., 2001)
t
Effect on COOLMOS switching times
relative to VDMOS switching times.
v (t) V
DS V Turn-on delay time - shorter
DS(on)
d
Current rise time - shorter
Voltage fall time1 - shorter
t
td ( o n ) t r i t fv1 t t rv1 tfi Voltage fall time2 - longer
fv2 t d(off)
Turn-off delay time - longer
i (t) t rv2 Voltage rise time1 - longer
D Io
Voltage rise time2 - shorter
t Current fall time - shorter
Copyright by John Wiley & Sons 2003
MOSFETs - 29
PSPICE Built-in MOSFET Model
Circuit components
Drain
RG RB
RDS Idrain Cbs and Cbd = nonlinear voltage-
Gate Bulk dependent capacitors (depletion layer
capacitances)
Cgs Cbs
N+ N+
C bg
Body-source short puts Cbd between drain and
source.
P
C bs C bd
Variations in drain-source voltage relatively
Drain-body small, so changes in Cbd also relatively small.
Source-body B
depletion layer
depletion layer
Body-
source source gate
short
Cg s
Cbg
N+
Cg d N+
Cbs P
P
Cb d N
N+
drain
drain-body depletion layer
Drain-drift region and large drain-source
voltage variations cause large variations in MOSFET circuit simulation
drain-body depletion layer thickness models must take this variation
into account.
Large changes in Cgd with changes in drain-source
voltage. 10 to 100:1 changes in Cgd measured in high
voltage MOSFETs.
0
0V
10V V 20V 30V
DS
60V
MTP3055E V
DS
Comparison of transient response of drain-
40V
source voltage using PSPICE model and
Motorola an improved subcircuit model. Both
SPICE
20V subcircuit model models used in same step-down converter
model circuit.
0V
0s 100ns 200ns 300ns
Time
M2 M3
JFET Q1 and Rd account for voltage drop
Dsub
V offset Q
1
in N- drain drift region
+
-
Gate M1
Dsub is built-in SPICE diode model used
LG R
G to account for parasitic anti-parallel diode
in MOSFET structure.
RS
LS
Reference - "An Accurate Model for
Power DMOSFETs Including Inter-
Source electrode Capacitances", Robert Scott,
Gerhard A. Frantz, and Jennifer L.
LG, RG, LS RS, LD, RD - parasitic Johnson, IEEE Trans. on Power
inductances and resistances Electronics, Vol. 6, No. 2, pp. 192-198,
(April, 1991)
M1= intrinsic SPICE level 2 MOSFET with no
parasitic resistances or capacitances.
Copyright by John Wiley & Sons 2003
MOSFETs - 35