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1.1 Encoders:
Definition
I0 Enc
I1 O0
I2 O1
ON-1
IM
Always: 2N M
Example
o 4 inputs
o 2 outputs
Inputs Outputs
A Enc A B C D Y X
B Y 1 0 0 0 0 0
C 0 1 0 0 0 1
X 0 0 1 0 1 0
D
0 0 0 1 1 1
Y
AB/CD0001111000X1X1010XXX11XXXX100XXX
Y=D+C
Similarly:
EE201: Digital Circuits and Systems 1 Combinatorial Logic page 3 of 29
X=D+B
B X
Y
D
Application
S0 S1 S2 S3 S4 S5 S6 S7 S8 S 9 B0 B1 B2 B3
1 0 0 0 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 0 0 0 1 0 0
0 0 0 0 0 1 0 0 0 0 0 1 0 1
0 0 0 0 0 0 1 0 0 0 0 1 1 0
0 0 0 0 0 0 0 1 0 0 0 1 1 1
0 0 0 0 0 0 0 0 1 0 1 0 0 0
0 0 0 0 0 0 0 0 0 1 1 0 0 1
EE201: Digital Circuits and Systems 1 Combinatorial Logic page 4 of 29
1.2 Decoders:
Definition
Dec O0
I0 O1
I1 O2
IN-1
OM-1
Always: 2N M
EE201: Digital Circuits and Systems 1 Combinatorial Logic page 5 of 29
Example
o 2 inputs
o 4 outputs
Inputs Outputs
A X Y A B C D
X Dec 0 0 1 0 0 0
B
0 1 0 1 0 0
Y C 1 0 0 0 1 0
D 1 1 0 0 0 1
A
X/Y01010100
_ _ _ _
A = X Y, B = X Y,C = X Y, D=XY
EE201: Digital Circuits and Systems 1 Combinatorial Logic page 6 of 29
Implementation
X
A
Application 1
o 4 inputs B0
o 10 outputs Dec S0
B1
B2
S9
B3
EE201: Digital Circuits and Systems 1 Combinatorial Logic page 7 of 29
Inputs Outputs
B0 B1 B2 B3 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9
0 0 0 0 1 0 0 0 0 0 0 0 0 0
0 0 0 1 0 1 0 0 0 0 0 0 0 0
0 0 1 0 0 0 1 0 0 0 0 0 0 0
0 0 1 1 0 0 0 1 0 0 0 0 0 0
0 1 0 0 0 0 0 0 1 0 0 0 0 0
0 1 0 1 0 0 0 0 0 1 0 0 0 0
0 1 1 0 0 0 0 0 0 0 1 0 0 0
0 1 1 1 0 0 0 0 0 0 0 1 0 0
1 0 0 0 0 0 0 0 0 0 0 0 1 0
1 0 0 1 0 0 0 0 0 0 0 0 0 1
S0
B0B1/B2 B30001111000100001000011XXXX1000XX
S 0 B0 B1 B 2 B3 S 5 B1 B 2 B3
S1 B0 B1 B2 B3 S 6 B1 B2 B3
S 2 B1 B 2 B3 S 7 B1 B2 B3
S 3 B1 B2 B3 S 8 B0 B3
S 4 B1 B 2 B3 S 9 B0 B3
Implementation
EE201: Digital Circuits and Systems 1 Combinatorial Logic page 8 of 29
So
B0
S1
B1 S2
S3
B2
S4
B3
S5
S6
S7
S8
S9
EE201: Digital Circuits and Systems 1 Combinatorial Logic page 9 of 29
Application 2
a
a d b
A b
Dec
B c
d
C e c
f e g
D g
A B C D No. Segments
0 0 0 0 0 a, b, d, e, f, g
0 0 0 1 1 b, g
0 0 1 0 2 a, b, c, e, f
0 0 1 1 3 a, b, c, f, g
0 1 0 0 4 b, c, d, g
0 1 0 1 5 a, c, d, f, g
0 1 1 0 6 a, c, d, e, f, g
0 1 1 1 7 a, b, g
1 0 0 0 8 a, b, c, d, e, f, g
1 0 0 1 9 a, b, c, d, f, g
1 0 1 0 X -
1 0 1 1 X -
1 1 0 0 X -
1 1 0 1 X -
1 1 1 0 X -
1 1 1 1 X -
EE201: Digital Circuits and Systems 1 Combinatorial Logic page 10 of 29
Horizontal segments: a, c, f
a => 0, 2, 3, 5, 6, 7, 8, 9
c => 2, 3, 4, 5, 6, 8, 9
f => 0, 2, 3, 5, 6, 8, 9
Minimisation
AB/CD 00 01 11 10
00 1 0 1 1
01 0 1 1 1
11 X X X X
10 1 1 X X
Equation
a A C BD B D
Minimisation
AB/CD 00 01 11 10
00 0 0 1 1
01 1 1 0 1
11 X X X X
10 1 1 X X
EE201: Digital Circuits and Systems 1 Combinatorial Logic page 11 of 29
Equation
c A BC C D BC
Minimisation
f
AB/CD 00 01 11 10
00 1 0 1 1
01 0 1 0 1
11 X X X X
10 1 1 X X
Whats missing?
Equation
f A BC D C D BC B D
Implementation (a segment)
A
a
B
C
D
EE201: Digital Circuits and Systems 1 Combinatorial Logic page 12 of 29
a A C BD B D
a a A C BD B D A C BD B D
A
a
B
C
D
EE201: Digital Circuits and Systems 1 Combinatorial Logic page 13 of 29
1.3 Multiplexers:
Definition
I0 Mux
I1
Z
IN-1
S0 S1 SM
Always: 2M = N
EE201: Digital Circuits and Systems 1 Combinatorial Logic page 14 of 29
Example 1
Two-channel Multiplexer
o 2 inputs
o 1 select input
o 1 output
Example 2
Two-channel two-bit Multiplexer
o 4 inputs
o 1 select input
o 2 outputs
A0
2-channel
A0 MUX Z0
A1
2-channel
B0 MUX
Z1
B1
S
EE201: Digital Circuits and Systems 1 Combinatorial Logic page 16 of 29
I0
S1 S0 Z1
I1 Mux
0 0 I0
Z
0 1 I1
I2
1 0 I2
I3 1 1 I3
S0 S1
We have:
_ _ _ _
Z = I0 S1 S0 + I1 S1 S0 + I2 S1 S0 + I3 S1 S0
Implementation
I0
____
S1
____
S0
I1
____
S1
S0
I2
Z0
S1
____
S0
I3
S1
S0
EE201: Digital Circuits and Systems 1 Combinatorial Logic page 17 of 29
I0
S2 S1 S0 Z1
I1 Mux
0 0 0 I0
Z
0 0 1 I1
I6
0 1 0 I2
I7 0 1 1 I3
1 0 0 I4
1 0 1 I5
S0 S1 S2 1 1 0 I6
1 1 1 I7
We have:
_ _ _ _ _
Z = I0 S2 S1 S0 + I1 S2 S1 S0 + + I7 S2 S1 S0
Applications
EE201: Digital Circuits and Systems 1 Combinatorial Logic page 18 of 29
Application 1
o 4 inputs
o 1 output
o 4-bit Register
o 2-bit Counter
o 4-channel Mux
o 1 serial line
X0
X2
Serial
line
X3
S1 S2
2-bit
Counter
Clock
Application 2
E.g. 1
o Original function:
F ABC ABC AB
o Full form:
F A B C A B (0) A B C A B (1)
o 4-channel Multiplexer:
Z S1 S 2 I 0 S1 S 2 I1 S1 S 2 I 2 S1 S 2 I 3
0 4:1 line
MUX
_
C F
1 S1 S2
A B
EE201: Digital Circuits and Systems 1 Combinatorial Logic page 21 of 29
Notes:
Homework:
E. g. 2
o Original function:
F ABC AB D AB E
o Partial form:
F A B C A B D A B ( 0) A B E
o 4-channel Multiplexer:
Z S1 S 2 I 0 S1 S 2 I1 S1 S 2 I 2 S1 S 2 I 3
_ 4:1 line
D MUX
0 F
_
E S1 S2
A B
o Note: normal implementation would have
required a 16-channel MUX
E. g. 3
EE201: Digital Circuits and Systems 1 Combinatorial Logic page 23 of 29
o Original function:
F v w x y z v w x yz v w x y z v w x y z
vwx y zvwx y zvwx y zvwx y z
vwx y zvwx y zvwx y zvwx y z
0
v
v
v1
6
Ch
a
n
n
e
l
1MU
X
v
1
v
0
F
0
v
0
v
0
v
0S
S
1S
2
3S
4
w
x
y
z
o Factorised function:
F (v w x v w x v w x ) y z
(v w x v w x ) y z
(v w x v w x v w x v w v w x ) y z
(v w x v w x ) y z
EE201: Digital Circuits and Systems 1 Combinatorial Logic page 24 of 29
F ( F1 ) y z ( F2 ) y z ( F3 ) y z ( F2 ) y z
w
x
v
4 F 2
vCh
a
nn
el 4 F
C
h
a
n
ne
l
0 M
UX
M
U
X
0S1S
2
S
1S
2
w
x
yz
v
4 F
1C
h
a
n
ne
l
3
v M
U
X
vS
1S
2
w
x
Can you reduce it further if you had 2-ch MUX?
1.4 Demultiplexers:
O0
Definition
O1
I DMUX its input to one of the
A demultiplexer transfers
outputs depending on the binary code provided at
the select inputs
ON-1
S0 S1 SM-1
EE201: Digital Circuits and Systems 1 Combinatorial Logic page 25 of 29
Always: 2M = N
Example 1
Two-channel Demultiplexer
o 1 input
o 1 select input
EE201: Digital Circuits and Systems 1 Combinatorial Logic page 26 of 29
o 2 outputs
S O0 O1
0 I 0
1 0 I
O0
I DMUX
O1
O0
I
O1
S
EE201: Digital Circuits and Systems 1 Combinatorial Logic page 27 of 29
Example 2
Eight-channel Demultiplexer
o 1 input
o 3 select inputs
o 8 output
I
O0
S0
S1 O1
S2
O2
O3
O4
O5
O6
O7
EE201: Digital Circuits and Systems 1 Combinatorial Logic page 28 of 29
Application
4-bit/4-word Serial Data Transmission System:
B 4:1
Serial line
line
MUX
C
D
S1 S2
Mod-8 Mod-4
Counter Counter
1:4
line
Serial line
DMUX
S1 S2
Mod-8 Mod-4
Counter Counter