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CERTIFICATE
This is to certify that dissertation entitled, Design Of Key Analog
Building Blocks Using FinFETs submitted by Ekta Sharma in partial
fulfillment of the requirements for the award of degree of Master of
Technology in Electronics Engineering (Electronic Circuits and Systems
Design) to the Department of Electronics Engineering , AMU Aligarh is an
authentic record of work carried out by her under our supervision and
guidance.
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ACKNOWLEDGEMENT
Ekta Sharma
Faculty No. 15-LEEM-030
Enrolment No. GI-4777
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ABSTRACT
A simple alpha power law model for FinFET was proposed in preliminary dissertation
work which is being used for automatic design of CMOS Inverting Amplifier using
FinFETs in this dissertation using MATLAB and HSPICE software.
In addition to this, gm - ID method is also used for design of Single Stage Miller
Operational Amplifier(OP-AMP) using resistive load and Two Stage miller OP-AMP
with active load using Pre-Computed Lookup Tables, utilising the same softwares.
Main focus is on specification of Bandwidth, Gain and Phase Margin. The idea can be
further extended to more specifications in future work.
BSIM-CMG 20nm model is used for FinFET. HSPICE toolbox is used for the
simulation purpose in MATLAB.
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TABLE OF CONTENTS
List of abbreviations & Symbols
List of Figures
List of Tables
Motivation __________________________________________________________________ 1
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CHAPTER 4: Analog design & gm/ID design methodology __________________ 33
4.1 Analog design ____________________________________________________ 34
4.1.1 Performance metrics of analog design _____________________________ 34
4.1.2 Regions of transistor operation _________________________________ 34-35
4.2 gm/ID design methodology __________________________________________ 35
4.2.1 Basic description____________________________________________ 35-36
4.2.2 Key features of gm/ID method _________________________________ 36-37
4.2.3 Steps in gm/ID method ________________________________________ 37
4.2.3.1 For bandwidth specification _______________________________ 37
4.2.3.2 For gain specification ____________________________________ 37
CHAPTER 5: Results for validation of gm/ID starter kit for FinFET _________ 38
5.1 CMOS Inverting Amplifier __________________________________________ 39
5.1.1 Design using FinFET alpha power law model _____________________ 40-41
5.1.1.1 Results _____________________________________________ 41-42
5.1.2 Design using gm/ID technique __________________________________ 42
5.1.2.1 Results _______________________________________________ 43
5.2 Single stage Miller OP-AMP with resistive load _________________________ 44
5.2.1 Design using gm/ID technique __________________________________ 45
5.2.2 Results __________________________________________________ 46-48
5.3 Two stage Miller OP-AMP________________________________________ 48-50
5.3.1 Design using gm/ID technique ________________________________ 50-51
5.3.2 Results __________________________________________________ 52-53
6 Conclusion and future work __________________________________________ 54
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List of abbreviations & Symbols
= Intrinsic gate capacitance
ID = drain current,
= mobility of electrons(or holes in case of PMOS),
= drain-source voltage,
= gate-source voltage,
Cox = oxide capacitance per unit area,
Vdsat = drain saturation voltage,
Vth = threshold voltage of transistor,
W = width of MOSFET,
L = length of MOSFET.
Vov = Overdrive voltage
= channel length modulation parameter
KB = Boltzmann constant
T = Temperature
ro = output resistance
ft = transit frequency
VT = Thermal voltage
CL = Load capacitance
CC = Compensation capacitance
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LIST OF FIGURES
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Fig. 4.1 ID vs VGS for NMOS transistor with aspect ratio W/L = 6/100nm ______ 35
Fig. 5.1 Schemetic of CMOS Inverting amplifier(Inverter) ____________________ 39
Fig. 5.2 DC Characteristics of Inverter[FinFET model]_______________________ 41
Fig. 5.3 AC Characteristics of Inverter[FinFET model]_______________________ 41
Fig. 5.4 Slew rate Characteristics of Inverter[FinFET model] __________________ 42
Fig. 5.5 AC Characteristics of Inverter[gm/ID method]_______________________ 43
Fig. 5.6 Slew rate Characteristics of Inverter[gm/ID method] __________________ 43
Fig. 5.7 Schemetic of Single stage Miller OP-AMP with resistive load __________ 44
Fig. 5.8 AC Characteristics of Single stage Miller OP-AMP ___________________ 46
Fig. 5.9 Transient Characteristics of Single stage Miller OP-AMP ______________ 46
Fig. 5.10 DC Characteristics of Single stage Miller OP-AMP __________________ 47
Fig. 5.11 Schemetic of two stage Miller OP-AMP___________________________ 48
Fig. 5.12 DC Characteristics of Two stage Miller OP-AMP ___________________ 52
Fig. 5.13 Transient Characteristics of Two stage Miller OP-AMP ______________ 52
Fig. 5.14 AC Characteristics of Two Stage Miller OP-AMP __________________ 53
Fig. 5.15 Slew rate of Two Stage Miller OP-AMP __________________________ 53
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LIST OF TABLES
Table 1 Parameters extracted for Alpha Power Law model of FinFET ___________ 30
Table 2 Comparison of results obtained from FinFET model and gm/ID method ___ 43
Table 3 Results of Single Stage Miller OP-AMP with resistive load _____________ 47
Table 4 Results of Two Stage Miller OP-AMP ______________________________ 51
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