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3, JUNE 2014 1499

A Voltage-Controlled DSTATCOM
for Power-Quality Improvement
Chandan Kumar, Student Member, IEEE, and Mahesh K. Mishra, Senior Member, IEEE

AbstractThis paper proposes a new algorithm to generate ref- In CCM operation, the DSTATCOM cannot compensate for
erence voltage for a distribution static compensator (DSTATCOM) voltage disturbances. Hence, CCM operation of DSTATCOM is
operating in voltage-control mode. The proposed scheme exhibits not useful under voltage disturbances, which is a major disad-
several advantages compared to traditional voltage-controlled
DSTATCOM where the reference voltage is arbitrarily taken as vantage of this mode of operation [13]. Traditionally, in VCM
1.0 p.u. The proposed scheme ensures that unity power factor operation, the DSTATCOM regulates the PCC voltage at 1.0 p.u.
(UPF) is achieved at the load terminal during nominal operation, [2], [8][11]. However, a load works satisfactorily for a permis-
which is not possible in the traditional method. Also, the compen- sible voltage range [14]. Hence, it is not necessary to regulate
sator injects lower currents and, therefore, reduces losses in the the PCC voltage at 1.0 p.u. While maintaining 1.0-p.u. voltage,
feeder and voltage-source inverter. Further, a saving in the rating
of DSTATCOM is achieved which increases its capacity to mitigate DSTATCOM compensates for the voltage drop in feeder. For
voltage sag. Nearly UPF is maintained, while regulating voltage this, the compensator has to supply additional reactive currents
at the load terminal, during load change. The state-space model which increases the source currents. This increases losses in the
of DSTATCOM is incorporated with the deadbeat predictive voltage-source inverter (VSI) and feeder. Another important as-
controller for fast load voltage regulation during voltage distur- pect is the rating of the VSI. Due to increased current injection,
bances. With these features, this scheme allows DSTATCOM to
tackle power-quality issues by providing power factor correction, the VSI is de-rated in steady-state condition. Consequently, its
harmonic elimination, load balancing, and voltage regulation capability to mitigate deep voltage sag decreases. Also, UPF
based on the load requirement. Simulation and experimental cannot be achieved when the PCC voltage is 1 p.u. In the litera-
results are presented to demonstrate the efficacy of the proposed ture, so far, the operation of DSTATCOM is not reported where
algorithm. the advantages of both modes are achieved based on load re-
Index TermsCurrent control mode, power quality (PQ), quirements while overcoming their demerits.
voltage-control mode, voltage-source inverter. This paper considers the operation of DSTATCOM in VCM
and proposes a control algorithm to obtain the reference load
terminal voltage. This algorithm provides the combined advan-
tages of CCM and VCM. The UPF operation at the PCC is

A DISTRIBUTION system suffers from current as well as

voltage-related power-quality (PQ) problems, which in-
clude poor power factor, distorted source current, and voltage
achieved at nominal load, whereas fast voltage regulation is pro-
vided during voltage disturbances. Also, the reactive and har-
monic component of load current is supplied by the compen-
disturbances [1], [2]. A DSTATCOM, connected at the point sator at any time of operation. The deadbeat predictive con-
of common coupling (PCC), has been utilized to mitigate both troller [15][17] is used to generate switching pulses. The con-
types of PQ problems [2][12]. When operating in current con- trol strategy is tested with a three-phase four-wire distribution
trol mode (CCM), it injects reactive and harmonic components system. The effectiveness of the proposed algorithm is validated
of load currents to make source currents balanced, sinusoidal, through detailed simulation and experimental results.
and in phase with the PCC voltages [3][7]. In voltage-con-
trol mode (VCM) [2], [8][12], the DSTATCOM regulates PCC II. PROPOSED CONTROL SCHEME
voltage at a reference value to protect critical loads from voltage
Circuit diagram of a DSTATCOM-compensated distribution
disturbances, such as sag, swell, and unbalances. However, the
system is shown in Fig. 1. It uses a three-phase, four-wire,
advantages of CCM and VCM cannot be achieved simultane-
two-level, neutral-point-clamped VSI. This structure allows
ously with one active filter device, since two modes are inde-
independent control to each leg of the VSI [7]. Fig. 2 shows the
pendent of each other.
single-phase equivalent representation of Fig. 1. Variable is a
switching function, and can be either or depending upon
switching state. Filter inductance and resistance are and ,
Manuscript received April 07, 2013; revised July 23, 2013; accepted
February 28, 2014. Date of publication April 17, 2014; date of current respectively. Shunt capacitor eliminates high-switching
version May 20, 2014. This work was supported by the Department of frequency components.
Science and Technology, India, under Project Grant DST/TM/SERI/2k10/
First, discrete modeling of the system is presented to obtain a
47(G). Paper no. TPWRD-00399-2013.
The authors are with the Department of Electrical Engineering, In- discrete voltage control law, and it is shown that the PCC voltage
dian Institute of Technology Madras, Chennai 600 036, India (e-mail: can be regulated to the desired value with properly chosen pa-
chandan3107@gmail.com; mahesh@ee.iitm.ac.in).
rameters of the VSI. Then, a procedure to design VSI parame-
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org. ters is presented. A proportional-integral (PI) controller is used
Digital Object Identifier 10.1109/TPWRD.2014.2310234 to regulate the dc capacitor voltage at a reference value. Based

0885-8977 2014 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

The equivalent discrete solution of the continuous state is ob-

tained by replacing and as follows:

In (3), and represent the th sample and sampling period,
respectively. During the consecutive sampling period, the value
of is held constant, and can be taken as . After simpli-
fication and changing the integration variable, (3) is written as
Fig. 1. Circuit diagram of the DSTATCOM-compensated distribution system.

Equation (4) is rewritten as follows:


where and are sampled matrices, with a sampling time of

. For small sampling time, matrices and are calculated
as follows:
Fig. 2. Single-phase equivalent circuit of DSTATCOM.

on instantaneous symmetrical component theory and complex
Fourier transform, a reference voltage magnitude generation
scheme is proposed that provides the advantages of CCM at
nominal load. The overall controller block diagram is shown in
Fig. 3. These steps are explained as follows.

A. System Modeling and Generation of the Voltage-Control From (6) and (7), ,
Law , , ,
, and . Hence, the capacitor voltage using
The state-space equations for the circuit shown in Fig. 2 are
(5) is given as
given by

where As seen from (8), the terminal voltage can be maintained at a ref-
erence value depending upon the VSI parameters , , ,
, and sampling time . Therefore, VSI parameters must be
chosen carefully. Let be the reference load terminal voltage.
A cost function is chosen as follows [8]:


The cost function is differentiated with respect to and its

minimum is obtained at


The general time-domain solution of (1) to compute the state The deadbeat voltage-control law, from (8) and (10), is given as
vector with known initial value , is given as follows:


Fig. 3. Overall block diagram of the controller to control DSTATCOM in a distribution system.

In (11), is the future reference voltage which is un- where and are the reference dc bus voltage and max-
known. One-step-ahead prediction of this voltage is done using imum-allowed voltage during transients, respectively. Hence
a second-order Lagrange extrapolation formula as follows:

The term is valid for a wide frequency range [17] and Here, 10 kVA, 650 V, 1, and
when substituted in (11), yields to a one-step-ahead deadbeat or . Using (14), capacitor values are found to be 2630
voltage-control law. Finally, is converted into the ON/OFF and 2152 . The capacitor value 2600 is chosen to achieve
switching command to the corresponding VSI switches using a satisfactory performance during all operating conditions.
deadbeat hysteresis controller [17]. 3) Filter Inductance : Filter inductance should pro-
vide reasonably high switching frequency and a sufficient rate
B. Design of VSI Parameters of change of current such that VSI currents follow desired cur-
rents. The following equation represents inductor dynamics:
DSTATCOM regulates terminal voltage satisfactorily, de-
pending upon the properly chosen VSI parameters. The design
procedure of these parameters is presented as follows.
1) Voltage Across DC Bus ( ): The dc bus voltage is taken
twice the peak of the phase voltage of the source for satisfactory The inductance is designed to provide good tracking per-
performance [19]. Therefore, for a line voltage of 400 V, the dc formance at a maximum switching frequency ( ) which is
bus voltage is maintained at 650 V. achieved at the zero of the source voltage in the hysteresis con-
2) DC Capacitance : Values of dc capacitors are troller. Neglecting , is given by
chosen based on a period of sag/swell and change in dc bus
voltage during transients. Let the total load rating be kVA. (16)
In the worst case, the load power may vary from minimum to
maximum that is, from 0 to kVA. The compensator needs where is the ripple in the current. With 10 kHz and
to exchange real power during transient to maintain the load 0.75 A (5% of rated current), the value of using (16) is
power demand. This transfer of real power during the tran- found to be 21.8 mH, and 22 mH is used in realizing the filter.
sient will result in the deviation of capacitor voltage from its 4) Shunt Capacitor : The shunt capacitor should not
reference value. The voltage continues to decrease until the resonate with feeder inductance at the fundamental frequency
capacitor voltage controller comes into action. Consider that ( ). Capacitance, at which resonance will occur, is given as
the voltage controller takes cycles, that is, seconds to act,
where is the system time period. Hence, maximum energy (17)
exchange by the compensator during transient will be .
This energy will be equal to the change in the capacitor stored For proper operation, must be chosen very small compared
energy. Therefore to . Here, a value of 5 F is chosen which provides an
impedance of 637 at . This does not allow the capacitor
(13) to draw significant fundamental reactive current.

C. Controller for DC Bus Capacitor Voltage The fundamental positive-sequence component of load cur-
Average real power balance at the PCC will be rent , calculated by finding the complex Fourier coefficient,
is expressed as follows:
where , , and are the average PCC power, load
power, and losses in the VSI, respectively. The power available is a complex quantity, contains magnitude and phase angle
at the PCC, which is taken from the source, depends upon the information, and can be expressed in phasor form as follows:
angle between source and PCC voltages, that is, load angle .
Hence, must be maintained constant to keep constant. (23)
The voltage of the dc bus of DSTATCOM can be maintained
at its reference value by taking inverter losses from the Hence, the instantaneous fundamental positive-sequence com-
source. If the capacitor voltage is regulated to a constant refer- ponent of load current in phase- , , is expressed as
ence value, is a constant value. Consequently, is also a
constant value. Thus, it is evident that dc-link voltage can be (24)
regulated by generating a suitable value of . This includes The fundamental positive-sequence component of load currents
the effect of losses in the VSI and, therefore, it takes care of must be supplied by the source at nominal load. Hence, it will
the term in its action. To calculate load angle , the aver- be treated as reference source currents. For UPF at nominal op-
aged dc-link voltage ( ) is compared with a reference eration, the nominal load angle is used. By knowing ,
voltage, and error is passed through a PI controller. The output fundamental positive-sequence currents in phases and can be
of the PI controller, which is load angle , is given as follows: easily computed by providing a phase displacement of
and , respectively, and are given as

where is the voltage error.

Terms and are proportional and integral gains, re-
spectively. must lie between 0 to 90 for the power flow
from the source to PCC. Hence, controller gains must be chosen (25)
When reference source currents derived in (25) are supplied by
D. Proposed Method To Generate Reference Terminal Voltages the source, three-phase terminal voltages can be computed using
Reference terminal voltages are generated such that, at nom- the following equations:
inal load, all advantages of CCM operation are achieved while
DSTATCOM is operating in VCM. Hence, the DSTATCOM (26)
will inject reactive and harmonic components of load current.
To achieve this, first the fundamental positive-sequence com- Let the rms value of reference terminal and source voltages
ponent of load currents is computed. Then, it is assumed that be and , respectively. For UPF, the source current and ter-
these currents come from the source and considered as reference minal voltage will be in phase. However, to obtain the expres-
source currents at nominal load. With these source currents and sion of independent of , we assume the PCC voltage as a
for UPF at the PCC, the magnitude of the PCC voltage is calcu- reference phasor for the time-being. Hence, phase- quantities,
lated. Let three-phase load currents , , and be by considering UPF at the PCC, will be
represented by the following equations:

where represent three phases, is the harmonic Substituting (27) into (26), the phasor equation will be
number, and is the maximum harmonic order. repre-
sents the phase angle of the th harmonic with respect to ref- (28)
erence in phase- and is similar to other phases. Using instan-
taneous symmetrical component theory, instantaneous zero-se- Simplifying the above equation
quence , positive-sequence , and negative-sequence
current components are calculated as follows:
Equating real and imaginary parts of both sides of (29), the
(21) following equation is obtained:

where is a complex operator and defined by . (30)



Fig. 4. Before compensation. (a) Terminal voltages. (b) Source currents.

To remove from (30), both sides are squared and added to

obtain the following:


After rearranging (31), the expression for reference load voltage

magnitude will be


Finally, using from (32), the load angle from (19), and the
phase- source voltage as reference, three-phase reference ter-
minal voltages are given as

Fig. 5. Terminal voltages and source currents using the traditional method.
(33) (a) Phase- . (b) Phase- . (c) Phase- .


The control scheme is implemented using PSCAD software.
Simulation parameters are given in Table I. Terminal voltages
and source currents before compensation are plotted in Fig. 4.
Distorted and unbalanced source currents flowing through the
feeder make terminal voltages unbalanced and distorted. Three
conditions, namely, nominal operation, operation during sag, Fig. 6. (a) Voltage at the dc bus. (b) Load angle.
and operation during load change are compared between the tra-
ditional and proposed method. In the traditional method, the ref-
erence voltage is 1.0 p.u. [2], [8][11], whereas in the proposed shows the dc bus voltage regulated at a nominal voltage of 1300
method, (32) is used to find the reference voltage. V. Fig. 6(b) shows the load angle settled around 8.50 .
Using the proposed method, terminal voltages and source cur-
A. Nominal Operation rents in phases , , and are shown in Fig. 7(a)(c), respec-
Initially, the traditional method is considered. Fig. 5(a)(c) tively. It can be seen that the respective terminal voltages and
shows the regulated terminal voltages and corresponding source source currents are in phase with each other, in addition to being
currents in phases , , and , respectively. These waveforms are balanced and sinusoidal. Therefore, UPF is achieved at the load
balanced and sinusoidal. However, source currents lead respec- terminal.
tive terminal voltages which show that the compensator supplies For the considered system, waveforms of load reactive
reactive current to the source to overcome feeder drop, in addi- power ( ), compensator reactive power ( ), and reac-
tion to supplying load reactive and harmonic currents. Fig. 6(a) tive power at the PCC ( ) in the traditional and proposed

Fig. 9. Phase- source rms currents. (a) Traditional method. (b) Proposed

Fig. 7. Terminal voltages and source currents using the proposed method.
(a) Phase- . (b) Phase- . (c) Phase- . Fig. 10. Phase- compensator rms currents. (a) Traditional method. (b) Pro-
posed method.

the proposed method. Losses in the VSI ( ) represented by

resistance , and rating of VSI ( ) are defined as follows:



Using (34) and (35), VSI losses are reduced by 61.68% and only
Fig. 8. Load reactive power ( ), compensator reactive power ( ), and
61.9% VSI rating is utilized in the proposed method.
reactive power at PCC ( ). (a) Traditional method. (b) Proposed method. In the traditional method, DSTATCOM maintains a load
terminal voltage at 1.0 p.u. For this, it needs to compensate
for the entire feeder drop. Hence, at the steady state, the com-
pensator supplies reactive power to the source to overcome
methods are given in Fig. 8(a) and (b), respectively. In the this drop. However, in the proposed scheme, the compensator
traditional method, the compensator needs to overcome voltage does not compensate for the feeder drop in the steady-state
drop across the feeder by supplying reactive power into the condition. Hence, a lesser rating of VSI is utilized in the steady
source. As shown in Fig. 8(a), reactive power that is supplied state. This savings in rating is utilized to mitigate deep sag, and
by the compensator and has a value of 4.7 kVAr is significantly DSTATCOM capacity to mitigate deep sag increases.
more than the load reactive power demand of 2.8 kVAr. This
additional reactive power of 1.9 kVAr goes into the source.
B. Operation During Sag
This confirms that significant reactive current flows along the
feeder in the traditional method. However, in the proposed To create sag, source voltage is lowered by 20% from its nom-
method, UPF is achieved at the PCC by maintaining suitable inal value at 0.6 s as shown in Fig. 11(a). Sag is removed
voltage magnitude. Thus, the reactive power supplied by the at 1.0 s as shown in Fig. 11(b). Since voltage regulation
compensator is the same as that of the load reactive power de- capability does not depend upon reference voltage, it is not
mand. Consequently, reactive power exchanged by the source shown separately for the traditional method. Fig. 11(c) and (d)
at the PCC is zero. These waveforms are given in Fig. 8(b). shows terminal voltages regulated at their reference value.
Fig. 9(a) and (b) shows the source rms currents in phase- The controller provides a fast voltage regulation at the load
for the traditional and proposed methods, respectively. The terminal. Fig. 11(e) and (f) shows the total dc bus voltage
source current has decreased from 11.35 to 10.5 A in the and the load angle, respectively. During the transient period,
proposed method. Consequently, it reduces the ohmic losses capacitors supply real power to maintain load power which
in the feeder. Fig. 10(a) and (b) shows the compensator rms results in discharging of capacitors. Consequently, increases
currents in phase- for the traditional and proposed methods, to draw more power from the source compared to normal
respectively. The current has decreased from 8.4 to 5.2 A in operation. After some time, the dc bus voltage again reaches

Fig. 12. (a) Source voltages. (b) Terminal voltages. (c) Voltage at the dc bus.
(d) Compensator rms current in the proposed method.

Fig. 11. (a) Source voltages during normal to sag. (b) Source voltages during
sag to normal. (c) Terminal voltages during normal to sag. (d) Terminal voltages
during sag to normal. (e) Voltage at the dc bus. (f) Load angle. (g) Compensator
rms current in the traditional method. (h) Compensator rms current in the pro- Fig. 13. Terminal voltage and source current in phase- during load change.
posed method. (a) Traditional method. (b) Proposed method.

the reference voltage whereas the load angle settles down at The terminal voltages, maintained at the reference value, are
17.4 . However, the load angle again settles down at nominal shown in Fig. 12(b). The voltage across the dc bus is shown
value once the sag gets cleared. Compensator rms currents in Fig. 12(c). During transients, this voltage deviates from its
in the traditional and proposed method in phase- are shown reference voltage. However, it is brought back to the reference
in Fig. 11(g) and (h), respectively. In the proposed method, value once steady state is reached. Fig. 12(d) shows the phase-
compensator rms current has decreased to 21.3 from 24.8 A. rms compensator current which is large, nearly 47 A, during
Loss reduction and percentage loss reduction in the VSI are the sag period. These waveforms confirm that the DSTATCOM
given as has the capability to mitigate deep sag independent of duration.
However, it requires a high current rating of the VSI.

C. Operation During Load Change

To show the impact of load changes on system performance,
load is increased to 140% of its nominal value. Under this condi-
Also, savings in utilization of the VSI rating will be tion, the traditional method gives less power factor as the com-
pensator will supply more reactive current to maintain the ref-
erence voltage. The voltage and current waveforms, as shown
in Fig. 13(a), confirm this. In proposed method, a load change
If the rating of VSI is limited to mitigate 20% sag, then this will result in small deviation in terminal voltage from its refer-
savings in rating can be used to mitigate additional sag. ence voltage. Compensator just needs to supply extra reactive
To show the capability of DSTATCOM to mitigate deep sag current to overcome this small extra feeder drop, hence, nearly
for a longer time, the source voltage is decreased to 60% of the UPF is maintained while regulating the terminal voltage at its
nominal value for 1 to 3 s duration as shown in Fig. 12(a). reference voltage. It is evident from Fig. 13(b).

Fig. 16. Experimental results with the proposed scheme.

Fig. 14. Experimental results without the compensator.

Fig. 17. Experimental results before, during, and after sag.

Fig. 15. Experimental results with the traditional scheme.

A voltage sag of 20% is created by using a programmable

IV. EXPERIMENTAL RESULTS ac power source. Fig. 17 shows the source voltage, terminal
The proposed idea and control strategy are experimentally voltage, dc-link voltage, and injected filter current waveforms
verified on a reduced scale setup. To implement the algorithm, before, during, and after the sag. It is seen that the terminal
the digital signal processor (DSP) TMS320F2812 interfaced voltage is sinusoidal and maintained at the reference voltage be-
with the host computer is used. fore, during, and after the sag without any significant transient.
Fig. 14 shows the uncompensated waveforms which include Hence, the proposed scheme is able to provide fast voltage reg-
source voltage ( ), terminal voltage ( ), and source current ulation. During voltage sag, the dc link supplies real power to
( ). It is seen that the distorted source current flowing through the load which results in discharging of the capacitor; hence,
the feeder makes the terminal voltage distorted. voltage decreases. However, the PI controller acts to bring back
First, the DSTATCOM operates with the traditional method voltage at the reference value. Once sag gets cleared, voltage
and the obtained results are shown in Fig. 15. It shows terminal is slowly brought back to its reference by controlling the load
voltage ( ), source current ( ), load current ( ), and in- angle. Injected filter current ( ) increases rapidly to support
jected current ( ). Here, is sinusoidal even though is the terminal voltage during the sag period, as shown in Fig. 17.
distorted, implying that the compensator supplies reactive and Injected and source currents will be more when the reference
harmonic component of . However, it can be noticed that voltage is set to 1.0 p.u. It will result in more losses; however,
the leads , indicating that the compensator supplies addi- they are not shown here.
tional reactive current to overcome feeder drop as well. The experimental results are quite consistent with the simu-
Fig. 16 shows the waveforms with the proposed scheme. lation results. They establish the effectiveness of the proposed
Here, is a sinusoidal waveform in phase with . Hence, control algorithm.
the compensator supplies only reactive and harmonic compo-
nent of . It provides the advantages of CCM. The difference V. CONCLUSION
between injected currents in Figs. 15 and 16 can be obtained In this paper, a control algorithm has been proposed for the
by observing their peak-to-peak or rms values. The rms value generation of reference load voltage for a voltage-controlled
of the injected current is reduced to 0.54 A from 0.76 A in DSTATCOM. The performance of the proposed scheme is com-
the proposed scheme compared to the traditional scheme. In pared with the traditional voltage-controlled DSTATCOM. The
addition, source current is also reduced to 1.86 A from 1.98 A proposed method provides the following advantages: 1) at nom-
in the proposed scheme. This results in the reduction of losses inal load, the compensator injects reactive and harmonic com-
in the VSI as well as in the feeder. Therefore, the capability of ponents of load currents, resulting in UPF; 2) nearly UPF is
DSTATCOM to mitigate deep sag is increased. maintained for a load change; 3) fast voltage regulation has been

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