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Procedia Technology 25 (2016) 574 581

Global Colloquium in Recent Advancement and Effectual Researches in Engineering, Science and
Technology (RAEREST 2016)

A Low Power Reconfigurable Encoder for Flash ADCs

a b
Dr. George Tom Varghese , Prof. Dr. Kamalakanta Mahapatra
a
Associate Professor, Dept of ECE, St.Josephs College of Engineering and Technology, Palai 686579, India

b
H.O.D,, Dept of ECE, National Institute of Technology, Rourkela , 769008, India

Abstract

The present analysis suggests a competent low power thermometer code to binary code converter anticipated for a 3 GS/s five bit
flash analog to digital converter. The speed and power are the bottle neck parameters in the design of thermometer to binary code
converter. With the aim of medium speed and low power dissipation, the first stage of encoder is designed using dynamic logic.
To make the code more resilient to bubble errors, the last stage is designed in wallace tree fashion with the help of four full
adders. With the use of CADENCE tool, the proposed encoder is designed using 90 nm technology with a power supply of 1.2 V.
The simulation results shows that maximum operating frequency of 3 GHz can be accomplished with a power dissipation of
2.424 mW which is a less value in comparison with other methods of implementation. The reconfigurable property of the
proposed encoder makes it useful in reconfigurable flash ADCs.
2016
2015TheTheAuthors.
Authors.Published
Published byby Elsevier
Elsevier Ltd.Ltd.
This is an open access article under the CC BY-NC-ND license
Peer-review under responsibility of the organizing committee of RAEREST 2016.
(http://creativecommons.org/licenses/by-nc-nd/4.0/).
Peer-review under responsibility of the organizing committee of RAEREST 2016
Keywords: Analog to digital Converter, Flash ADC, Dynamivc Logic

1. Introduction

Analog to Digital Converter (ADC) plays an important role in digital signal processing systems. The main
challenges of designing ADC for system on chip applications are high speed, low voltage, and low power
consumption. Reducing the power consumption is a major concern in a portable device. Low power techniques are
applied to prolong the battery life of a system. Similarly ADCs also require a low power technique in the design to
reduce the total power consumption of ADC. Speed, power dissipation and resolution are the three crucial
parameters the design of any ADC which cannot be changed once the design is complete. In wireless and mobile
communication applications require a high speed ADC with low resolution. In these applications, flash ADC is the
most suitable ADC because of its parallel operation. The complete conversion is done in a single cycle with the help
of a large number of comparators.

2212-0173 2016 The Authors. Published by Elsevier Ltd. This is an open access article under the CC BY-NC-ND license
(http://creativecommons.org/licenses/by-nc-nd/4.0/).
Peer-review under responsibility of the organizing committee of RAEREST 2016
doi:10.1016/j.protcy.2016.08.147
 George Tom Varghese and Kamalakanta Mahapatra / Procedia Technology 25 (2016) 574 581 575

Fig. 1 illustrates the structural design of a typical flash ADC. This architecture requires 2 n-1 comparators for the
operation. For example, a group of 31 comparators are required for a five bit flash ADC. The exponential increase of
the number of comparators in flash ADC leads to a large die size as well as large power consumption in a chip. The
reference voltage of each comparator is provided by an external reference source. The reference voltages are equally
spaced between largest reference voltage and the smallest reference voltage. A common analog input is connected to
all the comparators used in flash ADC. Since all the comparators are functioning in parallel way, the output is
produced in a single cycle. The digital output of the comparators is coming in a specific manner which is called
thermometer code. The thermometer code is converted into binary code with the help of thermometer to binary code
converter [1].
The speed and power of an encoder play an important role in the design of flash ADC. The proposed encoder
utilizes the properties of logic style implementation and wallace tree implementation. In order to reduce the power
dissipation, the logic implementation is done with the use of dynamic logic [3]. To make the code more defiant to
bubble error, last stage is implemented using wallace tree encoder. The present investigation is described as follows.
The encoder design explains comprehensively in section 2. The method of implementation is described in section 3.
Reconfigurable property of encoder is briefly explained in section 4. Simulation results, comparison and conclusion
are provided in the succeeding sections.

Fig. 1 Architecture of Flash ADC

2. Design Of The Proposed Encoder

Error handling capability and power dissipation are two vital parameters in the design of thermometer to binary code
conversion. Offset voltage in the comparator creates bubble error in the thermometer code. There are mainly two
methods to minimize the effect of bubble errors. The first method is to convert the thermometer code to gray code
(intermediate step) and then convert to binary code [7]. But the accuracy of the gray code decreases steadily as more
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number of bubble errors is present in the thermometer code. The second method is the use of wallace tree encoder
for the implementation. This technique offers a high robustness to bubble error and stuck at fault error because of its
inherent global bubble error correction/suppression capability [6]. The disadvantage of this method is the large delay
of the encoder. With the purpose of maintaining medium speed and low power dissipation with small amount of
bubble error, the first stage of encoder is designed using dynamic logic [3] and the last stage is designed by wallace
tree encoder style. In the first stage, conversion of thermometer code into two different four bit binary codes is done.
With the help of four full adders and two different four bit binary codes, the final binary code is designed. The truth
table which relates the thermometer code and binary code is presented in table 1. The design equations are shown
below. The equations are imitative from the truth table.
b3 T8
b2 T4 x T8  T12
b1 T2 x T4  T6 x T8  T10 x T12  T14
b0 T1 x T2  T3 x T4  T5 x T6  T7 x T8  T9 x T10  T11 x T12  T13 x T14  T15 (A)

a3 T24
a2 T20 x T24  T28
a1 T16 x T20  T22 x T24  T26 x T28  T30
a0 T17 x T18  T19 x T20  T21 x T22  T23 x T24  T25 x T26  T27 x T28  T29 x T30  T31

The final stage of conversion is shown in Fig. 2.

B4 B3 B2 B1 B0 Thermometer Code
0 0 0 0 0 0000000000000000000000000000000
0 0 0 0 1 0000000000000000000000000000001
0 0 0 1 0 0000000000000000000000000000011
0 0 0 1 1 0000000000000000000000000000111
0 0 1 0 0 0000000000000000000000000001111
0 0 1 0 1 0000000000000000000000000011111
0 0 1 1 0 0000000000000000000000000111111
0 0 1 1 1 0000000000000000000000001111111
0 1 0 0 0 0000000000000000000000011111111
0 1 0 0 1 0000000000000000000000111111111
0 1 0 1 0 0000000000000000000001111111111
0 1 0 1 1 0000000000000000000011111111111
0 1 1 0 0 0000000000000000000111111111111
0 1 1 0 1 0000000000000000001111111111111
0 1 1 1 0 0000000000000000011111111111111
0 1 1 1 1 0000000000000000111111111111111
1 0 0 0 0 0000000000000001111111111111111
1 0 0 0 1 0000000000000011111111111111111
1 0 0 1 0 0000000000000111111111111111111
1 0 0 1 1 0000000000001111111111111111111
1 0 1 0 0 0000000000011111111111111111111
1 0 1 0 1 0000000000111111111111111111111
1 0 1 1 0 0000000001111111111111111111111
 George Tom Varghese and Kamalakanta Mahapatra / Procedia Technology 25 (2016) 574 581 577

1 0 1 1 1 0000000011111111111111111111111
1 1 0 0 0 0000000111111111111111111111111
1 1 0 0 1 0000001111111111111111111111111
1 1 0 1 0 0000011111111111111111111111111
1 1 0 1 1 0000111111111111111111111111111
1 1 1 0 0 0001111111111111111111111111111
1 1 1 0 1 0011111111111111111111111111111
1 1 1 1 0 0111111111111111111111111111111
1 1 1 1 1 1111111111111111111111111111111

Table1. Five bit binary Encoder truth table

Fig. 2 Final Stage Implementation using Full Adders

3. IMPLEMENTATION OF PROPOSED ENCODER

There are different methods to implement the design equations for the conversion of thermometer code to binary
code. Static CMOS, pseudo NMOS, dynamic logic are the different logic styles used for the implementation. Static
CMOS implementation is having low power dissipation with very low speed and large number of transistors. Pseudo
NMOS logic style consumes more power with a good speed of operation and less number of transistors. Dynamic
logic style implementation operates with a medium speed with low power dissipation. With the intention of
achieving low power with medium speed, the implementation is done using dynamic logic [7].
The dynamic logic completes its operation in two phases [3]. The first phase is called precharge and the second
phase is evaluation. In the pre-charging phase (when CLK=0), the output node is charged to the supply voltage
irrespective of any condition through PMOS pull-up transistor. During this time, the pull down path is disconnected
from the supply voltage because of the presence of NMOS transistor whose gate is connected to clock input. In the
evaluation phase (CLK=1), the pull-up path is switched off and pull down path is discharged conditionally based on
the inputs. So the static power dissipation is avoided in the implementation, since pull-up as well as pull down path
is not switching on simultaneously. The important thing in the design of dynamic logic is that during the evaluation
phase, the input to the gate has to make at most one transition. The schematic implementation of the first stage is
shown in Fig. 3(a, b, c, d). The implementation is shown only for b 3, b2, b1 and b0. Similarly a3, a2, a1 and a0 are
designed. The output of the first stage is connected to an array of four full adders which are connected in a
sequential manner. The full adder cell is designed using dynamic logic. The schematic implementation is shown in
Fig. 4. This will reduce the overall speed of operation with minimization of bubble errors. Wallace tree encoder
counts the number of ones present at its inputs and encodes them into binary format. This style of implementation
provides global bubble error correction/suppression without any extra circuitry. The full adder is also implemented
using dynamic logic style.
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Fig. 3(a) Schematic Implementation of b3 using Dynamic Logic

Fig. 3(b) Schematic Implementation of b2 using Dynamic Logic

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Fig. 3(c) Schematic Implementation of b1 using Dynamic Logic

Fig. 3(d) Schematic Implementation of b0 using Dynamic Logic

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Fig. 4(a) Schematic Implementation of Sum in a Full Adder using Dynamic Logic

Fig. 4(b) Schematic Implementation of Carry in a Full Adder using Dynamic Logic

4. RECONFIGURABLE PROPERTY OF THE PROPOSED ENCODER

There are two methods to design the proposed encoder to work as a four bit binary encoder. The first method is by
making a3, a2, a1, a0 and T16 as zeroes. The output will be five bit with MSB as zero. The carry output of the full
adder is always zero which propagates to the next stage. So the final output will be same as b 3, b2, b1, b0. This
method is the most desirable one because all the inputs of the encoder are connected to some specific value. The
second method is to take the output from b3, b2, b1 and b0 and neglect all other inputs. The disadvantage of this
method is many inputs of the encoder are left unconnected. So any noise signal can be easily coupled to the
unconnected inputs that will propagate to the output and make the output erroneous.

5. SIMULATION RESULTS AND DISCUSSION

The proposed encoder is designed and tested for all the input combinations from the truth table. Result is verified
with the help of the truth table. The simulation result is shown in Fig. 5. It shows that the encoder can be operated at
frequency of 3GS/s with a power dissipation of 2.424 mW [5]. The proposed encoder is compared with other types
of encoders. The comparison table (Table 2) shows that the proposed encoder is having medium speed of operation
with low power dissipation. The reconfigurable capability of the proposed encoder makes this encoder design
adaptable to reconfigurable flash ADC architecture [4, 6].
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Fig. 5 Proposed Encoder Simulation

Results Current Mode [8] Proposed

Logic Encoder [2] Encoder
Architecture Flash Flash Flash
Resolution 4 bits 4 bits 5 bits
Technology 180 nm 180 nm 90 nm
Sampling Frequency 5 GHz 2.5 GHz 3 GHz
Vdd 1.8 V 1.8 V 1.2 V
Current 2.22 mA 3.055 mA 2.02 mA
Power Dissipation 4 mW 5.5 mW 2.424 mW
Table 2. Summary and Comparison with other encoders

6. CONCLUSION

The speed and power dissipation are the two vital parameters in the design of thermometer code to binary code
converters in flash ADCs. With the intention of maintaining a medium speed with lower power dissipation, the first
stage of encoder is designed using dynamic logic and the second stage by wallace tree style. The inherent property
of bubble error correction/suppression makes the encoder more resistant to bubble errors. The reconfigurable
property of the encoder makes it to use in reconfigurable flash ADCs. By the help of CADENCE tool, the proposed
encoder is designed and simulated using 90 nm technology with a supply voltage of 1.2 V.
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