(AUTONOMOUS)

Affiliated to JNTUH, Hyderabad

ASSIGNMENT QUESTION BANK

Name of the subject: VLSI DESIGN

Subject Code: A1429
Semester: VI
Elective for Electrical and Electronics Engineering

PART-A (2 Mark Questions)

Unit-I
1. What is Body Effect? Draw neat diagram?
2. What is the difference between ASIC and FPGA Design?
3. Draw the basic nMOS enhancement mode transistor? With neat diagram
4. Write down the below Delay Definitions
i) tpdr ii) tpdf
5. What is mean by the Channel Length Modulation?
6. Explain the terms
i) Accumulation ii) Depletion Mode
7. Draw the terminal voltages of the nMOS Device?
8. Draw the transistor circuit symbols?
9. Draw the nMOS Cutoff region with neat diagram?
10. Draw the basic nMOS depletion mode transistor? With neat diagram
11. What are the two common techniques used for the adjustment of the threshold voltage.
12. Draw the graphical derivation of inverter characteristic (load line).
13. What is mean by an Inversion layer in a n-transistor and draw the neat diagram for it.
14. What are the equations for the Cutoff, Linear, and Saturated regions?
15. Draw the V-I Characteristics for n- and p-transistors.
16. What is equation to find the charge moving is in the channel?
17. Draw the Physical structure of pMOS transistor. With neat diagram.
18. How much noise can a gate input see before it does not recognize the input?
19. Draw the CMOS inverter DC transfer characteristic and operating regions.
20. Draw the Pass transistor circuits with neat diagrams.
Unit-II
1. Draw the visualization the Oxide growth process.
2. Write short notes on
i) Wet oxidation
ii) Dry oxidation
iii) Atomic layer deposition(ALD)
3. Explain the importance of silicon Ntride in IC processing.
4. What is an Ion implantation draw neat diagram
5. Draw a neat diagram for photolithography.
6. Explain about Epitaxy in CMOS processing technology.
7. When will be the CMOS Latchup effect can occur?
8. What the basic raw material for making a Chip. What is the melting point (0C)
9. Find out diameter and thickness of the wafer roughly.
10. What is mean by a Technology explain with example
11. List out the four dominant CMOS technologies?
12. Draw the CMOS Process cross-section and layout conventions
13. What is the best possible metal for interconnect? Why isnt it used
14. Draw neat diagram for a typical metal fuse?
15. Write short notes on
iv) Wet oxidation
16. Step in the process is to form the Gate oxide for the transistor (SiO2).
17. What is meant by Antenna Rules with example?
18. List out the basic CMOS technology define each one.
19. Explain the transmission gate operation?
20. Draw the characteristic of Latch-up current versus voltage.
Unit-III
1. What is mean by a Stick diagram? What is the main use of it?
2. Explain about transistor design rules for nMOS.
3. Draw the Stick diagram and layout for nMOS Shift register Cell with neat diagram.
4. Explain what is mean by Sheet Resistance (Rs), draw the Sheet resistance model.
5. Calculate the Inverter resistance Calculation with neat diagram.
6. What is meant by Scaling and give the names of three Scaling models generally used
7. Derive the Scaling factor for Current Density in constant voltage scaling model.
8. Draw a Transistor related design rules (Orbit 2 m CMOS) minimum sizes and overlaps.
9. What is mean by a Yield? How you justify
10. Draw the aspects of -based design rules for contacts, including some factors contributing to
higher yield/reliability.
11. What mean by Wiring Capacitance explain neatly with diagram.
12. Provide scaling factors for gate area, gate delay, sat current
13. Explain the terms
i) Rise time ii) Fall time iii) Delay time
14. Draw the circuit schematic and stick diagram of CMOS 1-input NOT gate.
15. Explain the double metal MOS process rules.
16. Draw a sheet resistance concept applied to MOS transistors and inverters with neat diagram
17. Find out the importance of 2m Double metal Double poly CMOS rules.
18. Explain about the transistor design rules for CMOS.
19. Draw a stick diagram of p-well CMOS inverter design.
20. Draw the stick diagram of E = AB + CD
Unit-IV
1. How many CMOS are required to design a AND gate. Draw neat diagrams
2. What is the difference between Pull-up and Pull-down circuits?
3. Mention the different types of alternate gate circuits available
4. What is the concept of Charge sharing with respect to Dynamic CMOS logic circuit
5. Draw the basic block diagram of representation of pseudo nMOS logic specifying pull-up and
pull-down circuits.
6. Mention the limitation of CMOS Domino Logic.
7. Draw pseudo nMOS NOR gate and give the number of transistor required.
8. Draw the basic block diagram of representation of Dynamic CMOS logic specifying pull-up
and pull-down circuits.
9. Mention the drawback of using Pass transistor Logic.
10. What is purpose of using alternate gate circuits.
11. What is mean by Domino Logic Stage?
12. Explain what is mean by pseudo logic circuit.
13. Draw the Dynamic CMOS logic Circuit
14. Draw the complementary pass- Transistor logic with neat diagram.
15. Explain the importance of Pass transistor in VLSI design
16. Draw the circuit diagram for a dynamic logic gate that has an output of F = a.(b + c + d)
17. Design a tri-state circuit that is in a high-impedance state when the control signal T = 1, and
acts as a non-inverting buffer when T = 0.
18. Explain the Power Dissipation of Dynamic logic circuits.
19. Explain the pseudo nMOS logic with example.
20. Draw a Layout for a domino AND gate.
Unit-V
1. Draw the visualization of Wafer testing scheme and draw the Bathtub reliability curve
2. Draw the Circuit to Logic model and Boolean Logic with neat diagrams

3. Explain the importance of Observability and Controllability

4. Draw the CMOS bridging faults with neat diagram.
5. Define
i) Short-circuit
ii) Open-circuit Faults
6. What is mean by Delay Fault Testing draw neat diagram
7. Draw of Stuck-at fault effects for primitive logic gates with neat diagrams
8. What is mean by Ad hoc testing?
9. Draw the Circuit to Logic model and Boolean Logic with neat diagrams

10. Draw the delay fault model with neat diagram.

11. Explain any one of the method of testing bridge faults with neat diagram.
12. Why the chip testing is needed. At what levels testing a chip can occur.
13. Draw an example of a delay fault with neat diagram
14. Write short notes on
i) BIST
ii) ATPG
iii) ATE
15. Draw a Instruction bit implementation diagram
16. How are the sequential faults caused in CMOS? Give an example.
17. You have to test a large die (1cm X 1cm) that is housed in a package that costs $5. Would
you do wafer testing? Why?
18. Explain what is meant by a Stuck-at-1 fault and a Stuck-at-0 fault.
19. Explain the principles of Built-In Self-Test (BIST). What are the advantages and
disadvantages of BIST?
20. Draw the block diagram of Test-data registers.
PART-B (5 Mark Questions)
Unit-I
1. Draw a CMOS Inverter. Explain its transfer characteristics?
2. Explain the Enhancement Mode Transistor for particular values for V ds with (Vgs>Vt)
3. Consider a gate oxide that has a thickness of tox=50 A =50x10-8 cm. The oxide capacitance
per unit area is
4. Explain the DC Response of the in an Inverter circuits design? Response for Vout vs Vin.
5. Derive the equation for the Cutoff, Linear, Saturated region for nMOS transistors with neat
explanation
6. Draw a table for summary of CMOS inverter operation.
7. Explain the Noise Margin with neat block diagram and define NML and NMH.?
8. Draw the tri-state inverter circuit diagram explain with neat block diagram.
9. Explain the MOS Capacitance with various operating modes with neat block diagrams?
10. Draw the nMOS transistor structure and Drain-To-Source Current Ids versus Voltage Vds
Relationships.?
11. Draw the Block Diagram of the pMOS and nMOS transistor switches and explain the
switching activity in for both MOS transistors?
12. a) What is truth table for Inverter design? Construct the CMOS inverter with neat diagram
b) Explain the concept of channel length modulation and body-effect with respect to MOS
transistors.
13. Design a 2-bit AND gate by using nMOS and pMOS. To what conclusions do you come?
14. Draw the Conduction characteristics for enhancement and depletion mode transistor
(assume fixed Vds).
15. What are the parameters are including in the threshold voltage (Vt). Explain the each of
them.
16. Draw the nMOS device behavior under the influence of different terminal voltages, explain
with near diagrams
17. Make a table Relations between voltages for the three regions of operation of a CMOS
inverter
18. Explain the complementary inverter of DC-Characteristics with near graph?
19. Find out in Linear region ,Ids depends on
How much charges are in the channel?
How fast is the charge moving?
20. Draw the neat diagram for the effect of substrate bias on series connected transistors.
Unit-II
1. Write short notes on the following processes. a) Oxidation b) Encapsulation
2. Draw the Si wafer design process with neat steps and neat block diagram
3. What is difference between die and core and wafer explain with neat block diagrams
4. Define latch up. Explain latch-up in CMOS circuits. Also provide the ways to reduce latch
up.
5. What is meant by lithography process? Briefly explain different types of lithography
processes.

6. Derive pull-up to pull-down ratio for an NMOS inverter driven through one or more pass
transistor.
7.
8. Explain the design flow involved in VLSI. Explain each stage in detail.
9. With a neat sketch explain CMOS inverter Analysis by indicating all the operating
regions.
10. Mention different types of CMOS processes available. Explain the CMOS twin tub process
and its characteristics with neat diagrams.

11. How is an nMOS transistor fabricated? Explain with neat sketches.

12. Explain with diagrams, the main steps in the twin-tube process.
13. Explain the fabrication steps in P-well CMOS fabrication
14. Draw the CZOCHRALSKI Process for manufacturing silicon for wafer processing? With neat
diagram.
15. Show a diagram of an nMOS transistor showing the growth of field Oxide in both Vertical
 Direction.
16. Draw the layout for a pMOS transistor in an n-well process that has active, p-select, n-select,
polysilicon, contact, and metal1 mask1 masks. Include the well contact to VDD
17. Explain the difference between a polycide and a salicide CMOS process. Which would be
likely to have higher performance and why?
18. Design a metal6 fuse ROM cell in a process where the minimum metal width is 0.5 m and
the maximum current density is 2 mA/m. A fuse current of less than 10 mA is desired.
19. Draw the Latch-up effect in p-well structure with neat explanation. And draw the Latch-up
circuit model.
20. Using Table, calculate the minimum unconnected and contacted transistor pitch as shown in
figure

Unit-III
1. Sketch a 3-input gate with transistor widths chosen to achieve effective rise and fall resistance equal
to that of a unit inverter (R)
2. Figure 1 shows a layout of the 3-input NAND gate. A single drain diffusion region is shared
between two of the pMOS transistors. Estimate the actual diffusion capacitance from the
layout
3. A ring oscillator is constructed from an odd number of inverters, as shown in figure.
Estimate the frequency of an N-stage ring oscillator.
4. For much of the history of CMOS design, power was a secondary consideration behind
speed and area for many chips. So explain the importance of Power Dissipation CMOS
circuits.
5. A digital system in a 1.2 V 100nm process has 200 million transistors, of which 20 million are
in logic gates and the remainder in memory arrays. The average logic transistor width is 12
and the average memory transistor width is 4 . The process has two threshold voltages
and two oxide thickness. Sub threshold leakage for OFF devices is 20nA/m for thin oxides
and 0.002 nA/m for thick oxide. Memories us low-leakage device everywhere. Logic uses
low-leakage device in all but 20% of the paths that are most critical for performance. Diode
leakage is negligible. Estimate the static power consumption. How would the power
consumption change if the low-leakage device were not available?
6. Consider a 5mm long, 0.32 m wide metal2 wire in a 180 nm process. The sheet resistance
is 0.05 and the capacitance is 0.2fF/m. Construct a 3-segment -model for the wire.
7. Find the worst-case Elmore parasitic delay of an n-input NOR gate.
8. Estimate the delay of the fanout-of-4(FO4) inverter (i.e. an inverter driving four identical
copies) shown in figure. Assume the inverter is constructed in a 180 nm process with =15ps
9. Draw the transistor level diagram for the given expression and also get the corresponding
Stick diagram representation in CMOS logic
Y = a(b + c)+d
10. Draw the transistor level diagram and Layout for XOR gate in CMOS logic
11. Two nMOS inverters are cascaded to drive a capacitive load CL = 16 Cg as shown in figure 1.
Calculate the pair delay (Vin to Vout) in terms of for the inverter geometry indicated in the
figure. What are the ratios of each inverter?
12. Given the -based design rules for different layers, p and n MOSFETS and contact cut.
13. Obtain the stick diagram and layout of a two-way selector with enable?
14. A particular section of layout (as shown in fig) includes a 3 wide metal path which crosses a
2 wide polysilicon path at right angles. Assuming that the layers are separated by a 0.5 m
thick layer of silicon dioxide, find the capacitance between the two layers.

15. Draw the circuit schematic and stick diagram of CMOS 2-Input NAND gate
16. Draw the minimum size MOS inverter pair delay with neat diagram
17. Using the parameters given, calculate the Cin and Cout values of capacitance for the structure
represented in figure 2.

18. Draw a Schematic and Cell Layout with near diagrams?

19. With neat diagram explain - based design rules for contact cuts and Vias.
20. Draw the stick diagram for the NMOS implemented of the Boolean expression Y = AB + C.
Unit-IV
1. Draw the circuit diagram for a dynamic logic gate that has a output of f=a.c+b.a
2. Does the function have the correct symmetry required to build a mirror circuit? If so
construct the logic gate.

a b f
0 0 0
0 1 1
1 0 0
 1 1 1
3. Design a tri-state circuit that is in a high-impedance state when the control signal T=1, and
acts as a non-invertring buffer when T=0.
4. Design a clocked CMOS circuit that implements the function
f=a.(b+c)+x.y
5. Consider the dual expressions
g = x.y+z.w G = (x+y).(z+w)
which form (AOI or OAI) would provide the best performance when built using pseudo-
nMOS design

6. Is the mirror circuit an intelligent design for this situation? Explain

a b f
1 0 0
0 1 1
1 0 0
1 1 1
7. Suppose instead that we use transistors that are the same size the inverter values. Identify
the worst-case nMOS and pMOS paths that will slow down the response.
8. Find the time constant if we ignore C1 and C2. What is the percentage error introduced if
we do not include the internal capacitors?

9. One of your colleagues decides to use a mirror circuit to implement the 2-input function
described in the truth table of Figure

a b f
1 0 0
0 1 1
1 0 0
1 1 1
10. Consider a complex CMOS logic gate the implements the function F = a.b+ c.d.e
11. What is domino CMOS logic? How does it eliminate the issues related to cascading?
12. Explain different types of pseudo-NMOS logic.
13. What is Fan-in and Fan-out? What is the importance of fan-in and fan-out in IC
technology?

14. Sketch a 3-input CMOS NOR gate with neat diagram.

15. Draw the Physical Design of Logic Gate (NOT Cell) by using CMOS logic circuit.
16. Sketch a complementary CMOS gate computing Y = (A + B + D).C
17. What circuit design techniques would you employ to minimize the effect of body effect in p-
well process? In an n-well process?
18. Draw the flow chart for VLSI Design Flow with neat block diagram and explanation.
19. Sketch a complementary CMOS gate computing Y = (A + B + C).D
20. Explain the 2-input X-NOR gate in pass transistor logic.
Unit-V
1. Write an overview of testing problem with neat diagrams
2. What is Gate Level Testing? Explain with neat diagram
3. What is Path Sensitization? Explain with example
4. Explain briefly about manufacturing tests?
5. What is Automatic Test Pattern Generation? Draw neat block diagram
6. Narrate the meaning of Controllability and Observability in VLSI Chip testing.
7. What is delay fault testing? Explain with an example
8. Explain about Scan-design strategy for testing?
9. Explain Serial and Parallel fault simulation techniques with neat block diagram
10. What is the importance of Built-in-Self-Test. Explain about it with neat block diagram
11. Describe the stuck at fault model. What are the different stuck at faults? Explain the
process how to detect a stuck at 0 fault with an example.

12. Explain the following simulation techniques

a) Concurrent fault simulation.

b) Non deterministic fault simulation.

13. Write down the Chip Level Test Techniques with neat diagrams.
14. Write short notes on automatic test pattern generation.
15. Write note on testability and testing with neat diagrams.
16. What is the different scan based test techniques. Explain them briefly
17. Define the term DFT and explain about it. Also mention what is the need to go for testing.
18. List out the differences between self test and built-in test techniques.
19. Draw the basic boundary scan architecture and explain the detailed Test Access Port (TAP)
architecture.
20. Explain the following terms:
i) Controllability,
ii) Observability.