Lect1 Overview

EECT 6378 Power Management Circuits
Lecture 1: Course Overview and

Review on Stability and Frequency Compensation for
Amplifiers
Hoi Lee
Professor
Department of Electrical and Computer Engineering

The University of Texas at Dallas
hoilee@utdallas.edu
Administrative
Course materials are available on eLearning:

Login to https://elearning.utdallas.edu
Class Information
Time: Fridays 1:00 p.m. 3:45 p.m.
Location: JSOM 2.902
TA: Qi Cheng (qxc150030@utdallas.edu)
Professor Office Hours (ECSN 4.512)

Fridays 4:00 p.m. 5:00 p.m. (or by appointment)
EE6378 Lecture 1 pg. 2
1
Grading Policy and Arrangement
The final grade will be determined by the

following formula:
Term Paper (15%) + Final Project (25%) +

First Exam (15%) + Second Exam (15%) +
Third Exam (30%)
First exam is tentatively scheduled on 10/10

Second exam is scheduled on 11/3
Third exam is scheduled on 12/1
Email Use
All course announcements will be only sent

to your UTD email address
Email received should have the subject as
EECT 6378 ***
Example 1: EECT 6378: HW problem
Example 2: EECT 6378: I am sick and cannot
attend your class today
Example 3: EECT 6378: Extension of term
paper deadline
2
Textbook & Reference Books
Textbook
Class notes and research papers (all provided in the course
webpage; Not a single book can cover all materials in the
course)
Reference Books
Analog IC Design with Low Dropout Regulators, by Gabriel
Rincon-Mora, McGraw-Hill Professional Publisher, 2009. (ISBN:
0-071-60893-1)
Pulse-Width Modulated DC-DC Power Converters, by Marian K.
Kazimierczuk, John Wiley & Sons Publisher, 2008 (ISBN: 0-470-
77301-7)
Fundamentals of Power Electronics, 2nd Edition, by R. W.
Erickson and D. Maksimovic, Kluwer Academic Publisher, 2001.
(ISBN: 0-792-37270-0)
Elements of Power Electronics, Philip T. Krein, Oxford University
Press, 1998. (ISBN: 0-135-25643-7)
Course Topics
Main Topics
Review of Stability and Frequency Compensation of Two-Stage

Amplifier
Linear and Low-Dropout Regulators
Advances in Voltage References
Switched-Mode Power Converters
Control Methodologies of Switched-Mode Power Converters
Introduction to Magnetics
Introduction to Switched-Capacitor Power Converters
3
Course Contents
This course mainly covers analysis and design of power

conversion methodologies and controls including the
following topics:
Review on Stability analysis and Frequency compensation
techniques that are useful to understand operation of voltage
regulators.
Different types of DC-DC converters including linear regulators,
switched-mode power converters (SMPC), and switched-capacitor
power converters (SCPC).
Voltage references
We will deal with the power conversion circuits below 10W

range and can be integrated using CMOS transistors.
Prerequisite: EECT 6326 Analog IC

Recommended: EEPE 6354 Power Electronics
Introduction
Power electronics deals with circuits convert electrical

power from one form to another using electronics
devices (power conversion).
The design of power conversion circuits includes many

disciplines from within electrical engineering. This
includes applications of circuit theory, control theory,
electronics, electro-magnetics, power devices, heat
transfer, packaging, etc.
4
Converter Classification
Power management circuits convert one type of a

voltage or current waveform to another, and hence
called converters. Converters are classified by the
relationship between the input and the output:
AC-DC (rectifier): average power is transferred from an ac
source to a dc load.
DC-DC: It converts an unregulated dc voltage or current to a
regulated (specified) dc value with different dc value.
DC-AC (inverter): average power flows from dc side to ac side.
AC-AC: It is used to change the level and/or frequency of an ac
signal.
Power conversion can be a multistage process involving
more than one type of the converter.
Why Power Management Circuits?
Problems:
Input supply voltage is not constant
Current consumption of electronic equipment varies under
different conditions
Performances of internal systems in the equipment are
not consistent under different supply voltages and current
consumptions
Power Management ICs:
Always provide an regulated power source to the
electronic equipment
High power and area efficiencies, and low cost
5
Needs and Features of Portable Devices
Battery-Operated Portable Devices Energy Sources

Li-Ion Batteries
Long Battery Life,

Small Size, Light
Weight, & More
Functions
NiMH /NiCd Batteries
But, Limited
Battery Capacity
Power Management Circuits for Portable

Devices
Provide a regulated power source

Low Dropout Regulator (LDO)
Switched-Inductor DC-DC Regulator (SMPC)
Switched-Capacitor Power Converter (SCPC)
Energy Source
Power Management Circuits (h 1)
Analog Part Digital Part RF Part Interface

Part
6
Types & Comparisons of DC-DC Converters
Types Pros Cons

Highest power
Inductor efficiency Large board space
SMPC
-based Step up / down High conducted EMI
conversion
No step-up conversion
Simplest and lowest
LDO cost Poor efficiency if the
voltage mismatch between
Low output noise input and output is larger
Inductor
-less High switch count
SCPC (or Step up / down
conversion Lack of effective control
Charge Pump
scheme
without Low cost
Regulation) Poor power efficiency in
High energy density
regulator
Applications of Different PMICs in

Cellular Phones
SMPCs
DC-DC conversions from Li-Ion cell battery (nominal 3.6V) to low
supply voltage (1.2V) for internal digital baseband processors
Dynamically adjust supply voltages in RF power amplifier
Linear Regulators (LDOs)
Sensitive RF or audio blocks which have stringent noise and
PSRR requirements
Post-regulators following switching regulators
SC Regulators
LCD displays, backup-battery boost converters, etc.
Lower cost solution to substitute SMPCs as no inductor is
required
7
Combining Power Converters
Different applications have different requirements of output

ripples, power efficiency, etc
Best power efficiency Good power efficiency

Poor output ripple and noise Good output ripple and noise
Very good power efficiency Achieve output regulation

Poor output ripple and noise Good output ripple and noise
No output regulation Poor power efficiency
Integrated DC-DC Converters (1)
Current-mode switched-mode dc-dc

converter (buck converter)
From the chip micrograph:
2 On-chip power transistors
On-chip controller and gate driver
Chip area is dominated by integrated
power transistors
Chip area: 2.87mm2
Technology: AMS 0.6m CMOS
Publication: JSSC Jan. 04
8
Sub-1V current-mode switched-

mode dc-dc converter (boost
converter)
All control circuitries can operate at
sub-1V condition
Much larger chip area is occupied
by power transistors
Chip area: 4.96mm2
Publication: JSSC Nov. 05
Open-loop cross-coupled voltage

doubler
8 on-chip power transistors
Chip area: 3.92mm2
Publication: JSSC May 05
9
Regulated SC dc-dc converter

From the chip micrograph :
8 on-chip power transistors and
all are close to the bonding I/O
pads
On-chip controller
Chip area: 5.47mm2
Publications: ISSCC 05 and
JSSC Jun. 07
Integrated DC-DC Converter (5)
Low-dropout regulator
Main feature:
Has only one on-chip power
transistor
Area is much smaller than SCPC
and SMPC
Chip area: 0.31mm2
Publication: JSSC Oct. 03
10
Voltage References (2)
Accurate CMOS bandgap

reference (high-order curvature)
Main features:
Tempco: 5.3ppm/oC for 0oC to
100oC
Line regulation: 1.43mV/V at 27oC
Supply current: 23A (2V input)
Chip area: 0.057mm2
Publication: JSSC Mar. 03
Voltage References (1)
Sub-1V CMOS bandgap voltage

reference (First-order bandgap)
Main features:
Novel circuit technique to allow sub-
1V operation (min Vin=0.98V) with
|Vthp|=Vthn=0.9V at 0oC
Supply current: 18A
Tempco: 15ppm/oC for 0oC to 100oC
Chip area: 0.24mm2
Publication: JSSC Apr. 02
11
Review on
Poles & Zeros; Bode Plots; and Modeling of
Single and Two-Stage Amplifiers
Transfer Function
Consider a system shown below with an input vi(s) and an

output vo(s) represented by the Laplace transform.
vi(s) System
vo(s)
H(s)
12
Transfer Function (2)
R
A transfer function is defined by
v (s ) vi(s) C vo(s)
H (s ) = o
v i (s )
It is noted that the transfer function is a property of the circuit

and does not depend on the input or the output.
An example of a low-pass filter is shown here. It is given by
ZC =1/sC. The transfer function of the low-pass filter (system)
is given by
1
v o (s ) sC = 1
H (s ) = =
v i (s ) R + 1 1 + sRC
sC
Poles and Zeros
The system described in the previous section may have a

transfer function of very high order:
b + b1s + b2s 2 + ... + bm -1s m -1 + bm s m
H (s ) = 0
a0 + a1s + a2s 2 + ... + an -1s n -1 + an s n
s s s s
H o 1 + 1 + 1 + ...1 +
z1 z2 z3 zm
=

1 + s s s s
1 + 1 + ...1 +
p1 p2 p3 pn
In the transfer function, a1 an and b1bm are the coefficients;
Ho is the low-frequency gain; the zeros (-z1, -z2, -z3,,-zm) are
roots of the numerator, and the poles (p1,-p2,-p3 ,,-pn) are
roots of the denominator. Both pole and zeros are in unit of
radian/sec.
13
Poles and Zeros (2)
For a physical system, all coefficients are real. Hence, the
poles and zeros can have only two forms: (1) the roots are
real, and (2) if one root is complex, its conjugate has to be
another root (e.g. If z1 = -p+jq is a root, then z1* = -p-jq is
another root).
Both poles and zeros can be located in either left half-plane

(LHP) or right half-plane (RHP). When the poles and zeros
locate in LHP, they are negative. However, they are positive
when they locate in RHP.
The system is unstable if there is any RHP pole!
Frequency Responses and Bode Plot
In frequency domain, Bode Plot, which includes both

magnitude plot and phase plot, describes the frequency
response of a system. To draw the frequency response of a
system, the transfer function H(s) is re-written in the polar form:
H(s) = H(s) H(s)
where H(s) and H( s) are the magnitude and phase of

the system, respectively.
14
Frequency Responses and Bode Plot (2)
20log|H(s)| p1 10 p1 2
20log|H(s)| p1 102p1
0.1p1 10p1 103p1 3
0.1p1 10p1 10 p1
0dB w w
0dB
-20dB (log scale) (log scale)
-20dB
-40dB -40dB
-60dB -60dB
2
H(s) Unstable!
H(s) p1 10 p1 3
0.1p1 10p1 10 p1
o
w
o
0 90
o (log scale) o
-45 45
-90
o
0
o
w
0.1p1 10p1 103p1 (log scale)
p1 102p1
1 1
LHP Pole : H (s ) = RHP Pole : H (s ) =
s s
1+ 1-
p1 p1
Frequency Responses and Bode Plot (3)

20log|H(s)| 20log|H(s)|
60dB 60dB
40dB 40dB
20dB
20dB
0dB w w
(log scale)
3 0dB
0.1z1 10z1 10 z1 3 (log scale)
0.1z1 10z1 10 z1
z1 102z1 z1 102z1
H(s)
H(s) z1 102z1
3
0.1z1 10z1 10 z1
90
o
0
o
w
o o (log scale)
45 -45
0
o
w -90
o
0.1z1 10z1 103z1 (log scale)

z1 102z1
s s
LHP zero : H (s ) = 1 + RHP zero : H (s ) = 1 -
z1 z1
15
Modeling of a Single-Stage Amplifier (1)
A single-stage amplifier is modeled using transconductance

modeling shown below.
vo
vi
vi Rin Ro CL vo
Gmvi
CL
vi, vo, Rin, Gm, Ro, and CL are the input signal, output signal,
input resistance, effective transconductance, output
resistance, and loading capacitance, respectively.
The transfer function A(s) is given by solving the nodal

equation of the model:
v (s ) GmRo Ao
A(s ) = o = = 20log|A(s)|
v i (s ) 1 + sRoCL 1 + s
Ao(dB)
p1 GBW
1
where Ao = GmRo and p1 =
RoCL w
are low-frequency voltage gain 0dB p1 (log scale)
and dominant pole, respectively. A(s)
p1 is the -3dB frequency and the w
gain-bandwidth product is given (log scale)
by
o
-90
1 G
GBW = Ao p1 = (GmRo ) ( )= m
RoCL CL
16
The -3dB frequency is the 20log|A(s)|

maximum frequency of the input Ao(dB)
signal that the amplifier retains a GBW
voltage gain Ao (In fact, should
be Ao / 2 ), while the GBW is w
0dB p1 (log scale)
the maximum frequency of the
input signal that amplifier A(s)
provides a voltage gain higher w
than one. In addition, the output (log scale)
o
signal suffers from the phase -90
shift.
Modeling of a Two-Stage Amplifier (1)
A two-stage amplifier can be similarly done by using a

transconductance model shown below.
v1 vo
vi
C1 CL
v1
vi Rin Ro1 C1 vo
Gm1vi Gm2v1 Ro2 CL
17
The transfer function A(s) is given by, again, solving the nodal
equations:
v (s ) Gm1Gm2Ro1Ro 2 Ao
A(s ) = o = =
v i (s ) (1 + sRo 2CL ) (1 + sRo1C1) (1 + s ) (1 + s )
p1 p2
It is generally that C1 is smaller than CL since C1 is due to

internal lumped parasitic capacitances, while CL is due to the
external capacitive load. Thus, p1 locates at a lower
frequency than p2.
From the transfer function, both poles are

LHP poles. As a reminder here, an LHP 20log|A(s)|
-20dB/dec
reduces the magnitude by -20dB/dec and Ao
provides a -90 phase shift.
-40dB/ dec
In the magnitude plot, the gain decreases 0dB w
(log scale)
by -20dB/decade when the frequency p1 p2
reaches p1. When the frequency further
A(s)
increases to p2, the gain drops by -40dB o w
(two times of -20dB) per decade. For the 0 (log scale)
phase, it has totally -180 phase shift due
to the two LHP poles. -180
o
18
20log|A(s)|
As will be discussed in the next -20dB/dec
Ao
chapter, when there are 2 poles
-40dB/ dec
before the unity-gain frequency, the
amplifier is generally unstable. Thus, a0dB w
(log scale)
p1 p2
circuit technique known as frequency
compensation is utilized to stabilize the A(s)
w
amplifier. Particularly, Miller 0
o
(log scale)
Compensation is commonly used in
two-stage amplifier design. o
-180
Extra Notes (-3dB Frequency)

-3dB Frequency
Considering the transfer function of a single-stage amplifier,
the magnitude of the transfer function is given by
Ao
A( jw ) =
w 2
1+ ( )
p1
At the pole frequency (i.e. w = p1), the magnitude is given by
Ao Ao
A( jp1) = =
p 2
1 + ( 1 )2
p1
When the magnitude expressed in dB,
Ao
20 log A( jp1) = 20 log = 20 log Ao - 20 log 2
2

= 20 log Ao - 3dB
19
Extra Notes (-3dB Frequency)
In other words, the magnitude is decreased by 3dB at p1, and

that is why the first-pole frequency is also termed as -3dB
frequency.
It is also noted that the magnitude and phase plots shown

previously are just approximations to predict the frequency
response. The real ones are smooth curves and do not have
sharp change.
Extra Notes (Gain-Bandwidth Product)

Gain-Bandwidth Product
From the previous discussion, the gain-bandwidth product
is defined as GBW = Ao p1
The above relationship holds only when there is only one
pole before the unity-gain frequency. If there is more than
one pole or more than one zero before the unity-gain
frequency, this equation does not hold anymore.
This equation thus holds for the single-stage amplifier as
there is only one pole before the unity-gain frequency. For
uncompensated two-stage (two-poles) or multi-stage
(multi-poles) amplifiers, this relationship does not hold
since there are more than one pole before the unity-gain
frequency.
EE6378 Lecture 1 H. Lee pg. 40
20
Extra Notes (Phase Shift)
Phase Shift
The phase shifts of LHP/RHP pole/zero are shown below
Ho w
1. LHP pole : H (s ) = H ( jw ) = - tan-1( )
s p1
1+
p1
Ho w
2. RHP pole : H (s ) = H ( jw ) = + tan-1( )
s p1
1-
p1
s w
3. LHP zero : H (s ) = Ho (1 + ) H ( jw ) = + tan-1( )
z1 z1
s w
4. RHP zero : H (s ) = Ho (1 - ) H ( jw ) = - tan-1( )
z1 z1
The phase shift is independent of Ho.

Example 1
An amplifier with unity DC gain has first pole at

100kHz, second pole at 1MHz, and a zero at
10MHz. What is the magnitude and phase at
2MHz?
21
Solution to Example 1
An amplifier with unity DC gain has first pole at

100kHz, second pole at 1MHz, and a zero at 10MHz.
What is the magnitude and phase at 2MHz?
s jw jw
1+ 1+ 1+
wz wz 2p * 107
H (s ) = H ( jw ) = =
s s jw jw jw jw
(1 + )(1 + ) (1 + )(1 + ) (1 + )(1 + )
wp1 wp2 wp1 wp2 2p * 10 5
2p * 106
j 2p * 2 * 106
1+
2p * 107 1 + j 0. 2
H (2p * 2 * 106 ) = =
j 2p * 2 * 106 j 2p * 2 * 106 (1 + j 20)(1 + j 2)
(1 + )(1 + )
2p * 105 2p * 106
1 + 0.22
20 log10 H (2p * 2 * 106 ) = 20 log10 = -32.85dB
1 + 202 1 + 22
H (2p * 2 * 106 ) = tan-1(0.2) - tan-1(20) - tan-1(2) = 11.3! - 87.1! - 63.4! = -139!
Review on
Stability & Frequency Compensation of
Two-Stage Amplifiers
22
Simplification for Two-Stage Amplifier
M3 M4 Cm
V1 ML
Vo gm1 gmL
Vin Vo
Cm
-A1 -AL
M1 M2
Vin CL r1 rL CL
C1
Mb2
Mb1 Mb3
Fig. 1 Fig. 2
Fig. 2 is the signal representation of Fig. 1

gm1 (fig. 2) = gm1,2 (fig. 1)
gmL (fig. 2) = gmL (fig. 1)
r1, C1 (fig. 2) = equivalent output resistance (ro2//ro4), capacitance
(Cdtot,M4+Cdtot,M2+Cgtot,ML) at V1 (fig. 1)
rL, CL (fig. 2) = output resistance (roL//rob3), capacitance (CL) at Vo
(fig. 1)
Hybrid-p Model of Two-Stage Amplifier
Cm
Cm
gm1 gmL V1 Vo
Vin Vo
-A1 -AL gmLV 1
gm1Vin r1 C1 rL CL
r1 rL CL
C1
Fig. 1 Fig. 2
Fig. 2 is the hybrid-p model of two-stage amplifier

Hybrid-p model is used to derive small-signal transfer function
(Vo/Vin) of the two-stage amplifier
Small-signal transfer function is a must to understand
frequency compensation
23
Example 1
M3 M4
V1 ML
Vo
Cm
M1 M2
Vin
Mb2
Mb1 Mb3
What are its hybrid-p model and dc gain?
Answer
Cm
V1 Vo
gmLV 1
gm1Vin r1 C1 rL CL
dc gain of the first gain stage is +ve

dc gain of the second gain stage is ve
Overall dc gain=-gm1gmLr1rL (-ve gain!)
24
Why Frequency Compensation?
Cm
V1 Vo
gmLV 1
gm1Vin r1 C1 rL CL
Frequency compensation relates certain circuit specifications with

design parameters
Circuit specifications: unity-gain bandwidth (UGF), phase margin (PM) and
CL
Design parameters: gm1, gmL, Cm
gm I, and area of Cm dominates the chip area of amplifier
Effective frequency compensation not only stabilizes the multistage
amplifier but also optimizes BW and PM by using minimum current
consumption (gm) and smallest chip area (Cm) for a particular CL
DC gain specification decides the values of r1 and rL
Miller Compensation in Two-Stage Amplifier (1)
Cm
V1 Vo Cm
g m1gmL r1rL (1 - s)
gmLV 1 Vo g mL
gm1Vin r1 C1 rL CL =
Vin (1 + sC g r r )(1 + s CL )
m mL 1 L
gmL
Numerator:
DC gain
Zero: (1-as) RHP zero, (1+as) LHP zero
1 RHP zero exits phase margin degradation
Denominator:
Poles: (1+as+bs2+), all terms should be positive (LHP poles);
otherwise amplifier is unstable
2 LHP poles exist
25
Cm
g m1gmL r1rL (1 - s)
DC Gain P-3dB Vo g mL
=
Vin (1 + sC g r r )(1 + s CL )
m mL 1 L
-20dB/decade gmL
0dB
s DC Gain = gm1gmLr1rL=A1AL
UGF
p2 RHP zero (zRHP) = gmL/Cm
-40dB/decade zRHP p-3dB = 1/CmgmLr1rL
-20dB/decade p2 = gmL/CL
UGF = DC Gainp-3dB =
gm1/Cm
Stability (phase margin of the amplifier):

UGF UGF UGF
PM = 180o - tan-1( ) - tan-1( ) - tan-1( )
p-3dB p2 zRHP
UGF UGF
= 90o - tan-1( ) - tan-1( )
p2 zRHP
g C g
= 90o - tan-1( m1 L ) - tan-1( m1 )
gmL Cm gmL
PM>45 to preserve stability

PM>60 to preserve stability and achieve better settling time
The presence of RHP zero degrades stability
What is the relationship gm1, gmL and Cm in order to
achieve stability?
26
Dimension Condition of Cm
If RHP zero is neglected

Case 1: PM = 60
tan-1(gm1CL/gmLCm) = 30
Cm = 1.73gm1CL/gmL
UGF = 0.58gmL/CL Recall: Single-Stage Amplifier,
Case 2: PM = 45 UGF=gmL/CL & PM=90
Cm = gm1CL/gmL
UGF = gmL/CL
\UGF of amplifier trades with the stability (PM)
In most textbooks: Cm = 2gm1CL/gmL & UGF =
0.5gmL/CL, then PM = 63.4
Quiz
As mentioned before, UGF = gm1/Cm, so is it the

best way to increase UGF of the amplifier by
decreasing Cm? From equation, decreasing Cm
does not increase the power consumption and
decreases the chip area. Then you should ask
yourself does it have any free lunch in the
world?
27
Answer
UGF increases due to the

|A(s)|
increase in p-3dB.
P-3dB
However, p2 does not DC Gain P-3dB
change, p2 is smaller than Decreasing Cm
UGF and PM is much p2

smaller than 45o. 0dB
s
Stability problem arises! UGF
p2
UGF
zRHP zRHP
No Free Lunch!!!
Probe Further
What is the frequency domain behavior if we increase

gm1 only based on UGF = gm1/Cm?
|A(s)|
DC Gain P-3dB
P-3dB
DC Gain
Increasing gm1
p2
0dB UGF s
UGF zRHP
p2
zRHP
Again, UGF increases but the amplifier suffers

from the stability problem!
28
Correct Way to Increase BW
How to enhance UGF without hurting stability (PM)?

Step 1: gmL
Both p2 and zRHP move to higher freq.
PM with same BW
Step 2: Cm according to Cm=2gm1CL/gmL
UGF
Rule of Thumb:
Larger current should be allocated to the
output stage for UGF enhancement!!
gmL >> gm1!
Effect of RHP Zero
By taking RHP zero into consideration and assume Cm=2gm1CL/gmL;

then
BW BW
PM = 90o - tan-1( ) - tan-1( )
p2 zRHP
g
= 63.4o - tan-1( m1 )
gmL
If gmL=gm1, then PM=18.4 (instability)
If gmL=10gm1, then PM=57.7 (stability degradation)
gmL >> gm1 to preserve stability due to RHP zero!
larger gmL implies larger power consumption.
Miller compensation is not suitable for low-power design due to the
presence of RHP zero!
RHP zero removal techniques Low-Power design!!
29
Miller Compensation with Null Resistor
Rm Cm
gm1 gmL
Vin Vo
-A1 -AL
r1 rL CL
C1
1
No change in pole locations
gm1gmL r1rL [1 - sCm ( - Rm )]
Vo gmL Rm is used to improve PM as
=
Vin CL zRHP is removed by Rm = 1/gmL
(1 + sCm gmL r1rL )(1 + s )
gmL PM = 63.4o
low-power design condition
Dimension Condition of Rm
LHP zero is generated if Rm > 1/gmL
If the LHP zero is used to cancel p2, then Rm is set as
CL 1 g 1
Rm = (1 + ) = (1 + mL )
Cm gmL 2gm1 gmL
Both zRHP and p2 are cancelled
Rm cannot be too large since very large Rm causes
open circuit and no pole-splitting effect due to Miller
compensation (Rm < r1/10)
Rule of Thumb:
1/gmL Rm < r1/10
30
Circuit Implementation of Miller Compensation
M3 M4
ML
Vo
Rm Cm
M1 M2
Mb2
Mb1 Mb3
If Rm is implemented by transistor(s), then the transistor(s)

should be placed between the drain of M4 and Cm to ensure
the transistor(s) always in the triode region!
Vgs,ML should be equal to Vgs,M3 and Vgs,M4 for minimizing the
systematic offset voltage.
Other Compensation Topologies

Multipath Miller Compensation Miller Compensation with Voltage Buffer
Cm
Cm gmv
Av
gm1 gmL
Vin Vo
-A1 -AL gm1 gmL
Vin Vo
rL CL -A1 -AL
r1 C1
r1 rL CL
C1
gmf
-Af
gma Cm
Current Buffer Compensation /
Aa
Cascode Compensation /
Active Compensation/Ahuja
gm1 gmL
Vin Vo
-A1 -AL
r1 rL CL
C1
31
Design Example
Design Example (1)
Given:
CL=10pF
UGF > 3MHz
PM > 60o
DC Gain > 80dB
SR > 2.5V/s
Power Consumption < 160W
Supply Voltage = 2V
Designers job: choose Rm, Cm, (W/L)i, Li, I to
meet specifications!!
What are the relationship between designers
job and the specifications?
32
Design Example (2)
Recall: for PM 63.4, then UGF = gmL/2CL & Cm =

2gm1CL/gmL
gmL is fixed (415 A/V) & Rm = 2.4 kW
Assume gm1 = 150 A/V, Cm is fixed at 7.2 pF
Theoretical UGF = 3.3 MHz (gmL/(2p)2CL)
Further assume r1 = 1.3 MW and ro = 200 kW

Theoretical dc gain = 84 dB
Use Hybrid-p model to verify the bandwidth, dc gain and phase

margin performances by using Hspice or Cadence
Hybrid-p AC Simulation Results
33
Design Example (3)
M3 M4
ML
Vo
Rm Cm
M1 M2
Mb2
Mb1 Mb3
SR=min(IMb3/CL, IMb2/Cm) IMb2/Cm (in most cases) fix IMb2

(W/L)M1 and (W/L)M2 are fixed as gm1 and IMb2 are known
Iterate (W/L)M3 and (W/L)M4 until the output resistance at V1 equaling
to r1 in the hybrid-p model
Systematic Offset Requirement (Vgs,M4=Vgs,ML
(W/L)ML/(W/L)M4= 2IML/IMb2) and total power consumption (Itot
IMb2+IML) fix (W/L)ML and IML (need iterations)
Make sure (W/L)ML and IML meet ro and dc gain requirements
Iterations of above steps are necessary until all specifications
are met.
Performance Summary
Actual Circuit
Specifications Theoretical Hybrid-p
(TSMC 0.35m CMOS)
Supply
2V
Voltage
Power
< 160 W 144.7 W N. A. 150 W
Consumption
DC Gain > 80 dB 84 dB 84 dB 85 dB
UGF > 3 MHz 3.3 MHz 3 MHz 3.2 MHz
PM > 60o 63.4o 65.7o 60o
SR 2.7 V/s (+ve slewing)

> 2.5 V/s 2.8 V/s N. A.
(0.5V step) 2.8 V/s (-ve slewing)
CL 10pF
34
Simulation Tips
DC Analysis: make sure all transistors

operating in the saturation region, and check the
lowest supply voltage to achieve the required
input common-mode range.
AC Analysis and Pole-Zero Analysis: check
dc gain, UGF, stability (phase margin, pole and
zero locations) and power consumption.
Transient Analysis: check step response of the
amplifier (slew rate and settling time). It should
be noted that the input step amplitude should be
within the input common-mode range of the
amplifier.
References
Design of Analog CMOS Integrated Circuits, by Behzad Razavi,

McGraw-Hill, 2001.
Analysis and Design of Analog Integrated Circuits, Paul R. Gray,
Paul J. Hurst, Stephen H. Lewis, and Robert G. Meyer, John Wiley
& Sons, Inc., 4th edition, 2000.
Slew rate: 9.6.1-9.6.2
Systematic offset voltage: 6.3.3
35

Lect1 Overview

Enviado por

Dados do documento

Título original

Direitos autorais

Formatos disponíveis

Compartilhar este documento

Compartilhar ou incorporar documento

Opções de compartilhamento

Você considera este documento útil?

Este conteúdo é inapropriado?

Direitos autorais:

Formatos disponíveis

Lect1 Overview

Enviado por

Direitos autorais:

Formatos disponíveis

EECT 6378 Power Management Circuits

Lecture 1: Course Overview and

Department of Electrical and Computer Engineering

Course materials are available on eLearning:

Professor Office Hours (ECSN 4.512)

EE6378 Lecture 1 pg. 2

The final grade will be determined by the

Term Paper (15%) + Final Project (25%) +

First exam is tentatively scheduled on 10/10

All course announcements will be only sent

EE6378 Lecture 1 pg. 4

Review of Stability and Frequency Compensation of Two-Stage

Linear and Low-Dropout Regulators

Advances in Voltage References

Switched-Mode Power Converters

Control Methodologies of Switched-Mode Power Converters

Introduction to Switched-Capacitor Power Converters

EE6378 Lecture 1 pg. 6

This course mainly covers analysis and design of power

We will deal with the power conversion circuits below 10W

Prerequisite: EECT 6326 Analog IC

Power electronics deals with circuits convert electrical

The design of power conversion circuits includes many

EE6378 Lecture 1 pg. 8

Power management circuits convert one type of a

EE6378 Lecture 1 pg. 9

Why Power Management Circuits?

EE6378 Lecture 1 pg. 10

Battery-Operated Portable Devices Energy Sources

Long Battery Life,

NiMH /NiCd Batteries

EE6378 Lecture 1 pg. 11

Power Management Circuits for Portable

Provide a regulated power source

Power Management Circuits (h 1)

Analog Part Digital Part RF Part Interface

Types Pros Cons

Applications of Different PMICs in

EE6378 Lecture 1 pg. 14

Different applications have different requirements of output

Best power efficiency Good power efficiency

Very good power efficiency Achieve output regulation

Integrated DC-DC Converters (1)

Current-mode switched-mode dc-dc

EE6378 Lecture 1 pg. 16

Sub-1V current-mode switched-

EE6378 Lecture 1 pg. 17

Integrated DC-DC Converters (3)

Open-loop cross-coupled voltage

EE6378 Lecture 1 pg. 18

Regulated SC dc-dc converter

EE6378 Lecture 1 pg. 19

Integrated DC-DC Converter (5)

EE6378 Lecture 1 pg. 20

Accurate CMOS bandgap

EE6378 Lecture 1 pg. 21

Voltage References (1)

Sub-1V CMOS bandgap voltage

EE6378 Lecture 1 pg. 22

EE6378 Lecture 1 pg. 23

Consider a system shown below with an input vi(s) and an

EE6378 Lecture 1 pg. 24

It is noted that the transfer function is a property of the circuit