DESIGN AND IMPLEMENTATION OF UART

COMMUNICATION USING FPGA BOARD

A universal asynchronous receiver and transmitter (UART) is a circuit
that sends parallel data through a serial line. UARTs are frequently used in
conjunction with the EIA (Electronic Industries Alliance) RS-232 standard, which
specifies the electrical, mechanical, functional, and procedural characteristics of two
data communication equipment. This project focuses on the implementation of UART
using FPGA board and verilog language. UART is a serial communication protocol
which allows the full duplex communication in serial link, it is an essential to
computers and allows them to communicate with low speed peripheral devices, such
as the keyboard, the mouse, modems etc.

A field-programmable gate array (FPGA) is an integrated circuit designed

to be configured by a customer or a designer after manufacturing hence "field-
programmable". FPGAs contain an array of programmable logic blocks, and a
hierarchy of reconfigurable interconnects that allow the blocks to be "wired together",
like many logic gates that can be inter-wired in different configurations. Logic
blocks can be configured to perform complex combinational functions, or merely
simple logic gates like AND and XOR. In most FPGAs, logic blocks also include
memory elements, which may be simple flip-flops or more complete blocks of
memory.
A UART includes a transmitter and a receiver. The transmitter is
essentially a special shift register that loads data in parallel and then shifts it out bit by
bit at a specific rate. The receiver, on the other hand, shifts in data bit by bit and then
reassembles the data. The serial line is 1 when it is idle. The transmission starts with a
start bit, which is 0, followed by data bits and an optional parity bit, and ends with
stop bits, which are 1. The number of data bits can be 6, 7, or 8. The optional parity bit
is used for error detection. For odd parity, it is set to 0 when the data bits have an odd
number of 1s. For even parity, it is set to 0 when the data bits have an even number of
1s. The number of stop bits can be 1, 1.5 or 2.
UART is used mostly for the short distance, low speed and is of low cost.
The UART consists of three main components namely transmitter, receiver and baud
rate generator which is nothing but the frequency divider. The universal asynchronous
receiver/transmitter is shortened as UART. The designated "start" and "stop" bits
indicate the framing of each character.

Ch.Sumanth sai - 13071A04D4

I.N.S Manoj - 13071A04E4
D.Nithish - 13071A04G2
E.Shiva Prasad - 14075A0433
Basic UART Transmission Flow:

Circuit diagram for UART communication :

The hardware language used for designing is Verilog and software used
for simulation is modelsim.

Verilog Description : Verilog, is a hardware description language (HDL) used to

model electronic systems. It is most commonly used in the design and verification of
digital circuits at the register-transfer level of abstraction.

Modelsim : ModelSim is a multi-language HDL simulation environment by Mentor

Graphics, for simulation of hardware description languages such as VHDL, Verilog
and SystemC, and includes a built-in C debugger.