AKHIL GAKHAR (173079027)

Question 1:

CPL XOR XNOR

*distortion near 43MHz

*present freq 100kHz

*Model file for the MOSFET

.include nmos.txt

.include pmos.txt

m1 b1 a1 c1 0 cmosn w=0.8u l=0.4u ad=0.64p as=0.64p pd=3.2u ps=3.2u

m2 b2 a2 c1 0 cmosn w=0.8u l=0.4u ad=0.64p as=0.64p pd=3.2u ps=3.2u

m3 b2 a1 c2 0 cmosn w=0.8u l=0.4u ad=0.64p as=0.64p pd=3.2u ps=3.2u

m4 b1 a2 c2 0 cmosn w=0.8u l=0.4u ad=0.64p as=0.64p pd=3.2u ps=3.2u

m5 vout1 c1 s s cmosp w=1.6u l=0.4u ad=1.28p as=1.28p pd=4.8u ps=4.8u

m6 vout1 c1 0 0 cmosn w=0.8u l=0.4u ad=0.64p as=0.64p pd=3.2u ps=3.2u

m7 vout2 c2 s s cmosp w=1.6u l=0.4u ad=1.28p as=1.28p pd=4.8u ps=4.8u

m8 vout2 c2 0 0 cmosn w=0.8u l=0.4u ad=0.64p as=0.64p pd=3.2u ps=3.2u

c1 c1 0 50f

c2 c2 0 50f

c3 vout1 0 0.1p

c4 vout2 0 0.1p

V1 b1 0 pulse(0.2 3 2.5u 1p 1p 5u 10u)

V2 b2 0 pulse(3 0.2 2.5u 1p 1p 5u 10u)

V3 a1 0 pulse(0.2 3 0 1p 1p 5u 10u)
V4 a2 0 pulse(3 0.2 0 1p 1p 5u 10u)

vs s 0 3.3v

.control

tran 1u 100u

*plot v(c2)+10

plot v(b1) v(a1)+5 v(c1)+10 v(vout1)+15

*plot v(c1) v(c2)+5 v(vout1)+10 v(vout2)+15

.endc

.end

fig 1: freq 100khz

fig 2: freq 10Mhz

fig 3: 25 Mhz
Question 2:

CPL XOR XNOR

*Model file for the MOSFET

.include nmos.txt

.include pmos.txt

*Usually, the order of terminals are

*drain, gate, source and body respectively

m1 b1 a1 c1 cmosn w=0.8u l=0.4u ad=0.64p as=0.64p pd=3.2u ps=3.2u

m2 b2 a2 c1 cmosn w=0.8u l=0.4u ad=0.64p as=0.64p pd=3.2u ps=3.2u

m3 b2 a1 c2 cmosn w=0.8u l=0.4u ad=0.64p as=0.64p pd=3.2u ps=3.2u

m4 b1 a2 c2 cmosn w=0.8u l=0.4u ad=0.64p as=0.64p pd=3.2u ps=3.2u

m5 vout1 c1 s1 s1 cmosp w=1.6u l=0.4u ad=1.28p as=1.28p pd=4.8u ps=4.8u

m6 vout1 c1 0 0 cmosn w=0.8u l=0.4u ad=0.64p as=0.64p pd=3.2u ps=3.2u

m7 vout2 c2 s2 s2 cmosp w=1.6u l=0.4u ad=1.28p as=1.28p pd=4.8u ps=4.8u

m8 vout2 c2 0 0 cmosn w=0.8u l=0.4u ad=0.64p as=0.64p pd=3.2u ps=3.2u

c1 c1 0 50f

c2 c2 0 50f

c3 vout1 0 0.1p

c4 vout2 0 0.1p

V1 b1 0 dc 3v

V2 b2 0 dc 0v

V3 a1 0 dc 0v

V4 a2 0 dc 3v

vd2 s s2 0v

vd1 s s1 0v

vs s 0 3.3v

.control

tran 0.01n 0.1n

plot i(vd1)

plot i(vd2)

.endc

.end
fig4: leakage current 17.4uA through xor inverter

fig5: leakage current through xnor inverter 17.4uA when complimentary inputs are given

Question 3:

CPL XOR XNOR

*Model file for the MOSFET

.include nmos.txt

.include pmos.txt

*distortion about 4.4u 1u i.e w/l ratio=4.4

*Usually, the order of terminals are

*drain, gate, source and body respectively

m1 b1 a1 c1 0 cmosn w=0.8u l=0.4u ad=0.64p as=0.64p pd=3.2u ps=3.2u

m2 b2 a2 c1 0 cmosn w=0.8u l=0.4u ad=0.64p as=0.64p pd=3.2u ps=3.2u

m3 b2 a1 c2 0 cmosn w=0.8u l=0.4u ad=0.64p as=0.64p pd=3.2u ps=3.2u

m4 b1 a2 c2 0 cmosn w=0.8u l=0.4u ad=0.64p as=0.64p pd=3.2u ps=3.2u

m5 vout1 c1 s s cmosp w=1.6u l=0.4u ad=1.28p as=1.28p pd=4.8u ps=4.8u

m6 vout1 c1 0 0 cmosn w=0.8u l=0.4u ad=0.64p as=0.64p pd=3.2u ps=3.2u

m7 vout2 c2 s s cmosp w=1.6u l=0.4u ad=1.28p as=1.28p pd=4.8u ps=4.8u

m8 vout2 c2 0 0 cmosn w=0.8u l=0.4u ad=0.64p as=0.64p pd=3.2u ps=3.2u

m9 c2 vout2 s s cmosp w=4.4u l=1u ad=8.8p as=8.8p pd=12.8u ps=12.8u

m10 c1 vout1 s s cmosp w=4.4u l=1u ad=8.8p as=8.8p pd=12.8u ps=12.8u

c1 c1 0 50f

c2 c2 0 50f

c3 vout1 0 0.1p

c4 vout2 0 0.1p

V1 b1 0 pwl(0 3v 1m 3v 1.00000001m 0.2v 2m 0.2v)

V2 b2 0 pwl(0 0.2v 1m 0.2v 1.00000001m 3v 2m 3v)

V3 a1 0 dc 3v

V4 a2 0 dc 0v
vs s 0 3.3v

.control

tran 0.1m 3m

plot v(c1) v(vout1)+10 v(c2)+15 v(vout2)+20

.endc

.end

fig 6: leakage current just before worst case w/l ratio=4.4 is 4.851pA