VLSI Design and Technology

Aim: To generate square/ramp waveform using DAC

Tools Required: Xilinx ISE 8.2i, SPARTAN2 DSP Trainer kit.

Theory:
Square wave:
It is non sinusoidal periodic waveform (which can be represented as an infinite, summation of
sinusoidal waves) in which the amplitude alternates at a steady frequency between fixed minimum and
maximum values, with the same duration at minimum and maximum. The transition between minimum
and maximum is instantaneous for an ideal square wave. In practice this is never achieved because of
physical limitation of the system that generates the waveform. The time taken for the signal to rise from
low level to high level and back again are called the rise time and fall time respectively.
Square waves are universally encountered in digital switching circuits and are naturally generated
by binary (two level) logic devices. They are used as timing references or clock signals because their
fast transition synchronous logic circuits at precisely determined intervals.
The DAC (AD 1222) is digital to analog convertor on Spartan 2 FPGA board. There are 4 DACs,
12 bit of each. Here separate enable pins are provided for each DAC to select any one of the four DACs
present in spartan2 board. In this Spartan 2 board 11 bits are sent from FPGA to DAC.
To get the square wave at the output of the DAC the digital input must be either 0 or 1. So we
get square wave as shown in following figure 1.

Figure 1: Block diagram for Square wave generation

Algorithm:
1. Start
2. Declare signal count
3. Check the reset value, if reset=1 then set the count=0
4. Else for positive edge of the clock signal, increment signal s.
5. Check whether the MSB of the signal cnt1 is one or not.
6. If yes, then set the count=00000000000
 VLSI Design and Technology

7. If no, then set the count=11111111111

8. Select any one of the four DACs with enable=1
9. Assign count value to dataout.
10. Stop.

Ramp wave:
A waveform that is similar to a sawtooth waveform but difference is that it starts at zero level and
gradually rises to its peak level and then instantly drops back to zero level to form one cycle.
To get ramp wave at the output of DAC we have to increase DAC input by 1 from 00000000000
to 11111111111 at each positive edge of clock pulse. Then we get ramp wave as shown in following figure
2.

Figure 2: Block diagram for Ramp wave generation

Algorithm:
1. Start.
2. Declare signal count.
3. Check the reset value, if reset=1 then set the output to zero.
4. Else for positive edge of the clock signal, increment the count by l.
5. Select any one of the 4 DACs with the Enable=1.
6. Assign count value to dataout.
7. Stop.

AD1222
 VLSI Design and Technology

General circuit information:

The simplified D/A circuit is shown in Figure 3. An inverted R-2R ladder structure is used that is, the
binary weighted currents are switched between the OUT1 and OUT2 bus lines, thus maintaining a constant
current in each ladder leg independent of the switch state.

Figure 3: Functional Diagram (Inputs HIGH)

The input resistance at VREF (Figure 3) is always equal to RLDR (RLDR is the R/2R ladder characteristic
resistance and is equal to value R). Since RIN at the VREF pin is constant, the reference terminal can be
driven by a reference voltage or a reference current, ac or dc, of positive or negative polarity. (If a current
source is used, a low temperature coefficient external RFB is recommended to define scale factor.)

Calculations:

Conclusion:
 VLSI Design and Technology

Code
Square Waveform:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity square_wave_prog is
Port ( clk,reset : in STD_LOGIC;
dataout : out STD_LOGIC_VECTOR(10 downto 0);
enable : out STD_LOGIC);
end square_wave_prog;

architecture Behavioral of square_wave_prog is

signal cnt: std_logic_vector(10 downto 0);
signal cnt1: std_logic_vector(11 downto 0);
begin
process(clk,reset)
begin
if(reset='1')then
cnt<=(others=>'0');
elsif(clk'event and clk='1')then
cnt1<=cnt1+1;
if(cnt1(11)='1')then
cnt<=(others=>'0');
else
cnt<=(others=>'1');
end if;
end if;
end process;
enable<='1';
dataout<=cnt;
end Behavioral;

Ramp Waveform:
library IEEE;
 VLSI Design and Technology

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ramp_wave_prog is
Port ( clk,reset : in STD_LOGIC;
dataout : out STD_LOGIC_VECTOR(10 downto 0);
enable : out STD_LOGIC);
end ramp_wave_prog;

architecture Behavioral of ramp_wave_prog is

signal cnt: STD_LOGIC_VECTOR(10 downto 0);
begin
process(clk,reset)
begin
if(reset='1')then
cnt<=(others=>'0');
elsif(clk'event and clk='1')then
cnt<=cnt+1;
end if;
end process;
enable<='1';
dataout<=cnt;
end Behavioral;