Solid-State Electronics 51 (2007) 387393

www.elsevier.com/locate/sse

A new analytical threshold voltage model for symmetrical double-gate

MOSFETs with high-k gate dielectrics
T.K. Chiang *, M.L. Chen
Department of Electronic Engineering, Southern Taiwan University of Technology, No. 1 Nan-tai Street, Tainan 710, Taiwan, ROC

Received 3 May 2006; received in revised form 2 January 2007; accepted 19 January 2007

The review of this paper was arranged by Prof. S. Cristoloveanu

Abstract

Based on the fully two-dimensional (2D) Poissons solution in both silicon lm and insulator layer, a compact and analytical thresh-
old voltage model, which accounts for the fringing eld eect of the \short channel symmetrical double-gate (SDG) MOSFETs, has been
developed. Exploiting the new model, a concerned analysis combining FIBL-enhanced short-channel eects and high-k gate dielectrics
assess their overall impact on SDG MOSFETs scaling. It is found that for the same equivalent oxide thickness, the gate insulator with
high-k dielectric constant which keeps a great characteristic length allows less design space than SiO2 to sustain the same FIBL induced
threshold voltage degradation.
 2007 Elsevier Ltd. All rights reserved.

Keywords: Threshold voltage; Fringing-induced barrier lowering; Symmetrical double-gate MOSFET; Characteristic length

1. Introduction eld lines termination on the source/drain regions increas-

As bulk and SOI MOSFETs scale into sub-100 nm
regime, the gate oxide thickness is projected to reduce to
1.5 nm or below. Such an ultra-thin gate oxide will induce
high direct tunneling gate leakage currents [14] that
increases the static power and can aect circuit operation.
To solve this problem, the new dielectric materials with
high dielectric constants as well as compatibility with the
silicon process are needed. Various high dielectric constant
(k) materials such as Si3N4(k = 7.5), HfSiO4(k = 12),
HfO2(k = 22), and BaSrTiO3(k = 200) have been recom-
mended to replace SiO2 for solving the gate leakage prob-
lem [58]. However, with increase in gate dielectrics, the
k
physical thickness of the gate dielectric (a factor of kSiO
2
to prevent direct gate tunneling becomes comparable to
the channel length, which brings about the percentage of
*
Corresponding author. Tel./fax: +886 6 5904779.
E-mail address: tkchiang@mail.stut.edu.tw (T.K. Chiang).
ing compared to the eld lines termination on the channel.
These eld lines nally induce an electric eld from source
to channel thereby reducing the source to channel barrier
height and causing a weaker coupling between gate and
channel. This phenomenon is generally known as FIBL
(Fringing Induced Barrier Lowering) [9] which will induce
the threshold behavior degradation. Both the characteris-
tics of sub-10 nm MOSFETs with high-k gate dielectrics
and the degradation of device characteristics due to FIBL
have been studied [911]. However, none of them provides
the consolidated and physical model to investigate
the short-channel performance associated with FIBL. To
assess the performance of the submicrometer device, there
) is a need to develop an analytical and physics-based model
to describe characteristics of MOSFETs with high-k gate
dielectrics. Zhang et al. [12] proposed a simple model to
evaluate high-k MOSFETs performance based on empiri-
cally adjustable parameters b1 and b2. It can not give the
physical insight into the device physics due to its empirical
equation. On the basis of variation method, Xiaoyan et al.

0038-1101/$ - see front matter  2007 Elsevier Ltd. All rights reserved.
doi:10.1016/j.sse.2007.01.026
388 T.K. Chiang, M.L. Chen / Solid-State Electronics 51 (2007) 387393

[13] suggested the threshold voltage model for the MOS- respect to the Fermi potential of the n+ source (at the con-
FETs with high-k gate dielectrics. However, quasi-2D duction band edge). When solving the Poissons equation,
potential distribution obtained by their approach can not only subthreshold regime is considered and the mobile car-
be applied for the device especially with ultra short channel riers are neglected [17,18]. Assuming a uniform impurity
length and thick gate oxide thickness without considering doping density Na in the channel region, the 2D potential
fully 2D eects both in silicon region and in oxide region, distribution in the fully-depleted silicon region can be
which play a very important role in predicting short-chan- obtained by solving the following Poissons equation:
nel device performance [14]. Moreover, Chen et al. [15]
proposed an analytical threshold voltage model for the o2 /x; y o2 /x; y qN a
1
short-channel undoped double-gate MOSFETs considering ox2 oy 2 si
the fringing-induced barrier lowering (FIBL) eect. But,
the model is not capable of exactly predicting the threshold where q is the electron charge, si is the permittivity of the
voltage without assuming a calibrated factor QTH to the silicon lm. By using the method of separation of variable
model. In this paper, based on fully resultant solution of proposed by our previous work [19,20] associated with the
2D Poissons equation in the gate dielectric layer and appropriate boundary conditions, the solutions of Eq. (1)
silicon depletion region the threshold voltage model associ- can be solved as follows:
ated with FIBL is derived. Without any tting parameters
qN a x2 qN a tsi ti qN a t2si
and calibrated factor, the simulated results of the analytical /x; y V g  DU  
model agree well with those simulated by device simulator 2si 2i 8si
[16]. These analytical results are useful in predictive com- h i  
X1 C n sinh
pLy
Dn sinh py  
pact short-channel threshold voltage model for fully kn kn px
  cos
depleted SDG MOSFETs. With this model, the impact of pL kn
n1 sinh
the fringing eld eect with high-k gate dielectrics on kn
threshold behavior can be thoroughly examined. Our
model can be applied for the circuit simulation due to its 2
ecient computation.
with
   
pti ptsi
2. Model derivation 2k2n tan sin
kn 2k
Cn 2   n 3 V bi  V g DU
The structure of the SDG MOSFET is shown in Fig. 1. ptsi
sin
The x-axis is perpendicular to the surface and x = 0 refers 6tsi k 7
p2 ti 6
42  n  ti 7
to the center of the lm and the y-axis is parallel to the chan- 2pti 5
sin
nel, respectively. The same voltage is applied to the two kn
gates. The electrostatic potential /(x, y) in the silicon body
   
is dened as the intrinsic potential at a point (x, y) with pti ptsi
qN a tsi k2n
tan sin
kn 2kn
2   3
ptsi
sin
6tsi k 7
p2 i 6
42  n  ti 7
2pti 5
sin
kn
 
ptsi
2qN a k3n sin
2k
2  n 3
ptsi
sin
6tsi k 7
p3 si 6
42  n  ti 7
2pti 5
sin
kn
 
ptsi
qN a tsi k2n cos
2kn
 2   3 3
ptsi
sin
6tsi k 7
p2 si 6
42  n  ti 7
2pti 5
sin
Fig. 1. Schematic cross section view of a SDG MOSFET. kn
 T.K. Chiang, M.L. Chen / Solid-State Electronics 51 (2007) 387393 389

and From equations of (6) and (7), the minimum surface poten-
    tial can be obtained as
pti ptsi  t 
2k2n tan sin si
kn 2k /min /  ; y min
Dn 2   n 3 V bi V ds  V g DU 2
ptsi
sin qN a tsi ti
6tsi k 7 V g  DU 
p2 ti 6
42  n  ti 7 2i
2pti 5
sin pL
C 1 sinh2k  12 ln DC11 D1 sinh2k
pL
12 ln DC11
kn 1 1
    sinhpL
2 pti ptsi k1
qN a tsi kn tan sin  
kn 2kn ptsi
2   3  cos 8
ptsi 2k1
sin
6tsi k 7
p2 i 6
42  n  ti 7 with
2pti 5
sin L k1 C 1
kn y min ln 9
  2 2p D1
pt si
2qN a k3n sin At threshold condition, the electron surface density of the
2kn
2   3 back gate and front gate must be equal to the substrate
ptsi
sin doping concentration [21,22] i.e.,
6tsi k 7
p3 si 6
42  n  ti 7
2pti 5
qWs1 UB qWs2 UB
ni e KT ni e KT Na 10
sin
kn
  with
ptsi p Eg
qN a tsi k2n cos ni N c N v e 2KT 11
2kn
 2   3 4
ptsi and
sin
6tsi k 7
p2 si 6
42  n  ti 7 Ws1 Ws2 /min 12
2pti 5
sin where ni is the intrinsic carrier density, Ws1 is the surface
kn
potential of the front gate, Ws2 is the surface potential of
where Vbi is the built-in voltage at the interface between the back gate, and Nc and Nv are the eective density of
source/drain and silicon body, Vg is the gate bias, Vds is states for conduction band and valence band respectively.
the drain bias, DU is the work function dierence between From (10)(12), at threshold, the minimum surface poten-
silicon body and gate electrode, and kn is the eigen value tial /min can be expressed as
which should satisfy the equation Eg 2KT Na
    /min ln p ; V g V t;s 13
pti ptsi q q 2N c N v
si tan i cot 5
kn 2kn where Vt,s is the threshold voltage for the short-channel
SDG MOSFETs. Solving for Vg through (3), (4), (8), (9),
The rst terms of C1 and D1 are sucient to express the po- and (13), the threshold voltage can be achieved. However,
tential in Si body because Fourier coecients for Dn and the form of the threshold voltage is too complicated to be
Cn decay very rapidly. Therefore, the entire expression used in analyzing the subthreshold characteristics. To
for the potential of silicon lm in subthreshold region is obtain the simple and feasible analytical threshold voltage
approximated as model, the condition of kL1  1 is assumed [23]. The
qN x2 qN tsi ti qN a t2si threshold voltage accounting for the SDG MOSFETs with
/x; y  V g  DU a  a  high-k dielectric constant of i can be dened as
2si 2i 8si
h i  
pLy py   V t;s V t;L  DV t;s 14
C 1 sinh k1 D1 sinh k1 px
  cos 6 with
sinh k1 pL k1
qN tsi ti
V t;L a DU a 15
Note that C1 and D1 in (6) have considered fully 2D eects 2
 i
in entire device region when deriving 2D potential. To ptsi 2kpL p
DV t;s 2b cos e 1 a  V bi  ca  V bi  V ds  c
solve the minimum surface potential, we set the derivative 2k1
of /x; yjxtsi to zero: 16
2

o/x; y where Vt,L is the threshold voltage for the long-channel

jxtsi 0 7
oy 2
devices, and DVt,s is the threshold voltage roll-o caused
390 T.K. Chiang, M.L. Chen / Solid-State Electronics 51 (2007) 387393

by the short-channel eects such as FIBL. The terms in (16) section. The physical, compact, and analytical 2D short-
for a, b, and c are given as channel threshold voltage model with FIBL included in
Eg 2KT Na fully-depleted SDG MOSFET pL is successfully derived. For
a ln p 17 the long-channel devices (i.e., e 2k1  0), the threshold volt-
q q 2N c N v
    age degradation resulted from 2D eects and shown in (16)
pti ptsi can be negligible. On the contrary, for the device with both
2k21 tan sin
k1 2k1 short channel and high-k gate dielectrics, which simulta-
b 2   3 18
ptsi neously cause greater k1 for MOSFETs, the threshold volt-
sin ti pL
6tsi k1 7 age behavior can be even worse due to e 2k1  1. The eect
p2 ti 6
42   7
2pti 5 of FIBL stemming from high-k dielectrics on the threshold
sin behavior degradation and device scaling is illustrated in the
k1
following section.
and
 
ptsi 3. Results and discussion
qN a tsi ti cos
qN a k1 ti 2k1
c       19 Fig. 2 shows the surface potential /min as a function of
pti pti ptsi
psi tan 2si tan sin normalized position along the channel for dierent k-val-
k1 k1 2k1
ues. It is observed that for a drain bias, the minimum sur-
where k1 is the characteristic length for the high-k dielectric face potential is elevated by the increasing gate dielectric
constant of i and should satisfy constant, which results in the considerable reduction of
    the channel barrier and causes a severe eld-induced bar-
pti ptsi
si tan i cot 20 rier lowering eect (FIBL). The consistency between the
k1 2k1
model results and those in numerical simulation veries
As for Vt,L in (15), it reveals that the long-channel thresh- the accuracy of our fully 2D analytical model. It can be fur-
old voltage is independent of the high-k gate dielectrics for ther pointed out that for more drian bias Vds, the minimum
the same equivalent oxide thickness of SDG MOSFETs. surface potential will be elevated even more due to the
However, for the short channel device, it is found that another DIBL induced by the increasing drain bias. The
the characteristic length k1 of high-k gate insulator is threshold voltage roll-o against the gate length L has been
greater than that of SiO2 when both materials of dier- plotted in Fig. 3 for dierent gate dielectric constants. The
ent dielectric constants apply for the same equivalent oxide threshold voltage extracted from CAD simulation in this
pL
thickness. Hence, according to the term of e 2k1 in Eq. (16), paper is based on the maximum-gm method (linear extrap-
it will give rise to much more threshold voltage roll-o for olation of Id  Vgs to zero at Vds = 0.01 V) for linear
the high-k gate insulator which will be shown in the next threshold voltage and a modied constant-current method

y
Fig. 2. Graph for surface potential distribution versus the normalized channel distance L
for dierent k-values. The simulated device parameters are
Na = 1.0 1016 cm3, tEQ
ox 1:5 nm, tsi = 10 nm, L = 50 nm, and Vds = 0.5 V.
 T.K. Chiang, M.L. Chen / Solid-State Electronics 51 (2007) 387393 391

Fig. 3. Threshold voltage roll-o versus the gate length for dierent k-values. The simulated results from variation method proposed by Ref. [13] are
included for comparison. The simulated device parameters are Na = 1.0 1016 cm3, tEQox 1:5 nm, tsi = 10 nm, and Vds = 0.1 V.

[24] for saturation threshold voltage at Vds = 0.1 V). It
reveals that for the same equivalent oxide thickness
tEQ ox
ox t i  i =1.5 nm), the high gate dielectric will suer
more FIBL than the low gate dielectric does. Therefore,
the signicant reduction of the channel barrier for k = 50
will induce great threshold voltage roll-o when the chan-
nel length is decreased further. Fig. 4 shows the dependence
of the threshold voltage roll-o on the gate length for var-
ious equivalent oxide thicknesses. It is obvious that the
great threshold voltage degradation is caused by large
equivalent oxide thickness which enhances the FIBL eect.
Fig. 5 shows the dependence of the characteristic length
(l kp1 ) on the silicon lm thickness for various k-values
of gate dielectrics. It is revealed that the great characteristic
length is caused by both the high gate dielectric and the
thick silicon lm, which results in strong 2D eect in gate
insulator. It should be noted that as the silicon thickness
becomes extremely large, the characteristic length increases
and agrees with each other regardless of gate dielectric con-
stant. It implies that 2D eects dominate the entire device

Fig. 4. Threshold voltage roll-o versus the gate length for dierent eective oxide values. The simulated results from variation method proposed by Ref.
[13] are included for comparison. The simulated device parameters are Na = 1.0 1016 cm3, tsi = 10 nm, and Vds = 0.1 V.
392 T.K. Chiang, M.L. Chen / Solid-State Electronics 51 (2007) 387393

Fig. 5. The dependence of the characteristic length l on the silicon lm thickness for various k-values of gate dielectrics. The simulated results from
variation method proposed by Ref. [13] are included for comparison.

behavior although the small k of gate insulator is used to
suppress it. According to (16), the high-k gate material with
large characteristic length causing great threshold voltage
roll-o can not eectively suppress the FIBL. The simu-
lated data from variation method is included for compari-
son in Figs. 35. It can be concluded that the approach of
variation method proposed by Ref. [13] overestimates the
FIBL and predicts the larger threshold voltage roll-o as
shown in Figs. 3 and 4. However, according to Fig. 5,
the characteristic length is almost the same with each other
for the low k-value of 3.9. As the k-value increases, the
deviation of the model and the approach of Ref. [13]
become great especially for the k-value of 100. Fig. 6 shows
the impact of the equivalent oxide thickness on the mini-
mum gate length for dierent gate dielectric constants with
DVt,s < 70 mV. It can be seen that for the required thresh-
old voltage roll-o of DVt,s < 70 mV, the minimum gate
dielectric constant of k = 3.9 makes the scaling gate length
even shorter than any other gate dielectric constant. From
the point of view of reducing the threshold voltage roll-o,
the low-k gate material is preferred. Even though both the
smaller equivalent oxide thickness and low dielectric con-

Fig. 6. The impact of the equivalent oxide thickness on the minimum channel length for dierent gate dielectric constants with DVt,s < 70 mV. The
simulated device parameters are Na = 1.0 1016 cm3, tsi = 10 nm, and Vds = 0.1 V.
 T.K. Chiang, M.L. Chen / Solid-State Electronics 51 (2007) 387393
stant of gate insulator are required to reduce the threshold
voltage roll-o and the drain leakage current caused by
FIBL, the low-k gate material will possibly initiate the gate
leakage current for its weak gate insulation, especially in
deep-submicrometer device regime [25]. The trade-o
between to alleviate the threshold voltage degradation
using low-k gate material and to resist the gate leakage cur-
rent by means of the high-k gate constant should be consid-
ered simultaneously when we choose the gate material in
optimizing the DG MOSFETs design.
4. Conclusions
On a basis of fully 2D solution of potential in both sil-
icon and gate insulator, a new and compact analytical
model for threshold voltage for the SDG MOSFETs has
been presented by incorporating the eld-induced barrier
lowering (FIBL) eect. The eect of gate dielectrics on
the device behavior such as the threshold voltage degrada-
tion DVt,s and characteristic length l for device scaling are
thoroughly examined. The results of proposed analytical
model match closely with numerical data. The model can
be applied to circuit simulation due to its computational
eciency.
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