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Data Sheet
14/20-Pin Flash Microcontrollers
with nanoWatt XLP Technology
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchips Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as unbreakable.
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchips code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
ISBN: 978-1-61341-289-3
ECCP (Half-Bridge)
Program Data
ECCP (Full-Bridge)
Timers (8/16-bit)
Cap Sense (ch)
10-bit ADC (ch)
Memory Memory
Comparators
SR Latch
EUSART
Data EEPROM
Device
I/Os(1)
MSSP
CCP
(bytes)
(bytes)
Words
PIC16LF1825 8K SRAM
1024 256 12 8 8 2 4/1 1 1 1 1 2 Yes
PIC16F1825 8K 1024 256 12 8 8 2 4/1 1 1 1 1 2 Yes
PIC16LF1829 8K 1024 256 18 12 12 2 4/1 1 2 1 1 2 Yes
PIC16F1829 8K 1024 256 18 12 12 2 4/1 1 2 1 1 2 Yes
Note 1: One pin is input only.
VDD 1 14 VSS
CCP2(1)/P2A(1)/T1CKI/T1OSI/OSC1/CLKIN/RA5 2 13 RA0/AN0/CPS0/C1IN+/VREF-/DACOUT/TX(1)/CK(1)/ICSPDAT
T1G(1)/P2B(1)/SDO(1)/CLKR/T1OSO/CLKOUT/OSC2/CPS3/AN3/RA4 3 12 RA1/AN1/CPS1/C12IN0-/VREF+/SRI/RX(1)/DT(1)/ICSPCLK
PIC16(L)F1825
MCLR/VPP/T1G(1)/SS1(1)/RA3 4 11 RA2/AN2/CPS2/T0CKI/INT/C1OUT/SRQ/CCP3/FLT0
MDCIN2/DT(1)/RX(1)/CCP1/P1A/RC5 5 10 RC0/AN4/CPS4/C2IN+/SCL/SCK/P1D(1)
MDOUT/CK(1)/TX(1)/P1B/SRNQ/C2OUT/RC4 6 9 RC1/AN5/CPS5/C12IN1-/SDA/SDI/P1C(1)/CCP4
MDMIN/SS1(1)/P1C(1)/CCP2(1)/P2A(1)/C12IN3-/CPS7/AN7/RC3 7 8 RC2/AN6/CPS6/C12IN2-/P1D(1)/P2B(1)/SDO(1)/MDCIN1
Preliminary
PIC16(L)F1825/1829
DS41440B-page 5
FIGURE 2: 16-PIN DIAGRAM FOR PIC16(L)F1825
DS41440B-page 6
PIC16(L)F1825/1829
QFN
VDD
VSS
NC
NC
16
15
14
13
CCP2(1)/P2A(1)/T1CKI/T1OSI/OSC1/CLKIN/RA5 1 12 RA0/AN0/CPS0/C1IN+/VREF-/DACOUT/TX(1)/CK(1)/ICSPDAT/ICDDAT
T1G(1)/P2B(1)/SDO(1)/CLKR/T1OSO/CLKOUT/OSC2/CPS3/AN3/RA4 2 11 RA1/AN1/CPS1/C12IN0-/VREF+/SRI/RX(1)/DT(1)/ICSPCLK/ICDCLK
PIC16(L)F1825
MCLR/VPP/T1G(1)/SS1(1)/RA3 3 10 RA2/AN2/CPS2/T0CKI/INT/C1OUT/SRQ/CCP3/FLT0
MDCIN2/DT(1)/RX(1)/CCP1/P1A/RC5 9 RC0/AN4/CPS4/C2IN+/SCL/SCK/P1D(1)
4
8
RC3/AN7/CPS7/C12IN3-/P2A(1)/CCP2(1)/P1C(1)/SS1(1)/MDMIN
Preliminary
RC4/C2OUT/SRNQ/P1B/TX(1)/CK(1)/MDOUT
RC1/AN5/CPS5/C12IN1-/SDA/SDI/P1C(1)/CCP4
RC2/AN6/CPS6/C12IN2-/P1D(1)/P2B(1)/SDO(1)/MDCIN1
2010-2011 Microchip Technology Inc.
14-Pin PDIP/SOIC/TSSOP
Comparator
16-Pin QFN
Cap Sense
Modulator
Reference
SR Latch
EUSART
Interrupt
Pull-up
Timers
MSSP
ECCP
Basic
A/D
I/O
PIC16(L)F1825/1829
PDIP, SOIC, SSOP
VDD 1 20 VSS
(1) (1) (1) RA0/AN0/CPS0/C1IN+/VREF-/DACOUT/ICSPDAT/ICDDAT
CCP2 /P2A /T1CKI/SD02 /T1OSI/OSC1/CLKIN/RA5 2 19
T1G(1)/P2B(1)/SS2(1)/CLKR/T1OSO/CLKOUT/OSC2/CPS3/AN3/RA4 3 18 RA1/AN1/CPS1/C12IN0-/VREF+/SRI/ICSPCLK/ICDCLK
PIC16(L)F1829
MCLR/VPP/T1G(1)/RA3 4 17 RA2/AN2/CPS2/T0CKI/INT/C1OUT/SRQ/CCP3/FLT0
MDCIN2/DT(1)/RX(1)/P1A/CCP1/RC5 5 16 RC0/AN4/CPS4/C2IN+/P1D(1)/SS2(1)
(1) (1)
MDOUT/CK /TX /P1B/SRNQ/C2OUT/RC4 6 15 RC1/AN5/CPS5/C12IN1-/P1C(1)/SDO2(1)
MDMIN/P2A(1)/CCP2(1)/P1C(1)/C12IN3-/CPS7/AN7/RC3 7 14 RC2/AN6/CPS6/C12IN2-/P1D(1)/P2B(1)/MDCIN1
SS1/CCP4/CPS8/AN8/RC6 8 13 RB4/AN10/CPS10/SDA1/SDI1
SDO/CPS9/AN9/RC7 9 12 RB5/AN11/CPS11/RX(1)/DT(1)/SDA2/SDI2
(1)
SCK2/SCL2/CK /TX /RB7(1)
10 11 RB6/SCL1/SCK1
Preliminary
T1G(1)/P2B(1)/SS2(1)/CLKR/T1OSO/CLKOUT/OSC2/CPS3/AN3/RA4
QFN 4x4
ICDDAT/ICSPDAT/DACOUT/VREF-/C1IN+/CPS0/AN0/RA0
CCP2(1)/P2A(1)/T1CKI/SDO2(1)/T1OSI/OSC1/CLKIN/RA5
Preliminary
VDD
Vss
20
19
18
17
16
MCLR/VPP/T1G(1)/RA3 1 15 RA1/AN1/CPS1/C12IN0-/VREF+/SRI/ICSPCLK/ICDCLK
PIC16(L)F1825/1829
MDCIN2/DT(1)/RX(1)/P1A/CCP1/RC5 2 14 RA2/AN2/CPS2/T0CKI/INT/C1OUT/SRQ/CCP3/FLT0
MDOUT/CK(1)/TX(1)/P1B/SRNQ/C2OUT/RC4 3 PIC16(L)F1829 13 RC0/AN4/CPS4/C2IN+/P1D(1)/SS2(1)
MDMIN/P2A(1)/CCP2(1)/P1C(1)/C12IN3-/CPS7/AN7/RC3 4 12 RC1/AN5/CPS5/C12IN1-/P1C(1)/SDO2(1)
SS1/CCP4/CPS8/AN8/RC6 5 11 RC2/AN6/CPS6/C12IN2-/P1D(1)/P2B(1)/MDCIN1
10
6
7
8
9
RC7/AN9/CPS9/SDO
RB7/TX(1)/CK(1)/SCL2/SCK2
RB5/AN11/CPS11/RX(1)/DT(1)/SDA2/SDI2
RB6/SCL1/SCK1
RB4/AN10/CPS10/SDA1/SDI1
DS41440B-page 9
20-Pin PDIP/SOIC/SSOP
Comparator
20-Pin QFN
Cap Sense
Reference
Modulator
SR Latch
EUSART
Interrupt
Pull-up
Timers
Basic
CCP
SSP
A/D
I/O
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
Microchips Worldwide Web site; http://www.microchip.com
Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
using.
PIC16(L)F1825
PIC16(L)F1829
Peripheral
ADC
Capacitive Sensing (CPS) Module
Data EEPROM
Digital-to-Analog Converter (DAC)
Digital Signal Modulator (DSM)
EUSART
Fixed Voltage Reference (FVR)
SR Latch
Capture/Compare/PWM Modules
ECCP1
ECCP2
CCP3
CCP4
Comparators
C1
C2
Master Synchronous Serial Ports
MSSP1
MSSP2
Timers
Timer0
Timer1
Timer2
Timer4
Timer6
Program
Flash Memory
RAM EEPROM
CLKR
Clock
Reference
OSC2/CLKOUT Timing
Generation PORTA
OSC1/CLKIN INTRC
CPU
Oscillator PORTB(3)
(Figure 2-1)
MCLR
PORTC
ADC
10-Bit Timer0 Timer1 Timer2 Timer4 Timer6 Comparators
SR MSSP
ECCP1 ECCP2 CCP3 CCP4 EUSART
Latch
15 Configuration
15 Data Bus 8
Program Counter
Flash
MUX
Program
Memory 16-Level
8 Level Stack
Stack
RAM
(13-bit)
(15-bit)
Program
14 Program Memory 12 RAM Addr
Bus
Read (PMR)
Addr MUX
Instruction
Instruction Reg
reg Indirect
Direct Addr 7 Addr
5 12 12
15 BSR
FSR Reg
reg
FSR0reg
FSR Reg
FSR1 Reg
FSR reg
15 STATUS Reg
STATUS reg
8
3 MUX
Power-up
Timer
Instruction Oscillator
Decodeand
Decode & Start-up Timer
ALU
Control
OSC1/CLKIN Power-on
Reset 8
Timing Watchdog
OSC2/CLKOUT Generation Timer W Reg
Brown-out
Reset
Internal
Oscillator
Block
VDD VSS
Rollover to Page 3
7FFFh
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared q = Value depends on condition
Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the twos complement of the
second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order
bit of the source register.
6Fh
70h
Common RAM
(16 bytes)
7Fh
PIC16(L)F1825/1829
BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7
000h INDF0 080h INDF0 100h INDF0 180h INDF0 200h INDF0 280h INDF0 300h INDF0 380h INDF0
001h INDF1 081h INDF1 101h INDF1 181h INDF1 201h INDF1 281h INDF1 301h INDF1 381h INDF1
002h PCL 082h PCL 102h PCL 182h PCL 202h PCL 282h PCL 302h PCL 382h PCL
003h STATUS 083h STATUS 103h STATUS 183h STATUS 203h STATUS 283h STATUS 303h STATUS 383h STATUS
004h FSR0L 084h FSR0L 104h FSR0L 184h FSR0L 204h FSR0L 284h FSR0L 304h FSR0L 384h FSR0L
005h FSR0H 085h FSR0H 105h FSR0H 185h FSR0H 205h FSR0H 285h FSR0H 305h FSR0H 385h FSR0H
006h FSR1L 086h FSR1L 106h FSR1L 186h FSR1L 206h FSR1L 286h FSR1L 306h FSR1L 386h FSR1L
007h FSR1H 087h FSR1H 107h FSR1H 187h FSR1H 207h FSR1H 287h FSR1H 307h FSR1H 387h FSR1H
008h BSR 088h BSR 108h BSR 188h BSR 208h BSR 288h BSR 308h BSR 388h BSR
009h WREG 089h WREG 109h WREG 189h WREG 209h WREG 289h WREG 309h WREG 389h WREG
00Ah PCLATH 08Ah PCLATH 10Ah PCLATH 18Ah PCLATH 20Ah PCLATH 28Ah PCLATH 30Ah PCLATH 38Ah PCLATH
00Bh INTCON 08Bh INTCON 10Bh INTCON 18Bh INTCON 20Bh INTCON 28Bh INTCON 30Bh INTCON 38Bh INTCON
00Ch PORTA 08Ch TRISA 10Ch LATA 18Ch ANSELA 20Ch WPUA 28Ch 30Ch 38Ch INLVLA
00Dh PORTB(1) 08Dh TRISB(1) 10Dh LATB(1) 18Dh ANSELB(1) 20Dh WPUB(1) 28Dh 30Dh 38Dh INLVLB(1)
00Eh PORTC 08Eh TRISC 10Eh LATC 18Eh ANSELC 20Eh WPUC 28Eh 30Eh 38Eh INLVLC
00Fh 08Fh 10Fh 18Fh 20Fh 28Fh 30Fh 38Fh
010h 090h 110h 190h 210h 290h 310h 390h
011h PIR1 091h PIE1 111h CM1CON0 191h EEADRL 211h SSP1BUF 291h CCPR1L 311h CCPR3L 391h IOCAP
012h PIR2 092h PIE2 112h CM1CON1 192h EEADRH 212h SSP1ADD 292h CCPR1H 312h CCPR3H 392h IOCAN
013h 093h 113h CM2CON0 193h EEDATL 213h SSP1MSK 293h CCP1CON 313h CCP3CON 393h IOCAF
014h 094h 114h CM2CON1 194h EEDATH 214h SSP1STAT 294h PWM1CON 314h 394h IOCBP(1)
Preliminary
015h TMR0 095h OPTION_REG 115h CMOUT 195h EECON1 215h SSP1CON 295h CCP1AS 315h 395h IOCBN(1)
016h TMR1L 096h PCON 116h BORCON 196h EECON2 216h SSP1CON2 296h PSTR1CON 316h 396h IOCBF(1)
017h TMR1H 097h WDTCON 117h FVRCON 197h 217h SSP1CON3 297h 317h 397h
018h T1CON 098h OSCTUNE 118h DACCON0 198h 218h 298h CCPR2L 318h CCPR4L 398h
019h T1GCON 099h OSCCON 119h DACCON1 199h RCREG 219h SSP2BUF(1) 299h CCPR2H 319h CCPR4H 399h
01Ah TMR2 09Ah OSCSTAT 11Ah SRCON0 19Ah TXREG 21Ah SSP2ADD(1) 29Ah CCP2CON 31Ah CCP4CON 39Ah CLKRCON
01Bh PR2 09Bh ADRESL 11Bh SRCON1 19Bh SPBRGL 21Bh SSP2MSK(1) 29Bh PWM2CON 31Bh 39Bh
01Ch T2CON 09Ch ADRESH 11Ch 19Ch SPBRGH 21Ch SSP2STAT(1) 29Ch CCP2AS 31Ch 39Ch MDCON
01Dh 09Dh ADCON0 11Dh APFCON0 19Dh RCSTA 21Dh SSP2CON(1) 29Dh PSTR2CON 31Dh 39Dh MDSRC
01Eh CPSCON0 09Eh ADCON1 11Eh APFCON1 19Eh TXSTA 21Eh SSP2CON2(1) 29Eh CCPTMRS 31Eh 39Eh MDCARL
01Fh CPSCON1 09Fh 11Fh 19Fh BAUDCON 21Fh SSP2CON3(1) 29Fh 31Fh 39Fh MDCARH
2010-2011 Microchip Technology Inc.
PIC16(L)F1825/1829
41Ch TMR6 49Ch 51Ch 59Ch 61Ch 69Ch 71Ch 79Ch
41Dh PR6 49Dh 51Dh 59Dh 61Dh 69Dh 71Dh 79Dh
41Eh T6CON 49Eh 51Eh 59Eh 61Eh 69Eh 71Eh 79Eh
41Fh 49Fh 51Fh 59Fh 61Fh 69Fh 71Fh 79Fh
420h 4A0h 520h 5A0h 620h General Purpose 6A0h 720h 7A0h
General General General General Register
Purpose Purpose Purpose Purpose 64Fh 48 Bytes Unimplemented Unimplemented Unimplemented
Register Register Register Register 650h Read as 0 Read as 0 Read as 0
80 Bytes 80 Bytes 80 Bytes 80 Bytes Unimplemented
Read as 0
46Fh 4EFh 56Fh 5EFh 66Fh 6EFh 76Fh 7EFh
470h 4F0h 570h 5F0h 670h 6F0h 770h 7F0h
Accesses Accesses Accesses Accesses Accesses Accesses Accesses Accesses
70h 7Fh 70h 7Fh 70h 7Fh 70h 7Fh 70h 7Fh 70h 7Fh 70h 7Fh 70h 7Fh
47Fh 4FFh 57Fh 5FFh 67Fh 6FFh 77Fh 7FFh
DS41440B-page 29
PIC16(L)F1825/1829
BANK 16 BANK 17 BANK 18 BANK 19 BANK 20 BANK 21 BANK 22 BANK 23
800h INDF0 880h INDF0 900h INDF0 980h INDF0 A00h INDF0 A80h INDF0 B00h INDF0 B80h INDF0
801h INDF1 881h INDF1 901h INDF1 981h INDF1 A01h INDF1 A81h INDF1 B01h INDF1 B81h INDF1
802h PCL 882h PCL 902h PCL 982h PCL A02h PCL A82h PCL B02h PCL B82h PCL
803h STATUS 883h STATUS 903h STATUS 983h STATUS A03h STATUS A83h STATUS B03h STATUS B83h STATUS
804h FSR0L 884h FSR0L 904h FSR0L 984h FSR0L A04h FSR0L A84h FSR0L B04h FSR0L B84h FSR0L
805h FSR0H 885h FSR0H 905h FSR0H 985h FSR0H A05h FSR0H A85h FSR0H B05h FSR0H B85h FSR0H
806h FSR1L 886h FSR1L 906h FSR1L 986h FSR1L A06h FSR1L A86h FSR1L B06h FSR1L B86h FSR1L
807h FSR1H 887h FSR1H 907h FSR1H 987h FSR1H A07h FSR1H A87h FSR1H B07h FSR1H B87h FSR1H
808h BSR 888h BSR 908h BSR 988h BSR A08h BSR A88h BSR B08h BSR B88h BSR
809h WREG 889h WREG 909h WREG 989h WREG A09h WREG A89h WREG B09h WREG B89h WREG
80Ah PCLATH 88Ah PCLATH 90Ah PCLATH 98Ah PCLATH A0Ah PCLATH A8Ah PCLATH B0Ah PCLATH B8Ah PCLATH
80Bh INTCON 88Bh INTCON 90Bh INTCON 98Bh INTCON A0Bh INTCON A8Bh INTCON B0Bh INTCON B8Bh INTCON
80Ch 88Ch 90Ch 98Ch A0Ch A8Ch B0Ch B8Ch
80Dh 88Dh 90Dh 98Dh A0Dh A8Dh B0Dh B8Dh
80Eh 88Eh 90Eh 98Eh A0Eh A8Eh B0Eh B8Eh
80Fh 88Fh 90Fh 98Fh A0Fh A8Fh B0Fh B8Fh
810h 890h 910h 990h A10h A90h B10h B90h
811h 891h 911h 991h A11h A91h B11h B91h
812h 892h 912h 992h A12h A92h B12h B92h
Preliminary
PIC16(L)F1825/1829
C19h C99h D19h D99h E19h E99h F19h F99h details
C1Ah C9Ah D1Ah D9Ah E1Ah E9Ah F1Ah F9Ah
C1Bh C9Bh D1Bh D9Bh E1Bh E9Bh F1Bh F9Bh
C1Ch C9Ch D1Ch D9Ch E1Ch E9Ch F1Ch F9Ch
C1Dh C9Dh D1Dh D9Dh E1Dh E9Dh F1Dh F9Dh
C1Eh C9Eh D1Eh D9Eh E1Eh E9Eh F1Eh F9Eh
C1Fh C9Fh D1Fh D9Fh E1Fh E9Fh F1Fh F9Fh
C20h CA0h D20h DA0h E20h EA0h F20h FA0h
Bank 1
080h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory xxxx xxxx xxxx xxxx
(not a physical register)
081h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory xxxx xxxx xxxx xxxx
(not a physical register)
082h(1) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000
083h(1) STATUS TO PD Z DC C ---1 1000 ---q quuu
084h(1) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu
085h(1) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000
086h(1) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu
087h(1) FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000
088h(1) BSR BSR<4:0> ---0 0000 ---0 0000
089h(1) WREG Working Register 0000 0000 uuuu uuuu
08Ah(1) PCLATH Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000
08Bh(1) INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000
08Ch TRISA TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111
08Dh TRISB(2) TRISB7 TRISB6 TRISB5 TRISB4 1111 ---- 1111 ----
08Eh TRISC TRISC7(2) TRISC6(2) TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111
08Fh Unimplemented
090h Unimplemented
091h PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
092h PIE2 OSFIE C2IE C1IE EEIE BCL1IE CCP2IE 0000 0--0 0000 0--0
093h PIE3 CCP4IE CCP3IE TMR6IE TMR4IE --00 0-0- --00 0-0-
094h PIE4(2) BCL2IE SSP2IE ---- --00 ---- --00
095h OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0> 1111 1111 1111 1111
096h PCON STKOVF STKUNF RMCLR RI POR BOR 00-- 11qq qq-- qquu
097h WDTCON WDTPS<4:0> SWDTEN --01 0110 --01 0110
098h OSCTUNE TUN<5:0> --00 0000 --00 0000
099h OSCCON SPLLEN IRCF<3:0> SCS<1:0> 0011 1-00 0011 1-00
09Ah OSCSTAT T1OSCR PLLR OSTS HFIOFR HFIOFL MFIOFR LFIOFR HFIOFS 10q0 0q00 qqqq qq0q
09Bh ADRESL A/D Result Register Low xxxx xxxx uuuu uuuu
09Ch ADRESH A/D Result Register High xxxx xxxx uuuu uuuu
09Dh ADCON0 CHS<4:0> GO/DONE ADON -000 0000 -000 0000
09Eh ADCON1 ADFM ADCS<2:0> ADNREF ADPREF<1:0> 0000 -000 0000 -000
09Fh Unimplemented
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved.
Shaded locations are unimplemented, read as 0.
Note 1: These registers can be addressed from any bank.
2: PIC16(L)F1829 only.
3: PIC16(L)F1825 only.
Bank 2
100h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory xxxx xxxx xxxx xxxx
(not a physical register)
101h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory xxxx xxxx xxxx xxxx
(not a physical register)
102h(1) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000
103h(1) STATUS TO PD Z DC C ---1 1000 ---q quuu
104h(1) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu
105h(1) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000
106h(1) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu
107h(1) FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000
108h(1) BSR BSR<4:0> ---0 0000 ---0 0000
109h(1) WREG Working Register 0000 0000 uuuu uuuu
10Ah(1) PCLATH Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000
10Bh(1) INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000
10Ch LATA LATA5 LATA4 LATA2 LATA1 LATA0 --xx -xxx --uu -uuu
10Dh LATB(2) LATB7 LATB6 LATB5 LATB4 xxxx ---- xxxx ----
10Eh LATC LATC7(2) LATC6(2) LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 xxxx xxxx uuuu uuuu
10Fh Unimplemented
110h Unimplemented
111h CM1CON0 C1ON C1OUT C1OE C1POL C1SP C1HYS C1SYNC 0000 -100 0000 -100
112h CM1CON1 C1INTP C1INTN C1PCH<1:0> C1NCH1 C1NCH0 0000 ---0 0000 ---0
113h CM2CON0 C2ON C2OUT C2OE C2POL C2SP C2HYS C2SYNC 0000 -100 0000 -100
114h CM2CON1 C2INTP C2INTN C2PCH<1:0> C2NCH<1:0> 0000 --00 0000 --00
115h CMOUT MC2OUT MC1OUT ---- --00 ---- --00
116h BORCON SBOREN BORRDY 1--- ---q u--- ---u
117h FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> ADFVR<1:0> 0q00 0000 0q00 0000
118h DACCON0 DACEN DACLPS DACOE DACPSS<1:0> DACNSS 000- 00-0 000- 00-0
119h DACCON1 DACR<4:0> ---0 0000 ---0 0000
11Ah SRCON0 SRLEN SRCLK<2:0> SRQEN SRNQEN SRPS SRPR 0000 0000 0000 0000
11Bh SRCON1 SRSPE SRSCKE SRSC2E(2) SRSC1E SRRPE SRRCKE SRRC2E(2) SRRC1E 0000 0000 0000 0000
11Ch Unimplemented
11Dh APFCON0 RXDTSEL SDOSEL(3) SSSEL(3) T1GSEL TXCKSEL 000- 0000 000- 0000
11Eh APFCON1 SDO2SEL(2) SS2SEL(2) P1DSEL P1CSEL P2BSEL CCP2SEL --00 0000 --00 0000
11Fh Unimplemented
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved.
Shaded locations are unimplemented, read as 0.
Note 1: These registers can be addressed from any bank.
2: PIC16(L)F1829 only.
3: PIC16(L)F1825 only.
Bank 3
180h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory xxxx xxxx xxxx xxxx
(not a physical register)
181h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory xxxx xxxx xxxx xxxx
(not a physical register)
182h(1) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000
183h(1) STATUS TO PD Z DC C ---1 1000 ---q quuu
184h(1) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu
185h(1) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000
186h(1) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu
187h(1) FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000
188h(1) BSR BSR<4:0> ---0 0000 ---0 0000
189h(1) WREG Working Register 0000 0000 uuuu uuuu
18Ah(1) PCLATH Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000
18Bh(1) INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000
18Ch ANSELA ANSA4 ANSA2 ANSA1 ANSA0 ---1 -111 ---1 -111
18Dh ANSELB(2) ANSB7 ANSB6 ANSB5 ANSB4 1111 ---- 1111 ----
18Eh ANSELC ANSC7(2) ANSC6(2) ANSC3 ANSC2 ANSC1 ANSC0 11-- 1111 11-- 1111
18Fh Unimplemented
190h Unimplemented
191h EEADRL EEPROM / Program Memory Address Register Low Byte 0000 0000 0000 0000
192h EEADRH EEPROM / Program Memory Address Register High Byte -000 0000 -000 0000
193h EEDATL EEPROM / Program Memory Read Data Register Low Byte xxxx xxxx uuuu uuuu
194h EEDATH EEPROM / Program Memory Read Data Register High Byte --xx xxxx --uu uuuu
195h EECON1 EEPGD CFGS LWLO FREE WRERR WREN WR RD 0000 x000 0000 q000
196h EECON2 EEPROM control register 2 0000 0000 0000 0000
197h Unimplemented
198h Unimplemented
199h RCREG USART Receive Data Register 0000 0000 0000 0000
19Ah TXREG USART Transmit Data Register 0000 0000 0000 0000
19Bh SPBRGL Baud Rate Generator Data Register Low 0000 0000 0000 0000
19Ch SPBRGH Baud Rate Generator Data Register High 0000 0000 0000 0000
19Dh RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
19Eh TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010
19Fh BAUDCON ABDOVF RCIDL SCKP BRG16 WUE ABDEN 01-0 0-00 01-0 0-00
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved.
Shaded locations are unimplemented, read as 0.
Note 1: These registers can be addressed from any bank.
2: PIC16(L)F1829 only.
3: PIC16(L)F1825 only.
Bank 4
200h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory xxxx xxxx xxxx xxxx
(not a physical register)
201h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory xxxx xxxx xxxx xxxx
(not a physical register)
202h(1) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000
203h(1) STATUS TO PD Z DC C ---1 1000 ---q quuu
204h(1) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu
205h(1) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000
206h(1) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu
207h(1) FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000
208h(1) BSR BSR<4:0> ---0 0000 ---0 0000
209h(1) WREG Working Register 0000 0000 uuuu uuuu
20Ah(1) PCLATH Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000
20Bh(1) INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000
20Ch WPUA WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 --11 1111 --11 1111
20Dh WPUB WPUB7 WPUB6 WPUB5 WPUB4 1111 ---- 1111 ----
20Eh WPUC WPUC7(2) WPUC6(2) WPUC5 WPUC4 WPUC3 WPUC2 WPUC1 WPUC0 1111 1111 1111 1111
20Fh Unimplemented
210h Unimplemented
211h SSP1BUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
212h SSP1ADD ADD<7:0> 0000 0000 0000 0000
213h SSP1MSK MSK<7:0> 1111 1111 1111 1111
214h SSP1STAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000
215h SSP1CON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 0000 0000 0000 0000
216h SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 0000 0000
217h SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 0000 0000 0000 0000
218h Unimplemented
219h SSP2BUF(2) Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
21Ah SSP2ADD(2) ADD<7:0> 0000 0000 0000 0000
21Bh SSP2MSK(2) MSK<7:0> 1111 1111 1111 1111
21Ch SSP2STAT(2) SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000
21Dh SSP2CON1(2) WCOL SSPOV SSPEN CKP SSPM<3:0> 0000 0000 0000 0000
21Eh SSP2CON2(2) GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 0000 0000
21Fh SSP2CON3(2) ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved.
Shaded locations are unimplemented, read as 0.
Note 1: These registers can be addressed from any bank.
2: PIC16(L)F1829 only.
3: PIC16(L)F1825 only.
Bank 5
280h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory xxxx xxxx xxxx xxxx
(not a physical register)
281h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory xxxx xxxx xxxx xxxx
(not a physical register)
282h(1) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000
283h(1) STATUS TO PD Z DC C ---1 1000 ---q quuu
284h(1) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu
285h(1) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000
286h(1) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu
287h(1) FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000
288h(1) BSR BSR<4:0> ---0 0000 ---0 0000
289h(1) WREG Working Register 0000 0000 uuuu uuuu
28Ah(1) PCLATH Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000
28Bh(1) INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000
28Ch Unimplemented
28Dh Unimplemented
28Eh Unimplemented
28Fh Unimplemented
290h Unimplemented
291h CCPR1L Capture/Compare/PWM Register 1 (LSB) xxxx xxxx uuuu uuuu
292h CCPR1H Capture/Compare/PWM Register 1 (MSB) xxxx xxxx uuuu uuuu
293h CCP1CON P1M<1:0> DC1B<1:0> CCP1M<3:0> 0000 0000 0000 0000
294h PWM1CON P1RSEN P1DC<6:0> 0000 0000 0000 0000
295h CCP1AS CCP1ASE CCP1AS<2:0> PSS1AC<1:0> PSS1BD<1:0> 0000 0000 0000 0000
296h PSTR1CON STR1SYNC STR1D STR1C STR1B STR1A ---0 0001 ---0 0001
297h Unimplemented
298h CCPR2L Capture/Compare/PWM Register 2 (LSB) xxxx xxxx uuuu uuuu
299h CCPR2H Capture/Compare/PWM Register 2 (MSB) xxxx xxxx uuuu uuuu
29Ah CCP2CON P2M1 P2M0 DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 0000 0000 0000 0000
29Bh PWM2CON P2RSEN P2DC6 P2DC5 P2DC4 P2DC3 P2DC2 P2DC1 P2DC0 0000 0000 0000 0000
29Ch CCP2AS CCP2ASE CCP2AS2 CCP2AS1 CCP2AS0 PSS2AC1 PSS2AC0 PSS2BD1 PSS2BD0 0000 0000 0000 0000
29Dh PSTR2CON STR2SYNC STR2D STR2C STR2B STR2A ---0 0001 ---0 0001
29Eh CCPTMRS C4TSEL1 C4TSEL0 C3TSEL1 C3TSEL0 C2TSEL1 C2TSEL0 C1TSEL1 C1TSEL0 0000 0000 0000 0000
29Fh Unimplemented
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved.
Shaded locations are unimplemented, read as 0.
Note 1: These registers can be addressed from any bank.
2: PIC16(L)F1829 only.
3: PIC16(L)F1825 only.
Bank 6
300h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory xxxx xxxx xxxx xxxx
(not a physical register)
301h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory xxxx xxxx xxxx xxxx
(not a physical register)
302h(1) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000
303h(1) STATUS TO PD Z DC C ---1 1000 ---q quuu
304h(1) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu
305h(1) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000
306h(1) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu
307h(1) FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000
308h(1) BSR BSR<4:0> ---0 0000 ---0 0000
309h(1) WREG Working Register 0000 0000 uuuu uuuu
30Ah(1) PCLATH Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000
30Bh(1) INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000
30Ch Unimplemented
30Dh Unimplemented
30Eh Unimplemented
30Fh Unimplemented
310h Unimplemented
311h CCPR3L Capture/Compare/PWM Register 3 (LSB) xxxx xxxx uuuu uuuu
312h CCPR3H Capture/Compare/PWM Register 3 (MSB) xxxx xxxx uuuu uuuu
313h CCP3CON DC3B1 DC3B0 CCP3M3 CCP3M2 CCP3M1 CCP3M0 --00 0000 --00 0000
314h Unimplemented
315h Unimplemented
316h Unimplemented
317h Unimplemented
318h CCPR4L Capture/Compare/PWM Register 4 (LSB) xxxx xxxx uuuu uuuu
319h CCPR4H Capture/Compare/PWM Register 4 (MSB) xxxx xxxx uuuu uuuu
31Ah CCP4CON DC4B1 DC4B0 CCP4M3 CCP4M2 CCP4M1 CCP4M0 --00 0000 --00 0000
31Bh Unimplemented
31Ch Unimplemented
31Dh Unimplemented
31Eh Unimplemented
31Fh Unimplemented
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved.
Shaded locations are unimplemented, read as 0.
Note 1: These registers can be addressed from any bank.
2: PIC16(L)F1829 only.
3: PIC16(L)F1825 only.
Bank 7
380h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory xxxx xxxx xxxx xxxx
(not a physical register)
381h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory xxxx xxxx xxxx xxxx
(not a physical register)
382h(1) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000
383h(1) STATUS TO PD Z DC C ---1 1000 ---q quuu
384h(1) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu
385h(1) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000
386h(1) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu
387h(1) FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000
388h(1) BSR BSR<4:0> ---0 0000 ---0 0000
389h(1) WREG Working Register 0000 0000 uuuu uuuu
38Ah(1) PCLATH Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000
38Bh(1) INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000
38Ch INLVLA INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0 --00 0100 --00 0100
38Dh INLVLB(2) INLVLB7 INLVLB6 INLVLB5 INLVLB4 0000 ---- 0000 ----
38Eh INLVLC INLVLC7(2) INLVLC6(2) INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0 11xx xxxx 11xx xxxx
38Fh Unimplemented
390h Unimplemented
391h IOCAP IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 --00 0000 --00 0000
392h IOCAN IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 --00 0000 --00 0000
393h IOCAF IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 --00 0000 --00 0000
394h IOCBP(2) IOCBP7 IOCBP6 IOCBP5 IOCBP4 0000 ---- 0000 ----
395h IOCBN(2) IOCBN7 IOCBN6 IOCBN5 IOCBN4 0000 ---- 0000 ----
396h IOCBF(2) IOCBF7 IOCBF6 IOCBF5 IOCBF4 0000 ---- 0000 ----
397h Unimplemented
398h Unimplemented
399h Unimplemented
39Ah CLKRCON CLKREN CLKROE CLKRSLR CLKRDC<1:0> CLKRDIV<2:0> 0011 0000 0011 0000
39Bh Unimplemented
39Ch MDCON MDEN MDOE MDSLR MDOPOL MDOUT MDBIT 0010 ---0 0010 ---0
39Dh MDSRC MDMSODIS MDMS<3:0> x--- xxxx u--- uuuu
39Eh MDCARL MDCLODIS MDCLPOL MDCLSYNC MDCL<3:0> xxx- xxxx uuu- uuuu
39Fh MDCARH MDCHODIS MDCHPOL MDCHSYNC MDCH<3:0> xxx- xxxx uuu- uuuu
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved.
Shaded locations are unimplemented, read as 0.
Note 1: These registers can be addressed from any bank.
2: PIC16(L)F1829 only.
3: PIC16(L)F1825 only.
Bank 8
400h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory xxxx xxxx xxxx xxxx
(not a physical register)
401h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory xxxx xxxx xxxx xxxx
(not a physical register)
402h(1) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000
403h(1) STATUS TO PD Z DC C ---1 1000 ---q quuu
404h(1) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu
405h(1) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000
406h(1) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu
407h(1) FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000
408h(1) BSR BSR<4:0> ---0 0000 ---0 0000
409h(1) WREG Working Register 0000 0000 uuuu uuuu
40Ah(1) PCLATH Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000
40Bh(1) INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000
40Ch Unimplemented
40Dh Unimplemented
40Eh Unimplemented
40Fh Unimplemented
410h Unimplemented
411h Unimplemented
412h Unimplemented
413h Unimplemented
414h Unimplemented
415h TMR4 Timer4 Module Register 0000 0000 0000 0000
416h PR4 Timer4 Period Register 1111 1111 1111 1111
417h T4CON T4OUTPS<3:0> TMR4ON T4CKPS<1:0> -000 0000 -000 0000
418h Unimplemented
419h Unimplemented
41Ah Unimplemented
41Bh Unimplemented
41Ch TMR6 Timer6 Module Register 0000 0000 0000 0000
41Dh PR6 Timer6 Period Register 1111 1111 1111 1111
41Eh T6CON T6OUTPS<3:0> TMR6ON T6CKPS<1:0> -000 0000 -000 0000
41Fh Unimplemented
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved.
Shaded locations are unimplemented, read as 0.
Note 1: These registers can be addressed from any bank.
2: PIC16(L)F1829 only.
3: PIC16(L)F1825 only.
Banks 9-30
x00h/ INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory xxxx xxxx xxxx xxxx
x80h(1) (not a physical register)
x00h/ INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory xxxx xxxx xxxx xxxx
x81h(1) (not a physical register)
x02h/ PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000
x82h(1)
x03h/ STATUS TO PD Z DC C ---1 1000 ---q quuu
x83h(1)
x04h/ FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu
x84h(1)
x05h/ FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000
x85h(1)
x06h/ FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu
x86h(1)
x07h/ FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000
x87h(1)
x08h/ BSR BSR<4:0> ---0 0000 ---0 0000
x88h(1)
x09h/ WREG Working Register 0000 0000 uuuu uuuu
x89h(1)
x0Ah/ PCLATH Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000
x8Ah(1)
x0Bh/ INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000
x8Bh(1)
x0Ch/ Unimplemented
x8Ch
x1Fh/
x9Fh
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved.
Shaded locations are unimplemented, read as 0.
Note 1: These registers can be addressed from any bank.
2: PIC16(L)F1829 only.
3: PIC16(L)F1825 only.
Bank 31
F80h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory xxxx xxxx xxxx xxxx
(not a physical register)
F81h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory xxxx xxxx xxxx xxxx
(not a physical register)
F82h(1) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000
F83h(1) STATUS TO PD Z DC C ---1 1000 ---q quuu
F84h(1) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu
F85h(1) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000
F86h(1) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu
F87h(1) FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000
F88h(1) BSR BSR<4:0> ---0 0000 ---0 0000
F89h(1) WREG Working Register 0000 0000 uuuu uuuu
F8Ah(1) PCLATH Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000
F8Bh(1) INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000
F8Ch Unimplemented
FE3h
FE4h STATUS_ Z_SHAD DC_SHAD C_SHAD ---- -xxx ---- -uuu
SHAD
FE5h WREG_ Working Register Shadow 0000 0000 uuuu uuuu
SHAD
FE6h BSR_ Bank Select Register Shadow ---x xxxx ---u uuuu
SHAD
FE7h PCLATH_ Program Counter Latch High Register Shadow -xxx xxxx uuuu uuuu
SHAD
FE8h FSR0L_ Indirect Data Memory Address 0 Low Pointer Shadow xxxx xxxx uuuu uuuu
SHAD
FE9h FSR0H_ Indirect Data Memory Address 0 High Pointer Shadow xxxx xxxx uuuu uuuu
SHAD
FEAh FSR1L_ Indirect Data Memory Address 1 Low Pointer Shadow xxxx xxxx uuuu uuuu
SHAD
FEBh FSR1H_ Indirect Data Memory Address 1 High Pointer Shadow xxxx xxxx uuuu uuuu
SHAD
FECh Unimplemented
FEDh STKPTR Current Stack pointer ---1 1111 ---1 1111
FEEh TOSL Top-of-Stack Low byte xxxx xxxx uuuu uuuu
FEFh TOSH Top-of-Stack High byte -xxx xxxx -uuu uuuu
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved.
Shaded locations are unimplemented, read as 0.
Note 1: These registers can be addressed from any bank.
2: PIC16(L)F1829 only.
3: PIC16(L)F1825 only.
15
PC + OPCODE <8:0>
0x0F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09 This figure shows the stack configuration
after the first CALL or a single interrupt.
0x08 If a RETURN instruction is executed, the
0x07 return address will be placed in the
Program Counter and the Stack Pointer
0x06 decremented to the empty state (0x1F).
0x05
0x04
0x03
0x02
0x01
TOSH:TOSL 0x00 Return Address STKPTR = 0x00
0x0F
0x0E
0x0D
0x0C
After seven CALLs or six CALLs and an
0x0B interrupt, the stack looks like the figure
on the left. A series of RETURN instructions
0x0A will repeatedly place the return addresses
into the Program Counter and pop the stack.
0x09
0x08
0x07
TOSH:TOSL 0x06 Return Address STKPTR = 0x06
0x0000 0x0000
Traditional
Data Memory
0x0FFF 0x0FFF
0x1000
Reserved
0x1FFF
0x2000
Linear
Data Memory
0x29AF
0x29B0
FSR Reserved
0x7FFF
Address
Range 0x8000 0x0000
Program
Flash Memory
0xFFFF 0x7FFF
Note: Not all memory regions are completely implemented. Consult device memory tables for memory limits.
0x7F
Bank 0 Bank 1 Bank 2 Bank 31
0xF20
Bank 30 0x7FFF
0xFFFF
0x29AF 0xF6F
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 1
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared P = Programmable bit
Note 1: Enabling Brown-out Reset does not automatically enable Power-up Timer.
2: The entire data EEPROM will be erased when the code protection is turned off during an erase.
3: The entire program memory will be erased when the code protection is turned off.
Note 1: Enabling Brown-out Reset does not automatically enable Power-up Timer.
2: The entire data EEPROM will be erased when the code protection is turned off during an erase.
3: The entire program memory will be erased when the code protection is turned off.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 1
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared P = Programmable bit
Note 1: The LVP bit cannot be programmed to 0 when Programming mode is entered via LVP.
2: The DEBUG bit in Configuration Word is managed automatically by device development tools including debuggers and
programmers. For normal device operation, this bit should be maintained as a 1.
4.4 User ID
Four memory locations (8000h-8003h) are designated as
ID locations where the user can store checksum or other
code identification numbers. These locations are
readable and writable during normal execution. See
Section 11.5 User ID, Device ID and Configuration
Word Access for more information on accessing these
memory locations. For more information on checksum
calculation, see the PIC16F/LF182X/PIC12F/LF1822
Memory Programming Specification (DS41390).
R R R R R R R
DEV1 DEV0 REV4 REV3 REV2 REV1 REV0
bit 6 bit 0
External
Oscillator LP, XT, HS, RC, EC
OSC2
Sleep
4 x PLL Sleep
OSC1
Oscillator Timer1 FOSC<2:0> = 100 T1OSC CPU and
MUX
T1OSO Peripherals
T1OSCEN
Enable
T1OSI Oscillator IRCF<3:0>
Internal Oscillator
16 MHz
8 MHz
Internal
Oscillator 4 MHz
Block 2 MHz
Postscaler 1 MHz Clock
HFPLL Control
MUX
16 MHz 500 kHz
(HFINTOSC) 250 kHz
125 kHz FOSC<2:0> SCS<1:0>
500 kHz
Source 500 kHz 62.5 kHz
(MFINTOSC) 31.25 kHz Clock Source Option
31 kHz for other modules
31 kHz
Source
OSC1/CLKIN OSC1/CLKIN
C1 To Internal C1 To Internal
Logic Logic
Quartz
RF(2) Sleep RP(3)
Crystal RF(2) Sleep
C2 OSC2/CLKOUT
RS(1) OSC2/CLKOUT
C2 Ceramic RS(1)
Resonator
Note 1: A series resistor (RS) may be required for
quartz crystals with low drive level. Note 1: A series resistor (RS) may be required for
ceramic resonators with low drive level.
2: The value of RF varies with the Oscillator mode
selected (typically between 2 M to 10 M. 2: The value of RF varies with the Oscillator mode
selected (typically between 2 M to 10 M.
3: An additional parallel feedback resistor (RP)
Note 1: Quartz crystal characteristics vary may be required for proper ceramic resonator
according to type, package and operation.
manufacturer. The user should consult the
manufacturer data sheets for specifications
and recommended application. 5.2.1.3 Oscillator Start-up Timer (OST)
2: Always verify oscillator performance over If the oscillator module is configured for LP, XT or HS
the VDD and temperature range that is modes, the Oscillator Start-up Timer (OST) counts
expected for the application. 1024 oscillations from OSC1. This occurs following a
3: For oscillator design assistance, reference Power-on Reset (POR) and when the Power-up Timer
the following Microchip Application Notes: (PWRT) has expired (if configured), or a wake-up from
Sleep. During this time, the program counter does not
AN826, Crystal Oscillator Basics and increment and program execution is suspended. The
Crystal Selection for rfPIC and PIC OST ensures that the oscillator circuit, using a quartz
Devices (DS00826) crystal resonator or ceramic resonator, has started and
AN849, Basic PIC Oscillator Design is providing a stable system clock to the oscillator
(DS00849) module.
AN943, Practical PIC Oscillator In order to minimize latency between external oscillator
Analysis and Design (DS00943) start-up and code execution, the Two-Speed Clock
AN949, Making Your Oscillator Work Start-up mode can be selected (see Section 5.4
(DS00949) Two-Speed Clock Start-up Mode).
5.2.1.4 4X PLL
The oscillator module contains a 4X PLL that can be
used with both external and internal clock sources to
provide a system clock source. The input frequency for
the 4X PLL must fall within specifications. See the PLL
Clock Timing Specifications in Section 30.0
Electrical Specifications.
The 4X PLL may be enabled for use by one of two
methods:
1. Program the PLLEN bit in Configuration Word 2
to a 1.
2. Write the SPLLEN bit in the OSCCON register to
a 1. If the PLLEN bit in Configuration Word 2 is
programmed to a 1, then the value of SPLLEN
is ignored.
LFINTOSC
IRCF <3:0> 0 0
System Clock
LFINTOSC
IRCF <3:0> 0 0
System Clock
LFINTOSC HFINTOSC/MFINTOSC
LFINTOSC turns off unless WDT or FSCM is enabled
LFINTOSC
Start-up Time 2-cycle Sync Running
HFINTOSC/
MFINTOSC
IRCF <3:0> =0 0
System Clock
Default system oscillator determined by FOSC The Timer1 oscillator is enabled using the T1OSCEN
bits in Configuration Word 1 control bit in the T1CON register. See Section 21.0
Timer1 Module with Gate Control for more
Timer1 32 kHz crystal oscillator
information about the Timer1 peripheral.
Internal Oscillator Block (INTOSC)
5.3.4 TIMER1 OSCILLATOR READY
5.3.1 SYSTEM CLOCK SELECT (SCS)
(T1OSCR) BIT
BITS
The user must ensure that the Timer1 Oscillator is
The System Clock Select (SCS) bits of the OSCCON
ready to be used before it is selected as a system clock
register selects the system clock source that is used for
source. The Timer1 Oscillator Ready (T1OSCR) bit of
the CPU and peripherals.
the OSCSTAT register indicates whether the Timer1
When the SCS bits of the OSCCON register = 00, oscillator is ready to be used. After the T1OSCR bit is
the system clock source is determined by value of set, the SCS bits can be configured to select the Timer1
the FOSC<2:0> bits in the Configuration Word 1. oscillator.
When the SCS bits of the OSCCON register = 01,
the system clock source is the Timer1 oscillator.
When the SCS bits of the OSCCON register = 1x,
the system clock source is chosen by the internal
oscillator frequency selected by the IRCF<3:0>
bits of the OSCCON register. After a Reset, the
SCS bits of the OSCCON register are always
cleared.
Note: Any automatic clock switch, which may
occur from Two-Speed Start-up or
Fail-Safe Clock Monitor, does not update
the SCS bits of the OSCCON register. The
user can monitor the OSTS bit of the
OSCSTAT register to determine the current
system clock source.
When switching between clock sources, a delay is
required to allow the new clock to stabilize. These oscil-
lator delays are shown in Table 5-1.
INTOSC
TOST
OSC2
Program Counter PC - N PC PC + 1
System Clock
Sample Clock
System Oscillator
Clock Failure
Output
Note: The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in
this example have been chosen for clarity.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared q = Conditional
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Note 1: If the base clock rate is selected without 6.4 Operation During Sleep
a divider, the output clock will always
have a duty cycle equal to that of the As the Reference Clock module relies on the system
source clock, unless a 0% duty cycle is clock as its source, and the system clock is disabled in
selected. If the clock divider is set to base Sleep, the module does not function in Sleep, even if
clock/2, then 25% and 75% duty cycle an external clock source or the Timer1 clock source is
accuracy will be dependent upon the configured as the system clock. The module outputs
source clock. will remain in their current state until the device exits
Sleep.
For information on using the reference clock output
with the modulator module, see Section 23.0 Data
Signal Modulator.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Note 1: In this mode, the 25% and 75% duty cycle accuracy will be dependent on the source clock duty cycle.
2: In this mode, the duty cycle will always be equal to the source clock duty cycle, unless a duty cycle of 0%
is selected.
3: To route CLKR to pin, CLKOUTEN of Configuration Word 1 = 1 is required. CLKOUTEN of Configuration
Word 1 = 0 will result in FOSC/4. See Section 6.3 Conflicts with the CLKR Pin for details.
External Reset
MCLRE
MCLR
Sleep
WDT
Time-out
Device
Power-on Reset
Reset
VDD
Brown-out
Reset
BOR
Enable
PWRT
Zero
64 ms
LFINTOSC
PWRTEN
VDD
VBOR
Internal
Reset TPWRT(1)
VDD
VBOR
VDD
VBOR
Internal
Reset TPWRT(1)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared q = Value depends on condition
VDD
Internal POR
TPWRT
Power-Up Timer
MCLR
TMCLR
Internal RESET
Oscillator Modes
External Crystal
TOST
Oscillator Start-Up Timer
Oscillator
FOSC
Internal Oscillator
Oscillator
FOSC
CLKIN
FOSC
Legend:
HC = Bit is cleared by hardware HS = Bit is set by hardware
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -m/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared q = Value depends on condition
IOCBNx D Q4Q1
Q
CK edge
detect
R
RBx
CK write IOCBFx CK
IOCIE
R
Q2
from all other
IOCBFx individual IOC interrupt
pin detectors to CPU core
Q1 Q1 Q1
Q2 Q2 Q2
Q3 Q3 Q3
Q4 Q4 Q4 Q4
Q4Q1 Q4Q1 Q4Q1 Q4Q1
OSC1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Interrupt
GIE
Interrupt
GIE
Interrupt
GIE
Interrupt
GIE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT (3)
(4)
INT pin
(1)
(1)
INTF (5) Interrupt Latency (2)
GIE
INSTRUCTION FLOW
PC PC PC + 1 PC + 1 0004h 0005h
Instruction
Fetched Inst (PC) Inst (PC + 1) Inst (0004h) Inst (0005h)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Note 1: The IOCIF Flag bit is read-only and cleared when all the Interrupt-on-Change flags in the IOCxF register
have been cleared by software.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared HS = Bit is set by hardware
I/O pins should not be floating The WDT is cleared when the device wakes up from
Sleep, regardless of the source of wake-up.
External circuitry sinking current from I/O pins
Internal circuitry sourcing current from I/O pins 9.1.1 WAKE-UP USING INTERRUPTS
Current draw from pins with internal weak pull-ups When global interrupts are disabled (GIE cleared) and
Modules using 31 kHz LFINTOSC any interrupt source has both its interrupt enable bit
Modules using Timer1 oscillator and interrupt flag bit set, one of the following will occur:
I/O pins that are high-impedance inputs should be If the interrupt occurs before the execution of a
pulled to VDD or VSS externally to avoid switching SLEEP instruction
currents caused by floating inputs. - SLEEP instruction will execute as a NOP.
Examples of internal circuitry that might be sourcing - WDT and WDT prescaler will not be cleared
current include modules such as the DAC and FVR - TO bit of the STATUS register will not be set
modules. See Section 17.0 Digital-to-Analog - PD bit of the STATUS register will not be
Converter (DAC) Module and Section 14.0 Fixed cleared.
Voltage Reference (FVR) for more information on
If the interrupt occurs during or after the execu-
these modules.
tion of a SLEEP instruction
- SLEEP instruction will be completely exe-
cuted
- Device will immediately wake-up from Sleep
- WDT and WDT prescaler will be cleared
- TO bit of the STATUS register will be set
- PD bit of the STATUS register will be cleared.
GIE bit
(INTCON reg.) Processor in
Sleep
Instruction Flow
PC PC PC + 1 PC + 2 PC + 2 PC + 2 0004h 0005h
Instruction Inst(PC + 1) Inst(PC + 2) Inst(0004h) Inst(0005h)
Fetched Inst(PC) = Sleep
Instruction Sleep Inst(PC + 1) Dummy Cycle Dummy Cycle
Executed Inst(PC - 1) Inst(0004h)
WDTE<1:0> = 01
SWDTEN
10.2 WDT Operating Modes The WDT is cleared when any of the following condi-
tions occur:
The Watchdog Timer module has four operating modes Any Reset
controlled by the WDTE<1:0> bits in Configuration
CLRWDT instruction is executed
Word 1. See Table 10-1.
Device enters Sleep
10.2.1 WDT IS ALWAYS ON Device wakes up from Sleep
When the WDTE bits of Configuration Word 1 are set to Oscillator fail event
11, the WDT is always on. WDT is disabled
WDT protection is active during Sleep. Oscillator Start-up TImer (OST) is running
See Table 10-2 for more information.
10.2.2 WDT IS OFF IN SLEEP
When the WDTE bits of Configuration Word 1 are set to 10.5 Operation During Sleep
10, the WDT is on, except in Sleep.
When the device enters Sleep, the WDT is cleared. If
WDT protection is not active during Sleep. the WDT is enabled during Sleep, the WDT resumes
counting.
10.2.3 WDT CONTROLLED BY SOFTWARE
When the device exits Sleep, the WDT is cleared
When the WDTE bits of Configuration Word 1 are set to
again. The WDT remains clear until the OST, if
01, the WDT is controlled by the SWDTEN bit of the
enabled, completes. See Section 5.0 Oscillator
WDTCON register.
Module (With Fail-Safe Clock Monitor) for more
WDT protection is unchanged by Sleep. See information on the OST.
Table 10-1 for more details.
When a WDT time-out occurs while the device is in
Sleep, no Reset is generated. Instead, the device
TABLE 10-1: WDT OPERATING MODES wakes up and resumes operation. The TO and PD bits
Device WDT in the STATUS register are changed to indicate the
WDTE<1:0> SWDTEN
Mode Mode event. See Section 3.0 Memory Organization for
more information.
11 X X Active
Awake Active
10 X
Sleep Disabled
1 Active
01 X
0 Disabled
00 X X Disabled
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -m/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
MOVLW 0AAh ;
MOVWF EECON2 ;Write AAh
BSF EECON1, WR ;Set WR bit to begin write
BSF INTCON, GIE ;Enable Interrupts
BCF EECON1, WREN ;Disable writes
BTFSC EECON1, WR ;Wait for write to complete
GOTO $-2 ;Done
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Flash Data INSTR (PC) INSTR (PC + 1) EEDATH,EEDATL INSTR (PC + 3) INSTR (PC + 4)
RD bit
EEDATH
EEDATL
Register
EERHLT
FIGURE 11-2: BLOCK WRITES TO FLASH PROGRAM MEMORY WITH 32 WRITE LATCHES
7 5 0 7 0
EEDATH EEDATA
6 8
14 14 14 14
Program Memory
MOVLW 0AAh ;
Required
START_WRITE
BCF EECON1,LWLO ; No more loading latches - Actually start Flash program
; memory write
MOVLW 0AAh ;
Required
TABLE 11-2: USER ID, DEVICE ID AND CONFIGURATION WORD ACCESS (CFGS = 1)
Address Function Read Access Write Access
8000h-8003h User IDs Yes Yes
8006h Device ID/Revision ID Yes No
8007h-8008h Configuration Words 1 and 2 Yes No
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
bit 7-0 EEDAT<7:0>: Read/write value for EEPROM data byte or Least Significant bits of program memory
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
bit 7-0 EEADR<7:0>: Specifies the Least Significant bits for program memory address or EEPROM address
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared HC = Bit is cleared by hardware
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
PORTC
; manner.
Device
BANKSEL PORTA ;
PIC16(L)F1825 CLRF PORTA ;Init PORTA
BANKSEL LATA ;Data Latch
PIC16(L)F1829 CLRF LATA ;
The Data Latch (LATx registers) is useful for BANKSEL ANSELA ;
read-modify-write operations on the value that the I/O CLRF ANSELA ;digital I/O
BANKSEL TRISA ;
pins are driving.
MOVLW B'00111000' ;Set RA<5:3> as inputs
A write operation to the LATx register has the same MOVWF TRISA ;and set RA<2:0> as
effect as a write to the corresponding PORTx register. ;outputs
A read of the LATx register reads of the values held in
the I/O PORT latches, while a read of the PORTx
register reads the actual I/O pin value.
Ports that support analog inputs have an associated
ANSELx register. When an ANSEL bit is set, the digital
input buffer associated with that bit is disabled.
Disabling the input buffer prevents analog signal levels
on the pin between a logic high and low from causing
excessive current in the logic input circuitry. A
simplified model of a generic I/O port, without the
interfaces to other peripherals, is shown in Figure 12-1.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return
of actual I/O pin values.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return
of actual I/O pin values.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Note 1: Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled.
2: The weak pull-up device is automatically disabled if the pin is in configured as an output.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Note 1: Writes to PORTB are actually written to corresponding LATB register. Reads from PORTB register is
return of actual I/O pin values.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
bit 7-4 ANSB<7:4>: Analog Select between Analog or Digital Function on pins RB<7:4>, respectively
0 = Digital I/O. Pin is assigned to port or digital special function.
1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
bit 3-0 Unimplemented: Read as 0
Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external
control of the voltage on the pin.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Note 1: Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled.
2: The weak pull-up device is automatically disabled if the pin is in configured as an output.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Note 1: RC<7:6> available on PIC16(L)F1829 only. Otherwise, they are unimplemented and read as 0.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Note 1: TRISC<7:6> available on PIC16(L)F1829 only. Otherwise, they are unimplemented and read as 0.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Note 1: Writes to PORTC are actually written to corresponding LATC register. Reads from PORTC register is
return of actual I/O pin values.
2: LATC<7:6> available on PIC16(L)F1829 only. Otherwise, they are unimplemented and read as 0.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
bit 7-6 ANSC<7:6>: Analog Select between Analog or Digital Function on pins RC<3:0>, respectively(2)
0 = Digital I/O. Pin is assigned to port or digital special function.
1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
bit 5-4 Unimplemented: Read as 0
bit 3-0 ANSC<3:0>: Analog Select between Analog or Digital Function on pins RC<3:0>, respectively
0 = Digital I/O. Pin is assigned to port or digital special function.
1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.
2: ANSELC<7:6> available on PIC16(L)F1829 only. Otherwise, they are unimplemented and read as 0.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Note 1: Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled.
2: The weak pull-up device is automatically disabled if the pin is in configured as an output.
3: WPUC<7:6> available on PIC16(L)F1829 only. Otherwise, they are unimplemented and read as 0.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Note 1: INLVLC<7:6> available on PIC16(L)F1829 only. Otherwise, they are unimplemented and read as 0.
IOCIE
IOCANx D Q IOCAFx
IOCAPx D Q
CK
Q2 Clock Cycle
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared HS - Bit is set in hardware
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared HS - Bit is set in hardware
ADC input channel The ADFVR<1:0> bits of the FVRCON register are
used to enable and configure the gain amplifier settings
ADC positive reference
for the reference supplied to the ADC module. Refer-
Comparator positive input ence Section 16.0 Analog-to-Digital Converter
Digital-to-Analog Converter (DAC) (ADC) Module for additional information.
Capacitive Sensing (CPS) module The CDAFVR<1:0> bits of the FVRCON register are
The FVR can be enabled by setting the FVREN bit of used to enable and configure the gain amplifier settings
the FVRCON register. for the reference supplied to the DAC, CPS and com-
parator module. Reference Section 17.0 Digital-to-
Analog Converter (DAC) Module and Section 19.0
Comparator Module for additional information.
ADFVR<1:0>
2
X1
X2 FVR BUFFER1
X4 (To ADC Module)
CDAFVR<1:0> 2
X1
X2 FVR BUFFER2
X4 (To Comparators, DAC, CPS)
+
FVREN
_ FVRRDY
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared q = Value depends on condition
TABLE 14-1: SUMMARY OF REGISTERS ASSOCIATED WITH THE FIXED VOLTAGE REFERENCE
Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on page
FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR1 CDAFVR0 ADFVR1 ADFVR0 146
Legend: Shaded cells are unused by the Fixed Voltage Reference module.
VREF- ADNREF = 1
ADNREF = 0
VSS
VDD
ADPREF = 00
ADPREF = 11
VREF+ ADPREF = 10
AN0 00000
AN1 00001
AN2 00010
AN3 00011
AN4 00100
AN5 00101
AN6 00110
AN7 00111
AN8(2) 01000 ADC
(2)
AN9 01001 10
GO/DONE
AN10(2) 01010
AN11(2) 01011 0 = Left Justify
ADFM
1 = Right Justify
ADON 16
CHS<4:0>
ADC
ADCS<2:0> 32 MHz 20 MHz 16 MHz 8 MHz 4 MHz 1 MHz
Clock Source
Fosc/2 000 62.5ns(2) 100 ns(2) 125 ns(2) 250 ns(2) 500 ns(2) 2.0 s
Fosc/4 100 125 ns (2)
200 ns (2)
250 ns (2)
500 ns (2)
1.0 s 4.0 s
Fosc/8 001 0.5 s(2) 400 ns(2) 0.5 s(2) 1.0 s 2.0 s 8.0 s(3)
Fosc/16 101 800 ns 800 ns 1.0 s 2.0 s 4.0 s 16.0 s(3)
Fosc/32 010 1.0 s 1.6 s 2.0 s 4.0 s 8.0 s (3)
32.0 s(3)
Fosc/64 110 2.0 s 3.2 s 4.0 s 8.0 s (3)
16.0 s (3)
64.0 s(3)
FRC x11 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4)
Legend: Shaded cells are outside of recommended range.
Note 1: The FRC source has a typical TAD time of 1.6 s for VDD.
2: These values violate the minimum required TAD time.
3: For faster conversion times, the selection of another clock source is recommended.
4: The ADC clock period (TAD) and total ADC conversion time can be minimized when the ADC clock is derived from the
system clock FOSC. However, the FRC clock source must be used when conversions are to be performed with the
device in Sleep mode.
TCY - TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11
b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
Conversion starts
Holding capacitor is disconnected from analog input (typically 100 ns)
Set GO bit
On the following cycle:
ADRESH:ADRESL is loaded, GO bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
ADRESH ADRESL
(ADFM = 0) MSB LSB
bit 7 bit 0 bit 7 bit 0
Note: A device Reset forces all registers to their Using the Special Event Trigger does not assure proper
Reset state. Thus, the ADC module is ADC timing. It is the users responsibility to ensure that
turned off and any pending conversion is the ADC timing requirements are met.
terminated. Refer to Section 24.0 Capture/Compare/PWM Mod-
ules for more information.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Note 1: When selecting the FVR or the VREF+ pin as the source of the positive reference, be aware that a
minimum voltage specification exists. See Section 30.0 Electrical Specifications for details.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
T ACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient
= T AMP + T C + T COFF
= 2s + T C + Temperature - 25C 0.05s/C
V AP P LI ED 1 -------------------------- = V CHOLD
1
;[1] VCHOLD charged to within 1/2 lsb
n+1
2 1
TC
----------
RC
V AP P LI ED 1 e = V CHOLD ;[2] VCHOLD charge response to VAPPLIED
Tc
---------
V AP P LI ED 1 e = V A PP LIE D 1 -------------------------- ;combining [1] and [2]
RC 1
n+1
2 1
T C = C HOLD R IC + R SS + R S ln(1/511)
= 10pF 1k + 7k + 10k ln(0.001957)
= 1.12 s
Therefore:
T A CQ = 2s + 1.12s + 50C- 25C 0.05 s/C
= 4.42s
Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.
2: The charge holding capacitor (CHOLD) is not discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin
leakage specification.
VDD
Analog Sampling
Input Switch
VT 0.6V
Rs pin RIC 1k SS Rss
VA CPIN I LEAKAGE(1)
VT 0.6V CHOLD = 10 pF
5 pF
VSS/VREF-
6V
5V RSS
Legend: CHOLD = Sample/Hold Capacitance VDD 4V
3V
CPIN = Input Capacitance 2V
I LEAKAGE = Leakage current at the pin due to
various junctions
5 6 7 8 9 10 11
RIC = Interconnect Resistance
Sampling Switch
RSS = Resistance of Sampling Switch (k)
SS = Sampling Switch
VT = Threshold Voltage
Full-Scale Range
3FFh
3FEh
3FDh
3FCh
ADC Output Code
3FBh
03h
02h
01h
00h
Analog Input Voltage
0.5 LSB 1.5 LSB
VREF- Zero-Scale
Transition Full-Scale
Transition VREF+
V OUT = V SOURCE +
V OUT = V SOURCE
FVR BUFFER2
VDD
VSOURCE+
DACR<4:0>
5
VREF+
R
R
DACPSS<1:0>
2
R
DACEN
DACLPS R
32-to-1 MUX
32
Steps DAC
(To Comparator, CPS and
ADC Modules)
R
R
DACOUT
R
DACOE
DACNSS
VREF- VSOURCE-
VSS
PIC MCU
DAC
R
Module
+
Voltage DACOUT Buffered DAC Output
Reference
Output
Impedance
Output Clamped to Positive Voltage Source Output Clamped to Negative Voltage Source
VSRC+ VSRC+
R R
DACR<4:0> = 11111
R R
DACEN = 0 DACEN = 0
DACLPS = 1 DAC Voltage Ladder DACLPS = 0 DAC Voltage Ladder
(see Figure 17-1) (see Figure 17-1)
R R
DACR<4:0> = 00000
VSRC- VSRC-
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Note 1: The output select bits are always right justified to ensure that any number of bits can be used without
affecting the register layout.
SRLEN
SRPS Pulse SRQEN
Gen(2)
SRI
SRSPE S Q
SRCLK
SRQ
SRSCKE
SYNCC2OUT(3, 4)
SRSC2E(4)
SYNCC1OUT(3)
SR
SRSC1E
Latch(1)
SRPR Pulse
Gen(2)
SRI
SRRPE R Q
SRCLK SRNQ
SRRCKE SRLEN
SYNCC2OUT(3, 4) SRNQEN
SRRC2E(4)
SYNCC1OUT(3)
SRRC1E
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared S = Bit is set only
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
det
C12IN0- 0 Set CxIF
C12IN1- 1
MUX Interrupt CxINTN
C12IN2- 2 (2) det
CXPOL
C12IN3- 3 CxVN
-
CXOUT To Data Bus
D Q
Cx(3) MCXOUT
+
CxVP
Q1 EN
CXIN+ 0
MUX CxHYS
DAC 1 (2) CxSP
To ECCP PWM Logic
FVR Buffer2 2
3
CXSYNC
VSS CxON CXOE
TRIS bit
CXOUT
CXPCH<1:0> 0
2
D Q 1
(from Timer1)
T1CLK To Timer1 or SR Latch
SYNCCXOUT
CPIN ILEAKAGE(1)
VA VT 0.6V
5 pF
Vss
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
FOSC/4
Data Bus
0
8
T0CKI 1
0 Sync
1 2 TCY TMR0
0
From CPSCLK
1 TMR0SE Set Flag bit TMR0IF
TMR0CS 8-bit on Overflow
Prescaler PSA
T0XCS
Overflow to Timer1
PS<2:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
000 1:2
001 1:4
010 1:8
011 1 : 16
100 1 : 32
101 1 : 64
110 1 : 128
111 1 : 256
T1GSS<1:0>
T1G 00 T1GSPM
The oscillator circuit is enabled by setting the Timer1 Gate can also be driven by multiple selectable
T1OSCEN bit of the T1CON register. The oscillator will sources.
continue to run during Sleep.
21.6.1 TIMER1 GATE ENABLE
Note: The oscillator requires a start-up and The Timer1 Gate Enable mode is enabled by setting
stabilization time before use. Thus, the TMR1GE bit of the T1GCON register. The polarity
T1OSCEN should be set and a suitable of the Timer1 Gate Enable mode is configured using
delay observed prior to using Timer1. A the T1GPOL bit of the T1GCON register.
suitable delay similar to the OST delay
can be implemented in software by When Timer1 Gate Enable mode is enabled, Timer1
clearing the TMR1IF bit then presetting will increment on the rising edge of the Timer1 clock
the TMR1H:TMR1L register pair to source. When Timer1 Gate Enable mode is disabled,
FC00h. The TMR1IF flag will be set when no incrementing will occur and Timer1 will hold the
1024 clock cycles have elapsed, thereby current count. See Figure 21-3 for timing details.
indicating that the oscillator is running and
reasonably stable. TABLE 21-3: TIMER1 GATE ENABLE
SELECTIONS
21.5 Timer1 Operation in T1CLK T1GPOL T1G Timer1 Operation
Asynchronous Counter Mode
0 0 Counts
If control bit T1SYNC of the T1CON register is set, the 0 1 Holds Count
external clock input is not synchronized. The timer
1 0 Holds Count
increments asynchronously to the internal phase
clocks. If the external clock source is selected then the 1 1 Counts
timer will continue to run during Sleep and can
generate an interrupt on overflow, which will wake-up
the processor. However, special precautions in
software are needed to read/write the timer (see
Section 21.5.1 Reading and Writing Timer1 in
Asynchronous Counter Mode).
Note: When switching from synchronous to
asynchronous operation, it is possible to
skip an increment. When switching from
asynchronous to synchronous operation,
it is possible to produce an additional
increment.
The output resulting from a Comparator 2 operation 21.6.5 TIMER1 GATE VALUE STATUS
can be selected as a source for Timer1 Gate Control.
When Timer1 Gate Value Status is utilized, it is possible
The Comparator 2 output (SYNCC2OUT) can be
to read the most current level of the gate control value.
synchronized to the Timer1 clock or left asynchronous.
The value is stored in the T1GVAL bit in the T1GCON
For more information see Section 19.4.1 Comparator
register. The T1GVAL bit is valid even when the Timer1
Output Synchronization.
Gate is not enabled (TMR1GE bit is cleared).
T1CKI = 1
when TMR1
Enabled
T1CKI = 0
when TMR1
Enabled
TMR1GE
T1GPOL
T1G_IN
T1CKI
T1GVAL
TMR1GE
T1GPOL
T1GTM
T1G_IN
T1CKI
T1GVAL
TMR1GE
T1GPOL
T1GSPM
Cleared by hardware on
T1GGO/ Set by software falling edge of T1GVAL
DONE
Counting enabled on
rising edge of T1G
T1G_IN
T1CKI
T1GVAL
Cleared by
TMR1GIF Cleared by software Set by hardware on software
falling edge of T1GVAL
TMR1GE
T1GPOL
T1GSPM
T1GTM
Cleared by hardware on
T1GGO/ Set by software falling edge of T1GVAL
DONE Counting enabled on
rising edge of T1G
T1G_IN
T1CKI
T1GVAL
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
TMR1CS<1:0> = 0X:
This bit is ignored.
bit 1 Unimplemented: Read as 0
bit 0 TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1
Clears Timer1 Gate flip-flop
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared HC = Bit is cleared by hardware
T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ T1GVAL T1GSS1 T1GSS0 196
DONE
Legend: = unimplemented location, read as 0. Shaded cells are not used by the Timer1 module.
* Page provides register information.
Sets Flag
TMRx
bit TMRxIF
Output
Prescaler Reset
FOSC/4 TMRx
1:1, 1:4, 1:16, 1:64
2 Postscaler
Comparator
EQ 1:1 to 1:16
TxCKPS<1:0>
PRx 4
TxOUTPS<3:0>
A 4-bit counter/prescaler on the clock input allows direct Timer2 can be optionally used as the shift clock source
input, divide-by-4 and divide-by-16 prescale options. for the MSSPx modules operating in SPI mode.
These options are selected by the prescaler control bits, Additional information is provided in Section 25.0
TxCKPS<1:0> of the TxCON register. The value of Master Synchronous Serial Port (MSSP1 and
TMRx is compared to that of the Period register, PRx, on MSSP2) Module.
each clock cycle. When the two values match, the
comparator generates a match signal as the timer 22.4 Timer2/4/6 Operation During Sleep
output. This signal also resets the value of TMRx to 00h
The Timer2/4/6 timers cannot be operated while the
on the next cycle and drives the output
processor is in Sleep mode. The contents of the TMRx
counter/postscaler (see Section 22.2 Timer2/4/6
and PRx registers will remain unchanged while the
Interrupt).
processor is in Sleep mode.
The TMRx and PRx registers are both directly readable
and writable. The TMRx register is cleared on any
device Reset, whereas the PRx register initializes to
FFh. Both the prescaler and postscaler counters are
cleared on the following events:
a write to the TMRx register
a write to the TxCON register
Power-on Reset (POR)
Brown-out Reset (BOR)
MCLR Reset
Watchdog Timer (WDT) Reset
Stack Overflow Reset
Stack Underflow Reset
RESET Instruction
Note: TMRx is not cleared when TxCON is
written.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
D
MDCL<3:0> SYNC
Q 1
VSS 0000
MDCIN1 0001
MDCIN2 0010
CLKR 0011 0
CCP1 0100
CCP2 0101 CARL MDCLSYNC
CCP3 0110
CCP4 0111
1000
Reserved
* MDCLPOL
No Channel
Selected *
1111
Modulator (MOD)
MDCHSYNC = 1
MDCLSYNC = 0
MDCHSYNC = 1
MDCLSYNC = 1
MDCHSYNC = 0
MDCLSYNC = 0
MDCHSYNC = 0
MDCLSYNC = 1
Modulator (MOD)
MDCHSYNC = 0
MDCLSYNC = 0
Modulator (MOD)
MDCHSYNC = 1
MDCLSYNC = 0
Modulator (MOD)
MDCHSYNC = 0
MDCLSYNC = 1
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Note 1: The modulated output frequency can be greater and asynchronous from the clock that updates this
register bit, the bit value may not be valid for higher speed modulator or carrier signals.
2: MDBIT must be selected as the modulation source in the MDSRC register for this operation.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Note 1: Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Note 1: Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Note 1: Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized.
TABLE 23-1: SUMMARY OF REGISTERS ASSOCIATED WITH DATA SIGNAL MODULATOR MODE
Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page
MDCARH MDCHODIS MDCHPOL MDCHSYNC MDCH<3:0> 210
MDCARL MDCLODIS MDCLPOL MDCLSYNC MDCL<3:0> 211
MDCON MDEN MDOE MDSLR MDOPOL MDOUT MDBIT 208
MDSRC MDMSODIS MDMS<3:0> 209
Legend: = unimplemented, read as 0. Shaded cells are not used in the Data Signal Modulator mode.
TMR1H TMR1L
CCPxM<3:0>
System Clock (FOSC)
PRx registers Figure 24-8 shows the pin assignments for various
Enhanced PWM modes.
TxCON registers
CCPRxL registers Note 1: The corresponding TRIS bit must be
CCPxCON registers cleared to enable the PWM output on the
CCPx pin.
The ECCP modules have the following additional PWM
registers which control Auto-shutdown, Auto-restart, 2: Clearing the CCPxCON register will
Dead-band Delay and PWM Steering modes: relinquish control of the CCPx pin.
FIGURE 24-5: EXAMPLE SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODE
DCxB<1:0> PxM<1:0> CCPxM<3:0>
Duty Cycle Registers
2 4
CCPRxL
CCPx/PxA CCPx/PxA
TRISx
CCPRxH (Slave)
PxB PxB
Output TRISx
Comparator R Q
Controller
PxC PxC
TMRx (1)
S TRISx
PxD PxD
Comparator
Clear Timer, TRISx
toggle PWM pin and
latch duty cycle
PRx PWMxCON
Note 1: The 8-bit timer TMRx register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler to create the 10-bit time
base.
PxA Active
PxD Modulated
PxA Inactive
PxD Inactive
Relationships:
Period = 4 * TOSC * (PRx + 1) * (TMRx Prescale Value)
Pulse Width = TOSC * (CCPRxL<7:0>:CCPxCON<5:4>) * (TMRx Prescale Value)
Delay = 4 * TOSC * (PWMxCON<6:0>)
Pulse PRx+1
PxM<1:0> Signal 0
Width
Period
PxA Modulated
Delay Delay
10 (Half-Bridge) PxB Modulated
PxA Active
PxD Modulated
PxA Inactive
PxD Inactive
Relationships:
Period = 4 * TOSC * (PRx + 1) * (TMRx Prescale Value)
Pulse Width = TOSC * (CCPRxL<7:0>:CCPxCON<5:4>) * (TMRx Prescale Value)
Delay = 4 * TOSC * (PWMxCON<6:0>)
FET
Driver +
PxA
-
Load
FET
Driver
+
PxB
-
V+
FET FET
Driver Driver
PxA
Load
FET FET
Driver Driver
PxB
FET QA QC FET
Driver Driver
PxA
Load
PxB
FET FET
Driver Driver
PxC
QB QD
V-
PxD
PxB(2)
PxC(2)
PxD(2)
(1) (1)
Reverse Mode
Period
Pulse Width
PxA(2)
PxB(2)
PxC(2)
PxD(2)
(1) (1)
Note 1: At this time, the TMRx register is equal to the PRx register.
2: Output signal is shown as active-high.
PxA (Active-High)
PxB (Active-High)
Pulse Width
PxC (Active-High)
(2)
PxD (Active-High)
Pulse Width
Note 1: The direction bit PxM1 of the CCPxCON register is written any time during the PWM cycle.
2: When changing directions, the PxA and PxC signals switch before the end of the current PWM cycle. The
modulated PxB and PxD signals are inactive at this time. The length of this time is four Timer counts.
PxA
PxB
PW
PxC
PxD PW
TON
External Switch C
TOFF
External Switch D
PWM Period
PWM Activity
Start of
PWM Period
Shutdown Event
CCPxASE bit
PWM
Shutdown Shutdown Resumes
Event Occurs Event Clears CCPxASE
Cleared by
Firmware
PWM Period
PWM Activity
Start of
PWM Period
Shutdown Event
CCPxASE bit
PWM
Shutdown Resumes
Event Occurs
Shutdown CCPxASE
Event Clears Cleared by
Hardware
FET
Driver +
PxA V
-
Load
FET
Driver
+
PxB V
-
V-
PORT Data
0
TRIS
STRxB
PORT Data 0
TRIS
STRxC
PxC pin
CCPxM1 1
PORT Data 0
TRIS
STRxD
PORT Data 0
TRIS
PWM Period
PWM
STRx
P1n = PWM
PWM
STRx
P1n = PWM
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Reset
1 = Bit is set 0 = Bit is cleared
1000 = Compare mode: initialize ECCPx pin low; set output on compare match (set CCPxIF)
1001 = Compare mode: initialize ECCPx pin high; clear output on compare match (set CCPxIF)
1010 = Compare mode: generate software interrupt only; ECCPx pin reverts to I/O state
1011 = Compare mode: Special Event Trigger (ECCPx resets Timer, sets CCPxIF bit, starts A/D conversion if A/
D module is enabled)(1)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Note 1: Bit resets to 0 with Two-Speed Start-up and LP, XT or HS selected as the Oscillator mode or Fail-Safe
mode is enabled.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Note 1: The PWM Steering mode is available only when the CCPxCON register bits CCPxM<3:2> = 11 and
PxM<1:0> = 00.
Data Bus
Read Write
SSPxBUF Reg
SDIx
SSPxSR Reg
SDOx bit 0 Shift
Clock
Edge
Select
SSPM<3:0>
4
( TMR22Output )
SCKx
Edge Prescaler TOSC
Select 4, 16, 64
Baud Rate
Generator
TRIS bit (SSPxADD)
Internal
data bus [SSPM 3:0]
Read Write
SSPxSR
Clock Cntl
MSb LSb
Receive Enable (RCEN)
Internal
Data Bus
Read Write
Shift
Clock
SSPxSR Reg
SDAx MSb LSb
SSPMSK Reg
SSPxADD Reg
SCKx SCKx
SPI Master
SDOx SDIx SPI Slave
SDIx SDOx #1
General I/O SSx
General I/O
General I/O SCKx
SDIx SPI Slave
SDOx #2
SSx
SCKx
SDIx SPI Slave
SDOx #3
SSx
Slave Select
General I/O SSx
Processor 1 (optional) Processor 2
Write to
SSPxBUF
SCKx
(CKP = 0
CKE = 0)
SCKx
(CKP = 1
CKE = 0)
4 Clock
SCKx Modes
(CKP = 0
CKE = 1)
SCKx
(CKP = 1
CKE = 1)
Input
Sample
(SMP = 1)
SSPxIF
SSPxSR to
SSPxBUF
SCK SCK
SPI Master
SDOx SDIx SPI Slave
SDIx SDOx #1
General I/O SSx
SCK
SDIx SPI Slave
SDOx #2
SSx
SCK
SDIx SPI Slave
SDOx #3
SSx
SSx
SCKx
(CKP = 0
CKE = 0)
SCKx
(CKP = 1
CKE = 0)
Write to
SSPxBUF
Shift register SSPxSR
and bit count are reset
SSPxBUF to
SSPxSR
SDIx bit 0
bit 7 bit 7
Input
Sample
SSPxIF
Interrupt
Flag
SSPxSR to
SSPxBUF
SSx
Optional
SCKx
(CKP = 0
CKE = 0)
SCKx
(CKP = 1
CKE = 0)
Write to
SSPxBUF
Valid
SDOx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
SDIx
bit 7 bit 0
Input
Sample
SSPxIF
Interrupt
Flag
SSPxSR to
SSPxBUF
Write Collision
detection active
SSx
Not Optional
SCKx
(CKP = 0
CKE = 1)
SCKx
(CKP = 1
CKE = 1)
Write to
SSPxBUF
Valid
SDOx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
SDIx
bit 7 bit 0
Input
Sample
SSPxIF
Interrupt
Flag
SSPxSR to
SSPxBUF
Write Collision
detection active
The I2C specification defines a Start condition as a A Restart is valid any time that a Stop would be valid.
transition of SDAx from a high to a low state while A master can issue a Restart if it wishes to hold the
SCLx line is high. A Start condition is always gener- bus after terminating the current transfer. A Restart
ated by the master and signifies the transition of the has the same effect on the slave that a Start would,
bus from an Idle to an Active state. Figure 25-10 resetting all slave logic and preparing it to clock in an
shows wave forms for Start and Stop conditions. address. The master may want to address the same or
A bus collision can occur on a Start condition if the another slave.
module samples the SDAx line low before asserting it In 10-bit Addressing Slave mode a Restart is required
low. This does not conform to the I2C Specification that for the master to clock data out of the addressed
states no bus collision can occur on a Start. slave. Once a slave has been fully addressed, match-
ing both high and low address bytes, the master can
25.4.6 STOP CONDITION issue a Restart and the high address byte with the
A Stop condition is a transition of the SDAx line from R/W bit set. The slave logic will then hold the clock
low-to-high state while the SCLx line is high. and prepare to clock out data.
After a full match with R/W clear in 10-bit mode, a prior
Note: At least one SCLx low time must appear
match flag is set and maintained. Until a Stop condi-
before a Stop is valid, therefore, if the SDAx
tion, a high address with R/W clear, or high address
line goes low then high again while the SCLx
match fails.
line stays high, only the Start condition is
detected. 25.4.8 START/STOP CONDITION INTERRUPT
MASKING
SDAx
SCLx
S P
Change of Change of
Data Allowed Data Allowed
Start Stop
Condition Condition
Sr
Change of Change of
Data Allowed Data Allowed
Restart
Condition
When the SEN bit of the SSPxCON2 register is set, 1. S bit of SSPxSTAT is set; SSPxIF is set if inter-
SCLx will be held low (clock stretch) following each rupt on Start detect is enabled.
received byte. The clock must be released by setting 2. Matching address with R/W bit clear is clocked
the CKP bit of the SSPxCON1 register, except in. SSPxIF is set and CKP cleared after the 8th
sometimes in 10-bit mode. See Section 25.2.3 SPI falling edge of SCLx.
Master Mode for more detail. 3. Slave clears the SSPxIF.
4. Slave can look at the ACKTIM bit of the
25.5.2.1 7-bit Addressing Reception
SSPxCON3 register to determine if the SSPxIF
This section describes a standard sequence of events was after or before the ACK.
for the MSSPx module configured as an I2C Slave in 5. Slave reads the address value from SSPxBUF,
7-bit Addressing mode. All decisions made by hard- clearing the BF flag.
ware or software and their effect on reception. 6. Slave sets ACK value clocked out to the master
Figure 25-13 and Figure 25-14 is used as a visual by setting ACKDT.
reference for this description.
7. Slave releases the clock by setting CKP.
This is a step by step process of what typically must 8. SSPxIF is set after an ACK, not after a NACK.
be done to accomplish I2C communication.
9. If SEN = 1 the slave hardware will stretch the
1. Start bit detected. clock after the ACK.
2. S bit of SSPxSTAT is set; SSPxIF is set if inter- 10. Slave clears SSPxIF.
rupt on Start detect is enabled.
Note: SSPxIF is still set after the 9th falling edge of
3. Matching address with R/W bit clear is received. SCLx even if there is no clock stretching and
4. The slave pulls SDAx low sending an ACK to the BF has been cleared. Only if NACK is sent
master, and sets SSPxIF bit. to Master is SSPxIF not set
5. Software clears the SSPxIF bit. 11. SSPxIF set and CKP cleared after 8th falling
6. Software reads received address from edge of SCLx for a received data byte.
SSPxBUF clearing the BF flag. 12. Slave looks at ACKTIM bit of SSPxCON3 to
7. If SEN = 1; Slave software sets CKP bit to determine the source of the interrupt.
release the SCLx line. 13. Slave reads the received data from SSPxBUF
8. The master clocks out a data byte. clearing BF.
9. Slave drives SDAx low sending an ACK to the 14. Steps 7-14 are the same for each received data
master, and sets SSPxIF bit. byte.
10. Software clears SSPxIF. 15. Communication is ended by either the slave
11. Software reads the received byte from sending an ACK = 1, or the master sending a
SSPxBUF clearing BF. Stop condition. If a Stop is sent and Interrupt on
12. Steps 8-12 are repeated for all received bytes Stop Detect is disabled, the slave will only know
from the Master. by polling the P bit of the SSTSTAT register.
13. Master sends Stop condition, setting P bit of
SSPxSTAT, and the bus goes Idle.
DS41440B-page 258
Bus Master sends
Stop condition
From Slave to Master
SCLx
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P
PIC16(L)F1825/1829
SSPxIF
SSPxIF set on 9th
Preliminary
Cleared by software Cleared by software falling edge of
SCLx
BF
First byte
SSPxBUF is read of data is
available
in SSPxBUF
SSPOV
SSPxIF
Preliminary
BF
First byte
of data is
SSPxBUF is read available
in SSPxBUF
SSPOV
DS41440B-page 259
Master Releases SDAx Master sends
to slave for ACK sequence Stop condition
FIGURE 25-16:
DS41440B-page 260
A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
SCLx
S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P
SSPxIF
If AHEN = 1: SSPxIF is set on
SSPxIF is set 9th falling edge of Cleared by software No interrupt
SCLx, after ACK after not ACK
BF from Slave
Address is
read from Data is read from SSPxBUF
PIC16(L)F1825/1829
ACKDT SSBUF
Slave software
clears ACKDT to Slave software
ACK the received sets ACKDT to
CKP byte not ACK
Preliminary
When AHEN=1:
When DHEN=1: CKP set by software,
CKP is cleared by hardware
CKP is cleared by SCLx is released
and SCLx is stretched hardware on 8th falling
edge of SCLx
ACKTIM
P
I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 1)
Stop condition
Master releases
R/W = 0 SDAx to slave for ACK sequence
Receiving Address Receive Data Receive Data ACK
SDAx ACK
A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0
SCLx
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P
SSPxIF
Cleared by software No interrupt after
if not ACK
from Slave
BF
Received
address is loaded into Received data is SSPxBUF can be
SSPxBUF available on SSPxBUF read any time before
next byte is loaded
ACKDT
Preliminary
ACKDT to ACK not ACK
the received byte
CKP
When AHEN = 1; When DHEN = 1; CKP is not cleared
on the 8th falling edge on the 8th falling edge Set by software, if not ACK
of SCLx of an address of SCLx of a received release SCLx
byte, CKP is cleared data byte, CKP is cleared
ACKTIM
P
I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 1, DHEN = 1)
PIC16(L)F1825/1829
DS41440B-page 261
PIC16(L)F1825/1829
25.5.3 SLAVE TRANSMISSION 25.5.3.2 7-bit Transmission
When the R/W bit of the incoming address byte is set A master device can transmit a read request to a
and an address match occurs, the R/W bit of the slave, and then clock data out of the slave. The list
SSPxSTAT register is set. The received address is below outlines what software for a slave will need to
loaded into the SSPxBUF register, and an ACK pulse is do to accomplish a standard transmission.
sent by the slave on the ninth bit. Figure 25-17 can be used as a reference to this list.
Following the ACK, slave hardware clears the CKP bit 1. Master sends a Start condition on SDAx and
and the SCLx pin is held low (see Section 25.5.6 SCLx.
Clock Stretching for more detail). By stretching the 2. S bit of SSPxSTAT is set; SSPxIF is set if inter-
clock, the master will be unable to assert another clock rupt on Start detect is enabled.
pulse until the slave is done preparing the transmit 3. Matching address with R/W bit set is received by
data. the Slave setting SSPxIF bit.
The transmit data must be loaded into the SSPxBUF 4. Slave hardware generates an ACK and sets
register which also loads the SSPxSR register. Then SSPxIF.
the SCLx pin should be released by setting the CKP bit 5. SSPxIF bit is cleared by user.
of the SSPxCON1 register. The eight data bits are
6. Software reads the received address from
shifted out on the falling edge of the SCLx input. This
SSPxBUF, clearing BF.
ensures that the SDAx signal is valid during the SCLx
high time. 7. R/W is set so CKP was automatically cleared
after the ACK.
The ACK pulse from the master-receiver is latched on
8. The slave software loads the transmit data into
the rising edge of the ninth SCLx input pulse. This ACK
SSPxBUF.
value is copied to the ACKSTAT bit of the SSPxCON2
register. If ACKSTAT is set (not ACK), then the data 9. CKP bit is set releasing SCLx, allowing the mas-
transfer is complete. In this case, when the not ACK is ter to clock the data out of the slave.
latched by the slave, the slave goes Idle and waits for 10. SSPxIF is set after the ACK response from the
another occurrence of the Start bit. If the SDAx line was master is loaded into the ACKSTAT register.
low (ACK), the next transmit data must be loaded into 11. SSPxIF bit is cleared.
the SSPxBUF register. Again, the SCLx pin must be 12. The slave software checks the ACKSTAT bit to
released by setting bit CKP. see if the master wants to clock out more data.
An MSSPx interrupt is generated for each data transfer Note 1: If the master ACKs the clock will be
byte. The SSPxIF bit must be cleared by software and stretched.
the SSPxSTAT register is used to determine the status
of the byte. The SSPxIF bit is set on the falling edge of 2: ACKSTAT is the only bit updated on the
the ninth clock pulse. rising edge of SCLx (9th) rather than the
falling.
25.5.3.1 Slave Mode Bus Collision 13. Steps 9-13 are repeated for each transmitted
A slave receives a Read request and begins shifting byte.
data out on the SDAx line. If a bus collision is detected 14. If the master sends a not ACK; the clock is not
and the SBCDE bit of the SSPxCON3 register is set, held, but SSPxIF is still set.
the BCLxIF bit of the PIRx register is set. Once a bus 15. The master sends a Restart condition or a Stop.
collision is detected, the slave goes Idle and waits to be 16. The slave is no longer addressed.
addressed again. User software can use the BCLxIF bit
to handle a slave bus collision.
SCLx
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P
SSPxIF
BF
BF is automatically
Received address Data to transmit is cleared after 8th falling
is read from SSPxBUF loaded into SSPxBUF edge of SCLx
CKP
When R/W is set CKP is not
SCLx is always held for not
held low after 9th SCLx Set by software ACK
falling edge
ACKSTAT
Preliminary
Masters not ACK
is copied to
ACKSTAT
R/W
R/W is copied from the
matching address byte
D/A
I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 0)
Indicates an address
has been received
P
PIC16(L)F1825/1829
DS41440B-page 263
PIC16(L)F1825/1829
25.5.3.3 7-bit Transmission with Address
Hold Enabled
Setting the AHEN bit of the SSPxCON3 register
enables additional clock stretching and interrupt gen-
eration after the 8th falling edge of a received match-
ing address. Once a matching address has been
clocked in, CKP is cleared and the SSPxIF interrupt is
set.
Figure 25-18 displays a standard waveform of a 7-bit
Address Slave Transmission with AHEN enabled.
1. Bus starts Idle.
2. Master sends Start condition; the S bit of
SSPxSTAT is set; SSPxIF is set if interrupt on
Start detect is enabled.
3. Master sends matching address with R/W bit
set. After the 8th falling edge of the SCLx line the
CKP bit is cleared and SSPxIF interrupt is
generated.
4. Slave software clears SSPxIF.
5. Slave software reads ACKTIM bit of SSPxCON3
register, and R/W and D/A of the SSPxSTAT
register to determine the source of the interrupt.
6. Slave reads the address value from the
SSPxBUF register clearing the BF bit.
7. Slave software decides from this information if it
wishes to ACK or not ACK and sets the ACKDT
bit of the SSPxCON2 register accordingly.
8. Slave sets the CKP bit releasing SCLx.
9. Master clocks in the ACK value from the slave.
10. Slave hardware automatically clears the CKP bit
and sets SSPxIF after the ACK if the R/W bit is
set.
11. Slave software clears SSPxIF.
12. Slave loads value to transmit to the master into
SSPxBUF setting the BF bit.
Note: SSPxBUF cannot be loaded until after the
ACK.
13. Slave sets CKP bit releasing the clock.
14. Master clocks out the data from the slave and
sends an ACK value on the 9th SCLx pulse.
15. Slave hardware copies the ACK value into the
ACKSTAT bit of the SSPxCON2 register.
16. Steps 10-15 are repeated for each byte transmit-
ted to the master from the slave.
17. If the master sends a not ACK the slave
releases the bus allowing the master to send a
Stop and end the communication.
Note: Master must send a not ACK on the last byte
to ensure that the slave releases the SCLx
line to receive a Stop.
SCLx
S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
P
BF BF is automatically
Received address Data to transmit is cleared after 8th falling
is read from SSPxBUF loaded into SSPxBUF edge of SCLx
ACKDT
Slave clears
ACKDT to ACK
address
Preliminary
ACKSTAT
Masters ACK
response is copied
to SSPxSTAT
CKP
When AHEN = 1; CKP not cleared
CKP is cleared by hardware When R/W = 1; Set by software, after not ACK
after receiving matching CKP is always releases SCLx
address. cleared after ACK
ACKTIM
I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 1)
R/W
D/A
PIC16(L)F1825/1829
DS41440B-page 265
PIC16(L)F1825/1829
25.5.4 SLAVE MODE 10-BIT ADDRESS 25.5.5 10-BIT ADDRESSING WITH ADDRESS OR
RECEPTION DATA HOLD
This section describes a standard sequence of events Reception using 10-bit addressing with AHEN or
for the MSSPx module configured as an I2C Slave in DHEN set is the same as with 7-bit modes. The only
10-bit Addressing mode. difference is the need to update the SSPxADD register
Figure 25-19 is used as a visual reference for this using the UA bit. All functionality, specifically when the
description. CKP bit is cleared and SCLx line is held low are the
same. Figure 25-20 can be used as a reference of a
This is a step by step process of what must be done by slave in 10-bit addressing with AHEN set.
slave software to accomplish I2C communication.
Figure 25-21 shows a standard waveform for a slave
1. Bus starts Idle. transmitter in 10-bit Addressing mode.
2. Master sends Start condition; S bit of SSPxSTAT
is set; SSPxIF is set if interrupt on Start detect is
enabled.
3. Master sends matching high address with the
R/W bit clear; UA bit of the SSPxSTAT register
is set.
4. Slave sends ACK and SSPxIF is set.
5. Software clears the SSPxIF bit.
6. Software reads received address from
SSPxBUF clearing the BF flag.
7. Slave loads low address into SSPxADD,
releasing SCLx.
8. Master sends matching low address byte to the
slave; UA bit is set.
Note: Updates to the SSPxADD register are not
allowed until after the ACK sequence.
Master sends
Stop condition
Receive First Address Byte Receive Second Address Byte Receive Data Receive Data
SDAx
1 1 1 1
0 A9 A8 ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK
SSPxIF
Set by hardware Cleared by software
on 9th falling edge
BF
Data is read
Preliminary
If address matches Receive address is
SSPxADD it is loaded into read from SSPxBUF from SSPxBUF
SSPxBUF
UA
When UA = 1; Software updates SSPxADD
SCLx is held low and releases SCLx
CKP
DS41440B-page 267
Receive First Address Byte R/W = 0 Receive Second Address Byte Receive Data Receive Data
FIGURE 25-21:
DS41440B-page 268
SCLx S 1 2 3 4 5 6 7 8 9 UA 1 2 3 4 5 6 7 8 9 UA 1 2 3 4 5 6 7 8 9 1 2
SSPxIF
Set by hardware Cleared by software Cleared by software
on 9th falling edge
PIC16(L)F1825/1829
BF
Preliminary
Slave software clears
ACKDT to ACK
the received byte
UA
Master sends
Master sends Stop condition
Restart event Master sends
not ACK
Receiving Address R/W = 0 Receiving Second Address Byte Receive First Address Byte Transmitting Data Byte ACK = 1
SDAx 1 1 1 1 0 A9 A8 ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK 1 1 1 1 0 A9 A8 ACK D7 D6 D5 D4 D3 D2 D1 D0
SSPxIF
BF
Preliminary
UA
High address is loaded
UA indicates SSPxADD After SSPxADD is back into SSPxADD
must be updated updated, UA is cleared
CKP and SCLx is released
Indicates an address
has been received
I2C SLAVE, 10-BIT ADDRESS, TRANSMISSION (SEN = 0, AHEN = 0, DHEN = 0)
PIC16(L)F1825/1829
DS41440B-page 269
PIC16(L)F1825/1829
25.5.6 CLOCK STRETCHING 25.5.6.2 10-bit Addressing Mode
Clock stretching occurs when a device on the bus In 10-bit Addressing mode, when the UA bit is set, the
holds the SCLx line low effectively pausing communi- clock is always stretched. This is the only time the
cation. The slave may stretch the clock to allow more SCLx is stretched without CKP being cleared. SCLx is
time to handle data or prepare a response for the mas- released immediately after a write to SSPxADD.
ter device. A master device is not concerned with
Note: Previous versions of the module did not
stretching as anytime it is active on the bus and not
stretch the clock if the second address byte
transferring data it is stretching. Any stretching done
did not match.
by a slave is invisible to the master software and han-
dled by the hardware that generates SCLx. 25.5.6.3 Byte NACKing
The CKP bit of the SSPxCON1 register is used to con-
trol stretching in software. Any time the CKP bit is When AHEN bit of SSPxCON3 is set; CKP is cleared
cleared, the module will wait for the SCLx line to go by hardware after the 8th falling edge of SCLx for a
low and then hold it. Setting CKP will release SCLx received matching address byte. When DHEN bit of
and allow more communication. SSPxCON3 is set; CKP is cleared after the 8th falling
edge of SCLx for received data.
25.5.6.1 Normal Clock Stretching Stretching after the 8th falling edge of SCLx allows the
Following an ACK if the R/W bit of SSPxSTAT is set, a slave to look at the received address or data and
read request, the slave hardware will clear CKP. This decide if it wants to ACK the received data.
allows the slave time to update SSPxBUF with data to 25.5.7 CLOCK SYNCHRONIZATION AND
transfer to the master. If the SEN bit of SSPxCON2 is THE CKP BIT
set, the slave hardware will always stretch the clock
after the ACK sequence. Once the slave is ready; CKP Any time the CKP bit is cleared, the module will wait
is set by software and communication resumes. for the SCLx line to go low and then hold it. However,
clearing the CKP bit will not assert the SCLx output
Note 1: The BF bit has no effect on if the clock will
low until the SCLx output is already sampled low.
be stretched or not. This is different than
Therefore, the CKP bit will not assert the SCLx line
previous versions of the module that
until an external I2C master device has already
would not stretch the clock, clear CKP, if
asserted the SCLx line. The SCLx output will remain
SSPxBUF was read before the 9th falling
low until the CKP bit is set and all other devices on the
edge of SCLx.
I2C bus have released SCLx. This ensures that a write
2: Previous versions of the module did not to the CKP bit will not violate the minimum high time
stretch the clock for a transmission if requirement for SCLx (see Figure 25-22).
SSPxBUF was loaded before the 9th fall-
ing edge of SCLx. It is now always cleared
for read requests.
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SDAx DX DX 1
SCLx
Master device
CKP asserts clock
Master device
releases clock
WR
SSPxCON1
SCLx
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S
SSPxIF
BF (SSPxSTAT<0>)
Cleared by software
SSPxBUF is read
GCEN (SSPxCON2<7>)
1
Master mode is enabled by setting and clearing the The master device generates all of the serial clock
appropriate SSPM bits in the SSPxCON1 register and pulses and the Start and Stop conditions. A transfer is
by setting the SSPEN bit. In Master mode, the SDAx ended with a Stop condition or with a Repeated Start
and SCKx pins must be configured as inputs. The condition. Since the Repeated Start condition is also
MSSP peripheral hardware will override the output the beginning of the next serial transfer, the I2C bus will
driver TRIS controls when necessary to drive the pins not be released.
low. In Master Transmitter mode, serial data is output
Master mode of operation is supported by interrupt through SDAx, while SCLx outputs the serial clock. The
generation on the detection of the Start and Stop con- first byte transmitted contains the slave address of the
ditions. The Stop (P) and Start (S) bits are cleared from receiving device (7 bits) and the Read/Write (R/W) bit.
a Reset or when the MSSPx module is disabled. Con- In this case, the R/W bit will be logic 0. Serial data is
trol of the I 2C bus may be taken when the P bit is set, transmitted 8 bits at a time. After each byte is transmit-
or the bus is Idle. ted, an Acknowledge bit is received. Start and Stop
conditions are output to indicate the beginning and the
In Firmware Controlled Master mode, user code end of a serial transfer.
conducts all I 2C bus operations based on Start and
Stop bit condition detection. Start and Stop condition In Master Receive mode, the first byte transmitted con-
detection is the only active circuitry in this mode. All tains the slave address of the transmitting device
other communication is done by the user software (7 bits) and the R/W bit. In this case, the R/W bit will be
directly manipulating the SDAx and SCLx lines. logic 1. Thus, the first byte transmitted is a 7-bit slave
address followed by a 1 to indicate the receive bit.
The following events will cause the SSPx Interrupt Flag Serial data is received via SDAx, while SCLx outputs
bit, SSPxIF, to be set (SSPx interrupt, if enabled): the serial clock. Serial data is received 8 bits at a time.
Start condition detected After each byte is received, an Acknowledge bit is
transmitted. Start and Stop conditions indicate the
Stop condition detected
beginning and end of transmission.
Data transfer byte transmitted/received
A Baud Rate Generator is used to set the clock fre-
Acknowledge transmitted/received
quency output on SCLx. See Section 25.7 Baud
Repeated Start generated Rate Generator for more detail.
Note 1: The MSSPx module, when configured in
I2C Master mode, does not allow queue-
ing of events. For instance, the user is not
allowed to initiate a Start condition and
immediately write the SSPxBUF register
to initiate transmission before the Start
condition is complete. In this case, the
SSPxBUF will not be written to and the
WCOL bit will be set, indicating that a
write to the SSPxBUF did not occur
2: When in Master mode, Start/Stop detec-
tion is masked and an interrupt is gener-
ated when the SEN/PEN bit is cleared and
the generation is complete.
SDAx DX DX 1
BRG decrements on
Q2 and Q4 cycles
BRG
03h 02h 01h 00h (hold off) 03h 02h
Value
TBRG
SCLx
S
TBRG
Preliminary
BF (SSPxSTAT<0>)
PEN
R/W
I2C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS)
PIC16(L)F1825/1829
DS41440B-page 277
PIC16(L)F1825/1829
25.6.7 I2C MASTER MODE RECEPTION 25.6.7.4 Typical Receive Sequence:
Master mode reception is enabled by programming the 1. The user generates a Start condition by setting
Receive Enable bit, RCEN bit of the SSPxCON2 the SEN bit of the SSPxCON2 register.
register. 2. SSPxIF is set by hardware on completion of the
Note: The MSSPx module must be in an Idle Start.
state before the RCEN bit is set or the 3. SSPxIF is cleared by software.
RCEN bit will be disregarded. 4. User writes SSPxBUF with the slave address to
The Baud Rate Generator begins counting and on each transmit and the R/W bit set.
rollover, the state of the SCLx pin changes 5. Address is shifted out the SDAx pin until all 8 bits
(high-to-low/low-to-high) and data is shifted into the are transmitted. Transmission begins as soon
SSPxSR. After the falling edge of the eighth clock, the as SSPxBUF is written to.
receive enable flag is automatically cleared, the con- 6. The MSSPx module shifts in the ACK bit from
tents of the SSPxSR are loaded into the SSPxBUF, the the slave device and writes its value into the
BF flag bit is set, the SSPxIF flag bit is set and the Baud ACKSTAT bit of the SSPxCON2 register.
Rate Generator is suspended from counting, holding 7. The MSSPx module generates an interrupt at
SCLx low. The MSSPx is now in Idle state awaiting the the end of the ninth clock cycle by setting the
next command. When the buffer is read by the CPU, SSPxIF bit.
the BF flag bit is automatically cleared. The user can 8. User sets the RCEN bit of the SSPxCON2 regis-
then send an Acknowledge bit at the end of reception ter and the Master clocks in a byte from the slave.
by setting the Acknowledge Sequence Enable, ACKEN
9. After the 8th falling edge of SCLx, SSPxIF and
bit of the SSPxCON2 register.
BF are set.
25.6.7.1 BF Status Flag 10. Master clears SSPxIF and reads the received
byte from SSPxUF, clears BF.
In receive operation, the BF bit is set when an address
or data byte is loaded into SSPxBUF from SSPxSR. It 11. Master sets ACK value sent to slave in ACKDT
is cleared when the SSPxBUF register is read. bit of the SSPxCON2 register and initiates the
ACK by setting the ACKEN bit.
25.6.7.2 SSPOV Status Flag 12. Masters ACK is clocked out to the slave and
In receive operation, the SSPOV bit is set when 8 bits SSPxIF is set.
are received into the SSPxSR and the BF flag bit is 13. User clears SSPxIF.
already set from a previous reception. 14. Steps 8-13 are repeated for each received byte
from the slave.
25.6.7.3 WCOL Status Flag 15. Master sends a not ACK or Stop to end
If the user writes the SSPxBUF when a receive is communication.
already in progress (i.e., SSPxSR is still shifting in a
data byte), the WCOL bit is set and the contents of the
buffer are unchanged (the write does not occur).
begin Start condition ACK from Master Set ACKEN, start Acknowledge sequence
Master configured as a receiver SDAx = ACKDT = 0 SDAx = ACKDT = 1
SEN = 0 by programming SSPxCON2<3> (RCEN = 1)
PEN bit = 1
Write to SSPxBUF occurs here, RCEN cleared RCEN = 1, start RCEN cleared
ACK from Slave next receive automatically written here
start XMIT automatically
Transmit Address to Slave Receiving Data from Slave Receiving Data from Slave
SDAx A7 A6 A5 A4 A3 A2 A1 R/W ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK
Set P bit
SDAx = 0, SCLx = 1 Cleared by software Cleared by software Cleared by software Cleared by software (SSPxSTAT<4>)
Cleared in
while CPU software and SSPxIF
responds to SSPxIF
BF
Preliminary
(SSPxSTAT<0>) Last bit is shifted into SSPxSR and
contents are unloaded into SSPxBUF
SSPOV
ACKEN
I2C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)
RCEN
Master configured as a receiver RCEN cleared ACK from Master RCEN cleared
by programming SSPxCON2<3> (RCEN = 1) automatically SDAx = ACKDT = 0 automatically
PIC16(L)F1825/1829
DS41440B-page 279
PIC16(L)F1825/1829
25.6.8 ACKNOWLEDGE SEQUENCE 25.6.9 STOP CONDITION TIMING
TIMING A Stop bit is asserted on the SDAx pin at the end of a
An Acknowledge sequence is enabled by setting the receive/transmit by setting the Stop Sequence Enable
Acknowledge Sequence Enable bit, ACKEN bit of the bit, PEN bit of the SSPxCON2 register. At the end of a
SSPxCON2 register. When this bit is set, the SCLx pin is receive/transmit, the SCLx line is held low after the
pulled low and the contents of the Acknowledge data bit falling edge of the ninth clock. When the PEN bit is set,
are presented on the SDAx pin. If the user wishes to the master will assert the SDAx line low. When the
generate an Acknowledge, then the ACKDT bit should SDAx line is sampled low, the Baud Rate Generator is
be cleared. If not, the user should set the ACKDT bit reloaded and counts down to 0. When the Baud Rate
before starting an Acknowledge sequence. The Baud Generator times out, the SCLx pin will be brought high
Rate Generator then counts for one rollover period and one TBRG (Baud Rate Generator rollover count)
(TBRG) and the SCLx pin is deasserted (pulled high). later, the SDAx pin will be deasserted. When the SDAx
When the SCLx pin is sampled high (clock arbitration), pin is sampled high while SCLx is high, the P bit of the
the Baud Rate Generator counts for TBRG. The SCLx pin SSPxSTAT register is set. A TBRG later, the PEN bit is
is then pulled low. Following this, the ACKEN bit is auto- cleared and the SSPxIF bit is set (Figure 25-30).
matically cleared, the Baud Rate Generator is turned off
and the MSSPx module then goes into Idle mode 25.6.9.1 WCOL Status Flag
(Figure 25-29). If the user writes the SSPxBUF when a Stop sequence
is in progress, then the WCOL bit is set and the
25.6.8.1 WCOL Status Flag contents of the buffer are unchanged (the write does
If the user writes the SSPxBUF when an Acknowledge not occur).
sequence is in progress, then the WCOL bit is set and
the contents of the buffer are unchanged (the write
does not occur).
SCLx 8 9
SSPxIF
Cleared in
SSPxIF set at software
the end of receive Cleared in
software SSPxIF set at the end
of Acknowledge sequence
Note: TBRG = one Baud Rate Generator period.
SDAx ACK
P
TBRG TBRG TBRG
SCLx brought high after TBRG
SDAx asserted low before rising edge of clock
to setup Stop condition
SDAx
BCLxIF
SDAx
SCLx
Set SEN, enable Start SEN cleared automatically because of bus collision.
condition if SDAx = 1, SCLx = 1 SSPx module reset into Idle state.
SEN
SDAx sampled low before
Start condition. Set BCLxIF.
S bit and SSPxIF set because
BCLxIF SDAx = 0, SCLx = 1.
SSPxIF and BCLxIF are
cleared by software
SSPxIF
TBRG TBRG
SDAx
SSPxIF 0 0
FIGURE 25-35: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION
SDAx = 0, SCLx = 1
Set S Set SSPxIF
Less than TBRG
TBRG
SCLx S
SCLx pulled low after BRG
time out
SEN
Set SEN, enable Start
sequence if SDAx = 1, SCLx = 1
BCLxIF 0
SSPxIF
SDAx = 0, SCLx = 1, Interrupts cleared
set SSPxIF by software
SDAx
SCLx
RSEN
BCLxIF
Cleared by software
S 0
SSPxIF 0
TBRG TBRG
SDAx
SCLx
S 0
SSPxIF
PEN
BCLxIF
P 0
SSPxIF 0
SDAx
PEN
BCLxIF
P 0
SSPxIF 0
SSPM<3:0> SSPxADD<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared HS = Bit is set by hardware C = User cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared HC = Cleared by hardware S = User set
bit 7 GCEN: General Call Enable bit (in I2C Slave mode only)
1 = Enable interrupt when a general call address (0x00 or 00h) is received in the SSPxSR
0 = General call address disabled
bit 6 ACKSTAT: Acknowledge Status bit (in I2C mode only)
1 = Acknowledge was not received
0 = Acknowledge was received
bit 5 ACKDT: Acknowledge Data bit (in I2C mode only)
In Receive mode:
Value transmitted when the user initiates an Acknowledge sequence at the end of a receive
1 = Not Acknowledge
0 = Acknowledge
bit 4 ACKEN: Acknowledge Sequence Enable bit (in I2C Master mode only)
In Master Receive mode:
1 = Initiate Acknowledge sequence on SDAx and SCLx pins, and transmit ACKDT data bit.
Automatically cleared by hardware.
0 = Acknowledge sequence Idle
bit 3 RCEN: Receive Enable bit (in I2C Master mode only)
1 = Enables Receive mode for I2C
0 = Receive Idle
bit 2 PEN: Stop Condition Enable bit (in I2C Master mode only)
SCKx Release Control:
1 = Initiate Stop condition on SDAx and SCLx pins. Automatically cleared by hardware.
0 = Stop condition Idle
bit 1 RSEN: Repeated Start Condition Enabled bit (in I2C Master mode only)
1 = Initiate Repeated Start condition on SDAx and SCLx pins. Automatically cleared by hardware.
0 = Repeated Start condition Idle
bit 0 SEN: Start Condition Enabled bit (in I2C Master mode only)
In Master mode:
1 = Initiate Start condition on SDAx and SCLx pins. Automatically cleared by hardware.
0 = Start condition Idle
In Slave mode:
1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)
0 = Clock stretching is disabled
Note 1: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode, this bit may not be
set (no spooling) and the SSPxBUF may not be written (or writes to the SSPxBUF are disabled).
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Note 1: For daisy-chained SPI operation; allows the user to ignore all but the last received byte. SSPOV is still set
when a new byte is received and BF = 1, but hardware continues to write the most recent byte to SSPxBUF.
2: This bit has no effect in Slave modes that Start and Stop condition detection is explicitly listed as enabled.
3: The ACKTIM Status bit is only active when the AHEN bit or DHEN bit is set.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
REGISTER 25-6: SSPxADD: MSSPx ADDRESS AND BAUD RATE REGISTER (I2C MODE)
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
ADD<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Master mode:
bit 7-3 Not used: Unused for Most Significant Address byte. Bit state of this register is a dont care. Bit
pattern sent by master is fixed by I2C specification and must be equal to 11110. However, those bits
are compared by hardware and are not affected by the value in this register.
bit 2-1 ADD<2:1>: Two Most Significant bits of 10-bit address
bit 0 Not used: Unused in this mode. Bit state is a dont care.
10-Bit Slave mode Least Significant Address byte:
TXEN
TRMT SPEN
Baud Rate Generator FOSC
n
TX9
BRG16 n
+1 Multiplier x4 x16 x64
TX9D
SYNC 1 X 0 0 0
SPBRGH SPBRGL BRGH X 1 1 0 0
BRG16 X 1 0 1 0
BRG16
+1 n
Multiplier x4 x16 x64
SYNC 1 X 0 0 0
SPBRGH SPBRGL BRGH FIFO
X 1 1 0 0 FERR RX9D RCREG Register
BRG16 X 1 0 1 0
8
Data Bus
RCIF Interrupt
RCIE
Write to TXREG
Word 1
BRG Output
(Shift Clock)
TX/CK
pin Start bit bit 0 bit 1 bit 7/8 Stop bit
Word 1
TXIF bit
(Transmit Buffer 1 TCY
Reg. Empty Flag)
Word 1
TRMT bit
Transmit Shift Reg.
(Transmit Shift
Reg. Empty Flag)
Write to TXREG
Word 1 Word 2
BRG Output
(Shift Clock)
TX/CK
pin Start bit bit 0 bit 1 bit 7/8 Stop bit Start bit bit 0
TXIF bit 1 TCY Word 1 Word 2
(Transmit Buffer
Reg. Empty Flag) 1 TCY
CREN = 1 Immediately after all data bits and the Stop bit have
been received, the character in the RSR is transferred
SYNC = 0
to the EUSART receive FIFO and the RCIF interrupt
SPEN = 1 flag bit of the PIR1 register is set. The top character in
All other EUSART control bits are assumed to be in the FIFO is transferred out of the FIFO by reading the
their default state. RCREG register.
Setting the CREN bit of the RCSTA register enables the Note: If the receive FIFO is overrun, no additional
receiver circuitry of the EUSART. Clearing the SYNC bit characters will be received until the overrun
of the TXSTA register configures the EUSART for condition is cleared. See Section 27.1.2.5
asynchronous operation. Setting the SPEN bit of the Receive Overrun Error for more
RCSTA register enables the EUSART. The programmer information on overrun errors.
must set the corresponding TRIS bit to configure the
RX/DT I/O pin as an input. 26.1.2.3 Receive Interrupts
Note 1: If the RX/DT function is on an analog pin, The RCIF interrupt flag bit of the PIR1 register is set
the corresponding ANSEL bit must be whenever the EUSART receiver is enabled and there is
cleared for the receiver to function. an unread character in the receive FIFO. The RCIF
interrupt flag bit is read-only, it cannot be set or cleared
by software.
RCIF interrupts are enabled by setting all of the
following bits:
RCIE interrupt enable bit of the PIE1 register
PEIE Peripheral Interrupt Enable bit of the
INTCON register
GIE Global Interrupt Enable bit of the INTCON
register
The RCIF interrupt flag bit will be set when there is an
unread character in the FIFO, regardless of the state of
interrupt enable bits.
Read Rcv
Buffer Reg.
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
TABLE 26-4: SUMMARY OF REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR
Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page
BAUDCON ABDOVF RCIDL SCKP BRG16 WUE ABDEN 306
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 305
SPBRGL BRG<7:0> 307*
SPBRGH BRG<15:8> 307*
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 304
Legend: = unimplemented location, read as 0. Shaded cells are not used for the Baud Rate Generator.
* Page provides register information.
BAUD FOSC = 32.000 MHz FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz
RATE SPBRG SPBRG SPBRG SPBRG
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300
1200
2400
9600 9615 0.16 207 9615 0.16 129 9600 0.00 119 9600 0.00 71
10417 10417 0.00 191 10417 0.00 119 10378 -0.37 110 10473 0.53 65
19.2k 19.23k 0.16 103 19.23k 0.16 64 19.20k 0.00 59 19.20k 0.00 35
57.6k 57.14k -0.79 34 56.82k -1.36 21 57.60k 0.00 19 57.60k 0.00 11
115.2k 117.64k 2.12 16 113.64k -1.36 10 115.2k 0.00 9 115.2k 0.00 5
BAUD FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz
RATE SPBRG SPBRG SPBRG SPBRG
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 300 0.16 207
1200 1202 0.16 207 1200 0.00 191 1202 0.16 51
2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25
9600 9615 0.16 51 9615 0.16 25 9600 0.00 23
10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5
19.2k 19231 0.16 25 19.23k 0.16 12 19.2k 0.00 11
57.6k 55556 -3.55 8 57.60k 0.00 3
115.2k 115.2k 0.00 1
BAUD FOSC = 32.000 MHz FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz
RATE SPBRG SPBRG SPBRG SPBRG
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 300.0 0.00 6666 300.0 -0.01 4166 300.0 0.00 3839 300.0 0.00 2303
1200 1200 -0.02 3332 1200 -0.03 1041 1200 0.00 959 1200 0.00 575
2400 2401 -0.04 832 2399 -0.03 520 2400 0.00 479 2400 0.00 287
9600 9615 0.16 207 9615 0.16 129 9600 0.00 119 9600 0.00 71
10417 10417 0.00 191 10417 0.00 119 10378 -0.37 110 10473 0.53 65
19.2k 19.23k 0.16 103 19.23k 0.16 64 19.20k 0.00 59 19.20k 0.00 35
57.6k 57.14k -0.79 34 56.818 -1.36 21 57.60k 0.00 19 57.60k 0.00 11
115.2k 117.6k 2.12 16 113.636 -1.36 10 115.2k 0.00 9 115.2k 0.00 5
BAUD FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz
RATE SPBRG SPBRG SPBRG SPBRG
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 299.9 -0.02 1666 300.1 0.04 832 300.0 0.00 767 300.5 0.16 207
1200 1199 -0.08 416 1202 0.16 207 1200 0.00 191 1202 0.16 51
2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25
9600 9615 0.16 51 9615 0.16 25 9600 0.00 23
10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5
19.2k 19.23k 0.16 25 19.23k 0.16 12 19.20k 0.00 11
57.6k 55556 -3.55 8 57.60k 0.00 3
115.2k 115.2k 0.00 1
BAUD FOSC = 32.000 MHz FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz
RATE SPBRG SPBRG SPBRG SPBRG
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 300.0 0.00 26666 300.0 0.00 16665 300.0 0.00 15359 300.0 0.00 9215
1200 1200 0.00 6666 1200 -0.01 4166 1200 0.00 3839 1200 0.00 2303
2400 2400 0.01 3332 2400 0.02 2082 2400 0.00 1919 2400 0.00 1151
9600 9604 0.04 832 9597 -0.03 520 9600 0.00 479 9600 0.00 287
10417 10417 0.00 767 10417 0.00 479 10425 0.08 441 10433 0.16 264
19.2k 19.18k -0.08 416 19.23k 0.16 259 19.20k 0.00 239 19.20k 0.00 143
57.6k 57.55k -0.08 138 57.47k -0.22 86 57.60k 0.00 79 57.60k 0.00 47
115.2k 115.9k 0.64 68 116.3k 0.94 42 115.2k 0.00 39 115.2k 0.00 23
BAUD FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz
RATE SPBRG SPBRG SPBRG SPBRG
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 300.0 0.00 6666 300.0 0.01 3332 300.0 0.00 3071 300.1 0.04 832
1200 1200 -0.02 1666 1200 0.04 832 1200 0.00 767 1202 0.16 207
2400 2401 0.04 832 2398 0.08 416 2400 0.00 383 2404 0.16 103
9600 9615 0.16 207 9615 0.16 103 9600 0.00 95 9615 0.16 25
10417 10417 0 191 10417 0.00 95 10473 0.53 87 10417 0.00 23
19.2k 19.23k 0.16 103 19.23k 0.16 51 19.20k 0.00 47 19.23k 0.16 12
57.6k 57.14k -0.79 34 58.82k 2.12 16 57.60k 0.00 15
115.2k 117.6k 2.12 16 111.1k -3.55 8 115.2k 0.00 7
BRG Clock
RCIDL
RCIF bit
(Interrupt)
Read
RCREG
Note 1: The ABD sequence requires the EUSART module to be configured in Asynchronous mode.
RCIF
Cleared due to User Read of RCREG
Note 1: The EUSART remains in Idle while the WUE bit is set.
Note 1: If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposc signal is
still active. This sequence should not depend on the presence of Q clocks.
2: The EUSART remains in Idle while the WUE bit is set.
Write to TXREG
Dummy Write
BRG Output
(Shift Clock)
TX/CK pin
(SCKP = 1)
Write to
TXREG Reg Write Word 1 Write Word 2
TXIF bit
(Interrupt Flag)
TRMT bit
1 1
TXEN bit
Note: Sync Master mode, SPBRGL = 0, continuous transmission of two 8-bit words.
TX/CK pin
Write to
TXREG reg
TXIF bit
TRMT bit
TXEN bit
RX/DT
pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7
TX/CK pin
(SCKP = 0)
TX/CK pin
(SCKP = 1)
Write to
bit SREN
SREN bit
CREN bit 0 0
RCIF bit
(Interrupt)
Read
RCREG
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
Upon waking from Sleep, the instruction following the 26.5.3 ALTERNATE PIN LOCATIONS
SLEEP instruction will be executed. If the GIE, Global
This module incorporates I/O pins that can be moved to
Interrupt Enable, bit of the INTCON register is also set,
other locations with the use of the alternate pin function
then the Interrupt Service Routine at address 004h will
registers, APFCON0 and APFCON1. To determine
be called.
which pins can be moved and what their default loca-
tions are upon a Reset, see Section 12.1 Alternate
Pin Function for more information.
Timer0 Module
Set
TMR0CS TMR0IF
T0XCS
FOSC/4 0
Overflow
T0CKI 0 TMR0
1
CPSCH<3:0> 1
Capacitive
Sensing Timer1 Module
CPS0 Oscillator
T1CS<1:0>
CPS1 CPSOSC
CPS2 FOSC
FOSC/4
CPS3 CPSCLK
0 Int.
CPS4 Ref- Ref. T1OSC/ TMR1H:TMR1L
EN
CPSOUT T1CKI
CPS5 1 DAC
CPS6 0 T1GSEL<1:0>
Ref+
CPS7 T1G
1 FVR
CPS8(1) Timer1 Gate
SYNCC1OUT Control Logic
CPS9(1)
CPS10(1) SYNCC2OUT
CPS11(1)
CPSRM
Note 1: Reference CPSCON1 register (Register 27-2) for channels implemented on each device.
2: If CPSON = 0, disabling capacitive sensing, no channel is selected.
Oscillator Module
VDD
(1)
(2)
+
-
S Q CPSCLK
CPSx
Internal
References
0 0
Ref- Ref+
1 DAC 1 FVR
CPSRM
Note 1: Module Enable and Power mode selections are not shown.
2: Comparators remain active in Noise Detection mode.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
RJ11-6PIN
R1
To MPLAB ICD 2 To Target Board
270 Ohm
LM431BCMX
2 A 1
K
3 A U1
6 A NC 4
7 A NC 5
VREF
8
R2 R3
10k 1% 24k 1%
Pin 1 Indicator
Pin Description*
1 1 = VPP/MCLR
2
2 = VDD Target
3
4 3 = VSS (ground)
5
6 4 = ICSPDAT
5 = ICSPCLK
6 = No Connect
External
Programming VDD Device to be
Signals Programmed
VDD VDD
VPP MCLR/VPP
VSS VSS
Data ICSPDAT
Clock ICSPCLK
* * *
To Normal Connections
OPCODE only
13 0
OPCODE
CONTROL OPERATIONS
BRA k Relative Branch 2 11 001k kkkk kkkk
BRW Relative Branch with W 2 00 0000 0000 1011
CALL k Call Subroutine 2 10 0kkk kkkk kkkk
CALLW Call Subroutine with W 2 00 0000 0000 1010
GOTO k Go to address 2 10 1kkk kkkk kkkk
RETFIE k Return from interrupt 2 00 0000 0000 1001
RETLW k Return with literal in W 2 11 0100 kkkk kkkk
RETURN Return from Subroutine 2 00 0000 0000 1000
INHERENT OPERATIONS
CLRWDT Clear Watchdog Timer 1 00 0000 0110 0100 TO, PD
NOP No Operation 1 00 0000 0000 0000
OPTION Load OPTION_REG register with W 1 00 0000 0110 0010
RESET Software device Reset 1 00 0000 0000 0001
SLEEP Go into Standby mode 1 00 0000 0110 0011 TO, PD
TRIS f Load TRIS register with W 1 00 0000 0110 0fff
C-COMPILER OPTIMIZED
ADDFSR n, k Add Literal k to FSRn 1 11 0001 0nkk kkkk
MOVIW n mm Move Indirect FSRn to W with pre/post inc/dec 1 00 0000 0001 0nmm Z 2, 3
modifier, mm
k[n] Move INDFn to W, Indexed Indirect. 1 11 1111 0nkk kkkk Z 2
MOVWI n mm Move W to Indirect FSRn with pre/post inc/dec 1 00 0000 0001 1nmm 2, 3
modifier, mm
k[n] Move W to INDFn, Indexed Indirect. 1 11 1111 1nkk kkkk 2
Note 1:If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require
one additional instruction cycle.
3: See Table in the MOVIW and MOVWI instruction descriptions.
C register f 0 Words: 1
Cycles: 1
Example: MOVF FSR, 0
After Instruction
LSRF Logical Right Shift
W = value in FSR register
Syntax: [ label ] LSLF f {,d} Z = 1
Operands: 0 f 127
d [0,1]
Operation: 0 dest<7>
(f<7:1>) dest<6:0>,
(f<0>) C,
Status Affected: C, Z
Description: The contents of register f are shifted
one bit to the right through the Carry
flag. A 0 is shifted into the MSb. If d is
0, the result is placed in W. If d is 1,
the result is stored back in register f.
0 register f C
Description: The W register is loaded with the eight Description: The contents of register f are rotated
bit literal k. The program counter is one bit to the left through the Carry
loaded from the top of the stack (the flag. If d is 0, the result is placed in
return address). This is a two-cycle the W register. If d is 1, the result is
instruction. stored back in register f.
Words: 1 C Register f
Cycles: 2
Words: 1
Example: CALL TABLE;W contains table
;offset value Cycles: 1
;W now has table value Example: RLF REG1,0
TABLE
Before Instruction
REG1 = 1110 0110
ADDWF PC ;W = offset
C = 0
RETLW k1 ;Begin table
After Instruction
RETLW k2 ;
REG1 = 1110 0110
W = 1100 1100
C = 1
RETLW kn ; End of table
Before Instruction
W = 0x07
After Instruction
W = value of k8
2.5
1.8
0 4 10 16 32
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: Refer to Table 30-1 for each Oscillator modes supported frequencies.
3.6
2.5
1.8
0 4 10 16 32
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: Refer to Table 30-1 for each Oscillator modes supported frequencies.
125
5%
85
3%
Temperature (C)
60
25 2%
0
-20 5%
-40
1.8 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
VDD
VPOR
VPORR
VSS
NPOR
POR REARM
VSS
TVLOW(2) TPOR(3)
21.7 45 50 A 5.0
D023 0.2 1.5 3.0 A 1.8 LPWDT Current (Note 1)
0.5 2.0 3.7 A 3.0
D023 18 32 36 A 1.8 LPWDT Current (Note 1)
20.9 42 48 A 3.0
22.1 45 52 A 5.0
D023A 12.6 22 25 A 1.8 FVR current (Note 1)
12.8 24 27 A 3.0
D023A 32.7 50 55 A 1.8 FVR current (Note 1)
39 60 65 A 3.0
69 100 110 mA 5.0
D024 7 14 16 A 3.0 BOR Current (Note 1)
D024 24 40 43 A 3.0 BOR Current (Note 1)
27 45 58 A 5.0
D025 1.1 4.5 5 A 1.8 T1OSC Current (Note 1)
1.3 5 5.5 A 3.0
D025 19 33 36 A 1.8 T1OSC Current (Note 1)
21.6 38 45 A 3.0
23 46 50 A 5.0
D026 0.05 1.5 3.0 A 1.8 A/D Current (Note 1, Note 3), no
0.07 2.0 3.5 A 3.0 conversion in progress
22 40 48 A 5.0
* These parameters are characterized but not tested.
Data in Typ column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is
enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Max
values should be used when calculating total current consumption.
2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
3: A/D oscillator source is FRC.
280 A 5.0
D027 2.3 5 6 A 1.8 Cap Sense Low Power
3.5 6 8 A 3.0 Oscillator mode (Note 1)
25 49 54 A 5.0
D027A 5 8 10 A 1.8 Cap Sense Medium Power
6.5 11 12 A 3.0 Oscillator mode (Note 1)
29 55 65 A 5.0
D027B 13 22 24 A 1.8 Cap Sense High Power
35 42 44 A 3.0 Oscillator mode (Note 1)
59 82 90 A 5.0
D028 68 16 17 A 1.8 Comparator Current, Low Power
7.3 18 19 A 3.0 mode, one comparator enabled
(Note 1)
D028 24 40 45 A 1.8 Comparator Current, Low Power
27 48 52 A 3.0 mode, one comparator enabled
(Note 1)
29 54 58 A 5.0
D028A 8 17 18 A 1.8 Comparator Current, Low Power
8.4 19 20 A 3.0 mode, two comparators enabled
(Note 1)
D028A 25 42 47 A 1.8 Comparator Current, Low Power
28 50 54 A 3.0 mode, two comparators enabled
(Note 1)
30 56 60 A 5.0
* These parameters are characterized but not tested.
Data in Typ column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is
enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Max
values should be used when calculating total current consumption.
2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
3: A/D oscillator source is FRC.
TH01 JA Thermal Resistance Junction to Ambient TBD C/W 8-pin PDIP package
TBD C/W 8-pin SOIC package
TBD C/W 8-pin DFN 3X3mm package
TBD C/W 14-pin PDIP package
TBD C/W 14-pin SOIC package
TBD C/W 14-pin TSSOP 4x4mm package
TBD C/W 16-pin QFN 4X4mm package
TH02 JC Thermal Resistance Junction to Case TBD C/W 8-pin PDIP package
TBD C/W 8-pin SOIC package
TBD C/W 8-pin DFN 3X3mm package
TBD C/W 14-pin PDIP package
TBD C/W 14-pin SOIC package
TBD C/W 14-pin TSSOP 4x4mm package
TBD C/W 16-pin QFN 4X4mm package
TH03 TJMAX Maximum Junction Temperature 150 C
TH04 PD Power Dissipation W PD = PINTERNAL + PI/O
TH05 PINTERNAL Internal Power Dissipation W PINTERNAL = IDD x VDD(1)
TH06 PI/O I/O Power Dissipation W PI/O = (IOL * VOL) + (IOH * (VDD - VOH))
TH07 PDER Derated Power W PDER = PDMAX (TJ - TA)/JA(2)
Legend: TBD = To Be Determined
Note 1: IDD is current to run the chip alone without driving any load on the output pins.
2: TA = Ambient Temperature
3: TJ = Junction Temperature
1. TppS2ppS
2. TppS
T
F Frequency T Time
Lowercase letters (pp) and their meanings:
pp
cc CCP1 osc OSC1
ck CLKOUT rd RD
cs CS rw RD or WR
di SDIx sc SCKx
do SDO ss SS
dt Data in t0 T0CKI
io I/O PORT t1 T1CKI
mc MCLR wr WR
Uppercase letters and their meanings:
S
F Fall P Period
H High R Rise
I Invalid (High-impedance) V Valid
L Low Z High-impedance
Pin CL
VSS
Q4 Q1 Q2 Q3 Q4 Q1
OSC1/CLKIN
OS02
OS04 OS04
OS03
OSC2/CLKOUT
(LP,XT,HS Modes)
OSC2/CLKOUT
(CLKOUT Mode)
OS01 FOSC External CLKIN Frequency(1) DC 0.5 MHz EC Oscillator mode (low)
DC 4 MHz EC Oscillator mode (medium)
DC 32 MHz EC Oscillator mode (high)
Oscillator Frequency(1) 32.768 kHz LP Oscillator mode
0.1 4 MHz XT Oscillator mode
1 4 MHz HS Oscillator mode, VDD 2.7V
1 20 MHz HS Oscillator mode, VDD > 2.7V
DC 4 MHz RC Oscillator mode
OS02 TOSC External CLKIN Period(1) 27 s LP Oscillator mode
250 ns XT Oscillator mode
50 ns HS Oscillator mode
31.25 ns EC Oscillator mode
Oscillator Period(1) 30.5 s LP Oscillator mode
250 10,000 ns XT Oscillator mode
50 1,000 ns HS Oscillator mode
250 ns RC Oscillator mode
OS03 TCY Instruction Cycle Time(1) 125 DC ns TCY = FOSC/4
OS04* TosH, External CLKIN High, 2 s LP oscillator
TosL External CLKIN Low 100 ns XT oscillator
20 ns HS oscillator
OS05* TosR, External CLKIN Rise, 0 ns LP oscillator
TosF External CLKIN Fall 0 ns XT oscillator
0 ns HS oscillator
* These parameters are characterized but not tested.
Data in Typ column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing code.
Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current con-
sumption. All devices are tested to operate at min values with an external clock applied to OSC1 pin. When an external
clock input is used, the max cycle time limit is DC (no clock) for all devices.
MFINTOSC
Wake-up from Sleep Start-up Time 20 30 s
*These parameters are characterized but not tested.
Data in Typ column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing
code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current
consumption. All devices are tested to operate at min values with an external clock applied to the OSC1 pin. When an
external clock input is used, the max cycle time limit is DC (no clock) for all devices.
2: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as
possible. 0.1 F and 0.01 F values in parallel are recommended.
3: By design.
FOSC
OS11 OS12
OS20
CLKOUT OS21
OS19 OS16 OS18
OS13 OS17
I/O pin
(Input)
OS15 OS14
I/O pin Old Value New Value
(Output)
OS18, OS19
FIGURE 30-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out 32
OSC
Start-Up Time
Internal Reset(1)
Watchdog Timer
Reset(1)
31
34
34
I/O pins
VDD
VBOR and VHYST
VBOR
37
Reset
33(1)
(due to BOR)
T0CKI
40 41
42
T1CKI
45 46
47 49
TMR0 or
TMR1
CC01 CC02
CC03
BSF ADCON0, GO
1 TCY
AD134 (TOSC/2(1))
AD131
Q4
AD130
A/D CLK
A/D Data 7 6 5 4 3 2 1 0
ADIF 1 TCY
GO DONE
Sampling Stopped
Sample AD132
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
BSF ADCON0, GO
AD134 (TOSC/2 + TCY(1)) 1 TCY
AD131
Q4
AD130
A/D CLK
A/D Data 7 6 5 4 3 2 1 0
ADIF 1 TCY
GO DONE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
Param
Sym. Characteristics Min. Typ. Max. Units Comments
No.
CM01 VIOFF Input Offset Voltage 7.5 60 mV
CM02 VICM Input Common Mode Voltage 0 VDD V
CM03 CMRR Common Mode Rejection Ratio 50 dB
CM04A Response Time Rising Edge 400 800 ns High Power Mode
(NOTE 1)
CM04B Response Time Falling Edge 200 400 ns High Power Mode
(NOTE 1)
TRESP
CM04C Response Time Rising Edge 1200 ns Low Power Mode
(NOTE 1)
CM04D Response Time Falling Edge 550 ns Low Power Mode
(NOTE 1)
CM04 TRESP Response Time 150 400 ns NOTE 1
CM05 TMC2OV Comparator Mode Change to 10 s
Output Valid*
CM06 CHYSTER Comparator Hysteresis 65 mV NOTE 2
* These parameters are characterized but not tested.
Note 1: Response time measured with one comparator input at VDD/2, while the other input transitions
from VSS to VDD.
2: Comparator Hysteresis is available when the CxHYS bit of the CMxCON0 register is enabled.
Param
Sym. Characteristics Min. Typ. Max. Units Comments
No.
DAC01* CLSB Step Size(2) VDD/32 V
DAC02* CACC Absolute Accuracy 1/2 LSb
DAC03* CR Unit Resistor Value (R) TBD
DAC04* CST Settling Time(1) 10 s
* These parameters are characterized but not tested.
Legend: TBD = To Be Determined
Note 1: Settling time measured while DACR<4:0> transitions from 0000 to 1111.
CK
US121 US121
DT
US120 US122
CK
US125
DT
US126
SSx
SP70
SCKx
(CKP = 0)
SP71 SP72
SP78 SP79
SCKx
(CKP = 1)
SP79 SP78
SP80
SP75, SP76
SP74
SP73
SSx
SP81
SCKx
(CKP = 0)
SP71 SP72
SP79
SP73
SCKx
(CKP = 1)
SP80
SP78
SP75, SP76
SP74
SSx
SP70
SCKx SP83
(CKP = 0)
SP71 SP72
SP78 SP79
SCKx
(CKP = 1)
SP79 SP78
SP80
SP74
SP73
SP82
SSx
SP70
SCKx SP83
(CKP = 0)
SP71 SP72
SCKx
(CKP = 1)
SP80
SP77
SP75, SP76
SDIx
MSb In bit 6 - - - -1 LSb In
SP74
SCLx
SP91 SP93
SP90 SP92
SDAx
Start Stop
Condition Condition
SCLx
SP90
SP106
SP107
SP91 SP92
SDAx
In
SP110
SP109
SP109
SDAx
Out
VCTH
VCTL
ISRC ISNK
Enabled Enabled
XXXXXXXXXXXXXX PIC16F1824-I/P
XXXXXXXXXXXXXX 11010017
YYWWNNN
XXXXXXXXXXX PIC16F1824
XXXXXXXXXXX -I/SL
YYWWNNN 1110017
XXXXXXXX 1824/ST
YYWW 1110
NNN 017
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
* Standard PICmicro device marking consists of Microchip part number, year code, week code and
traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check
with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP
price.
XXXXXX 16F1824
XXXXXXX -I/ML
XXXXXXX
YYWWNNN 1110017
XXXXXXXXXXXXXXXXX PIC16F1824-I/P
XXXXXXXXXXXXXXXXX 1110017
YYWWNNN
XXXXXXXXXXXXXX PICXXFXXXX-I
XXXXXXXXXXXXXX /SO
XXXXXXXXXXXXXX 1110017
YYWWNNN
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
* Standard PICmicro device marking consists of Microchip part number, year code, week code and
traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check
with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP
price.
XXXXXXXXXXX PICXXFXXXX
XXXXXXXXXXX -I/SS
YYWWNNN 1110017
XXXXXXX XXFXXX
XXXXXXX -I/ML
YYWWNNN 1110017
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
* Standard PICmicro device marking consists of Microchip part number, year code, week code and
traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check
with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP
price.
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K
N N
NOTE 1 L
TOP VIEW BOTTOM VIEW
A3 A1
3
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U
USART
Synchronous Master Mode
Requirements, Synchronous Receive .............. 374
Requirements, Synchronous Transmission ...... 374
Timing Diagram, Synchronous Receive ........... 374
Timing Diagram, Synchronous Transmission ... 374
V
VREF. SEE ADC Reference Voltage
W
Wake-up on Break ............................................................ 313
Wake-up Using Interrupts ................................................. 101
Watchdog Timer (WDT) ...................................................... 82
Associated Registers ................................................ 106
Configuration Word w/ Watchdog Timer ................... 106
Modes ....................................................................... 104
Specifications............................................................ 369
WCOL ....................................................... 273, 276, 278, 280
WCOL Status Flag .................................... 273, 276, 278, 280
WDTCON Register ........................................................... 105
WPUA Register ................................................................. 129
WPUB Register ................................................................. 134
WPUC Register................................................................. 139
Write Protection .................................................................. 55
WWW Address.................................................................. 415
WWW, On-Line Support ..................................................... 12
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