Anil Appala

E-mail: anilsanju2389@gmail.com
Contact: +91-7382327833

Objective:

To pursue a challenging career as an IC Design Engineer utilizing my experience of deep-submicron

tape-out in future endeavours of IC Design.

Profile:
2 years 7 months of service as Analog Layout Engineer, working with Incise Infotech Pvt Ltd.
Involved in the design of blocks like Band-gap reference, Low-dropout regulator, V/I bias generators,
Current mirrors, RF based Charge pump and limiter, Amplifiers, Digital VCO and Standard cells at
various technology nodes (28/65/90/180nm).

Technical Skill-Set:

Layout Tool : Cadence (IC-615) Virtuoso Layout Editor (L/XL).

LVS/DRC Tool : Calibre/Assura (DRC/LVS/PEX/ERC).
Technology Nodes : 28nm UMC, 65nm, 90nm &180 nm with TSMC foundry.
Simulation Tools : Cadence Spectre, LT-Spice.
Programming Language : Familiar with Perl.

Professional Experience:

Currently 1 year 4 months of service as Analog Layout Engineer with Incise Infotech Pvt
Ltd.
1 year 3 months service as Custom IC Layout Engineer in IIT- Hyderabad R&D Center.
Silicon Success Tape-Out of RF-Analog Front End IC with TSMC foundry (IITH R&D).
Comprehensive experience in developing an Area and Route optimized layout design.
Expert in Layout Physical Verification.
Hands-On experience in layout techniques like Half-Cell, Matching, Guard Rings
Shielding, Unit cell, Dummies, PAD ring, Capacitor and Resistor arrays.
Good fundamental understanding of CMOS basics, Basic Circuit Analysis, Layout
Concepts and Methods, Fabrication Process.
Good knowledge and protection awareness in layout from Latch-up mechanism, Electro
migration and Antenna effects.
Familiar with complete ASIC design flow (RTL to GDSII).
Industry Projects:
1. G5U28M Processor in UMC Foundry (28nm):
Client: Microsemi India Pvt Ltd.
Description and Responsibilities:
Major work engaged in Analog and Mixed-signal blocks layout implementation.
Analog block layout circuits includes like V/I bias generator& amplifier, power supply
nmos/pmos current mirrors, band-gap reference, top level integration and routing for
current generating band-gap calibrators and DAC modules.
General purpose IO block layouts includes like control data multiplexers and level
shifters, transmission gates, low voltage customized gate cells integration and power
ratio receivers for different voltage modes (1.8/2.5/3.3v).
Challenging tasks includes like EM based signal routing, efficient floorplan, symmetry
and shielding throughout critical node signals and proper surrounded double guard rings
for thick-gate devices, resistor and mosfet capacitor arrays.
Taken care of WPE effects, diffusion continuity and tight dispersion with enough
dummies, proper tie down to avoid Latch-up in crucial circuits.
Physical verification to check DRC, LVS issues.

2. IC Tape-Out for UHF-RF Energy Harvesting Front End (180nm):

Client: DRDO/ AMS R&D.

Description and Responsibilities:
Circuit simulations and Full-chip layout integration of RF-energy extraction system to
generate 1.1 volt constant DC at load from Analog Front End (AFE).
Block level layouts of Op-Amp, BGR, Charge pump, LDO, POR, RF limiter circuits.
Efficient floor-planning and placement of individual block layouts for Full-chip
integration to meet chip dimensions.
Ensure proper shielding and No-fill CAD layer insertion of signal nets since source is of
UHF (925 MHz and 2.4 GHz).
Performance track of chip with post layout simulations at all process corners (PVT).
Taken care of things like Area estimation, Device matching, RC delay, Signal coupling,
Parasitics, Noise coupling, Guarding, EM and Latch-up in all individual Blocks.
Proper implementation of Resistor, Decoupling mosfet capacitor & Capacitor layouts.
IC physical verification to check DRC, LVS, ERC, PEX, Antenna and Density issues.
3. Band Gap Reference (BGR) (28nm):
Description and Responsibilities:
Worked on layout design of Sub-threshold and BJT based Band-Gap Reference.
Place the Current mirrors, Comparator, BJT network in closer proximity.
General efforts include like Area estimation, floor-planning, Matching, Shielding, Metal
Stacking, Symmetry, Optimized routing in sub-blocks integration.
Route using Multi stack wide-metals between the BJT network, Current mirrors, and
Resistor divider as parasitic resistance is crucial compared to parasitic capacitance.
Taken care of Op-Amp RC matching, current mirror current matching, Common centroid
for BJT structure and interdigitated Resistor dividers with surrounded substrate isolation.
Physical Verification using Calibre (DRC/LVS/PEX/ERC).

4. Low-Dropout Voltage Regulator (LDO) (65nm).

Description and Responsibilities:
Worked on layout design of sub-blocks like Error-amplifier, Power FET, Resistor divider
circuits.
Proper choice of fingers to share uniform current throughout in PFET construction.
General efforts includes like Area estimation, floor-planning, Shielding, Isolation, Metal
Stacking, Matching, Dummies, Symmetry, Optimized sub-blocks integration routing.
Resistor divider is laid-out by surrounding Guard-rings to avoid substrate noise coupling.
Physical Verification using Calibre (DRC/LVS/PEX/ERC).

5. Operational Amplifiers (65nm):

Description and Responsibilities:
Worked on layout design of Single and Differential ended amplifiers.
Centroid matching for current mirror and cross-quad for input Pairs.
Used the concepts of Unit cell, Half-cell, Device orientation along with Dummies to
provide RC matching and symmetry.
Proper floor-plan for Area estimation and routing strategy to minimize parasitics.
Physical Verification using Calibre (DRC/LVS/PEX/ERC).

6. Digital - Clock Controller and VCO Blocks (65nm):

Description and Responsibilities:
Worked on layout design of Clocks Generator block and Digital Voltage Controlled
Oscillator.
Floor-plan is crucial in Clock Controller as it involves highly complex routing between
closely communicating various Standard cells and MOS switches.
Analyzing and optimizing the parasitics & routing delays in Clock Controller through
proper metal and via options.
 Signal flow, Symmetry and Shielding/Guarding plays vital in construction of VCO so as to
avoid clock jitter and noise.
Bias circuit in VCO needs an Analog Guard ring to isolate the external Digital noisy
signal.
Physical Verification using Calibre (DRC/LVS/PEX/ERC).

Training/Academic Projects:
1. Layout Design and Characterization of Standard Cells (90/180 nm):
Description and Responsibilities:
Layout design of standard cells like D-flop, NAND, NOR, XOR, Buffers, Inverters with
different drive strengths.
Achieving highly Area optimized cell layout using minimized routing between layers.
Strictly adhering to PR-boundaries for proper implementation by Place and Route Tool.
Choose proper power planning, metal resource utilization and Grid intersection Pin
placement.
Physical Verification using Calibre (DRC/LVS/ERC/PEX).
Generating the Spice extraction data to verify the functionality.
Simple characterization of standard cells using predefined scripts to check power
consumption and propagation delays.

2. Synthesis, Place and Route of Orcha Chip using Synopsys Tools:

Description and Responsibilities:
Basic understanding of the complete physical design flow from RTL to GDS II.
Simple Predefined TCL script based Physical Design implementation.
Basic synthesis of RTL code using DC-Shell compiler to generate Gate level net-list.
Observing and analyzing the cells and routing procedure through Place and Route option.
Basic static timing analysis for Set-up and Hold time calculations using Prime-Time tool.

Publications and Recognition:

Have an accepted conference paper Efficient Dual Band RF Energy Harvesting Front End
for Ultra Low Power Sensitive Passive Wearable Devices in IEEE International
Conference of 5th ISED, 2014 held at NIT- Surathkal.
Participated in National Level Children Science Congress held at IISC, Bangalore in
2006.
Gold medal and Merit Scholarship Certificate awardee for excellence in X-CBSE Board.
Best Exhibit awardee in Physics Regional Level Meet held in 2006.
Education Summary:

Education University/Institute Year Percentage

Training/PG-Diploma in RV-VLSI Design Center,
2013 Certification
ASIC VLSI Design Bangalore
Bachelor of Engineering JNTU, Hyderabad 2012 77.0

XII JNV(CBSE) 2007 76.0

X JNV(CBSE) 2005 90.0

Personal Profile:
Name : Anil Appala
Address : S/O Komuraiah,10-50,Cheemalakuntapally,Karimnagar,Telangana
Gender : Male
Languages : English, Telugu, Hindi

Declaration:
I hereby declare the above mentioned information is correct up to my knowledge and I bear the
responsibility for the correctness of above mentioned Particulars.

Place: Hyderabad Anil Appala