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E-mail: anilsanju2389@gmail.com
Contact: +91-7382327833
Objective:
Profile:
2 years 7 months of service as Analog Layout Engineer, working with Incise Infotech Pvt Ltd.
Involved in the design of blocks like Band-gap reference, Low-dropout regulator, V/I bias generators,
Current mirrors, RF based Charge pump and limiter, Amplifiers, Digital VCO and Standard cells at
various technology nodes (28/65/90/180nm).
Technical Skill-Set:
Professional Experience:
Currently 1 year 4 months of service as Analog Layout Engineer with Incise Infotech Pvt
Ltd.
1 year 3 months service as Custom IC Layout Engineer in IIT- Hyderabad R&D Center.
Silicon Success Tape-Out of RF-Analog Front End IC with TSMC foundry (IITH R&D).
Comprehensive experience in developing an Area and Route optimized layout design.
Expert in Layout Physical Verification.
Hands-On experience in layout techniques like Half-Cell, Matching, Guard Rings
Shielding, Unit cell, Dummies, PAD ring, Capacitor and Resistor arrays.
Good fundamental understanding of CMOS basics, Basic Circuit Analysis, Layout
Concepts and Methods, Fabrication Process.
Good knowledge and protection awareness in layout from Latch-up mechanism, Electro
migration and Antenna effects.
Familiar with complete ASIC design flow (RTL to GDSII).
Industry Projects:
1. G5U28M Processor in UMC Foundry (28nm):
Client: Microsemi India Pvt Ltd.
Description and Responsibilities:
Major work engaged in Analog and Mixed-signal blocks layout implementation.
Analog block layout circuits includes like V/I bias generator& amplifier, power supply
nmos/pmos current mirrors, band-gap reference, top level integration and routing for
current generating band-gap calibrators and DAC modules.
General purpose IO block layouts includes like control data multiplexers and level
shifters, transmission gates, low voltage customized gate cells integration and power
ratio receivers for different voltage modes (1.8/2.5/3.3v).
Challenging tasks includes like EM based signal routing, efficient floorplan, symmetry
and shielding throughout critical node signals and proper surrounded double guard rings
for thick-gate devices, resistor and mosfet capacitor arrays.
Taken care of WPE effects, diffusion continuity and tight dispersion with enough
dummies, proper tie down to avoid Latch-up in crucial circuits.
Physical verification to check DRC, LVS issues.
Training/Academic Projects:
1. Layout Design and Characterization of Standard Cells (90/180 nm):
Description and Responsibilities:
Layout design of standard cells like D-flop, NAND, NOR, XOR, Buffers, Inverters with
different drive strengths.
Achieving highly Area optimized cell layout using minimized routing between layers.
Strictly adhering to PR-boundaries for proper implementation by Place and Route Tool.
Choose proper power planning, metal resource utilization and Grid intersection Pin
placement.
Physical Verification using Calibre (DRC/LVS/ERC/PEX).
Generating the Spice extraction data to verify the functionality.
Simple characterization of standard cells using predefined scripts to check power
consumption and propagation delays.
Personal Profile:
Name : Anil Appala
Address : S/O Komuraiah,10-50,Cheemalakuntapally,Karimnagar,Telangana
Gender : Male
Languages : English, Telugu, Hindi
Declaration:
I hereby declare the above mentioned information is correct up to my knowledge and I bear the
responsibility for the correctness of above mentioned Particulars.