Subhash Patel

Personal Data
Address A-2, Aarti So.
Payalnagar Road, Naroda, 382330-Ahmedabad
Email subhashpatel9@googlemail.com, subhash.bvm@gmail.com
Phone 0091 9408590009

Education
February 2010 Master of Science in Microelectronics & Microsystems
Hamburg University of Technology (TUHH), Hamburg, Germany
Grade 1.4 (Very good) | Major: Microelectronics | Detailed List of Exams

June 2006 Bachelor of Engineering Electronics

Sardar Patel University, Vallabhvidyanagar, India
Result 81.79% (First class with distinction) | Detailed List of Exams

Work Experience
April-2009 to Internship and Thesis at IPGEN Rechte GmbH, Bochum, Germany
February 2010 Field :- Analog and Mixed signal integrated circuit design
Designed IP of CDR-PLL and Synthesizer PLL (Design, simulation, layout & verification)
Optimized area of Resistive DAC
Designed Analog multiplexer

July-2006 to Engineer at Bombardier Transportation, India

July-2007 Field :- Electronics testing and design
Developed Train control and Management System for Indian Railways Locomotive
Involved in testing of traction converter control electronics

Expertise
• Experience in Verilog RTL coding, synthesis and simulation
• Experience in CMOS analog and mixed signal circuit design (ASIC) with Cadence DFII and Mentor
Graphics IC design environment
• Knowledge of RTL coding, simulation and synthesis using XILINX ISE
• Knowledge of Digital signal processing (DSP), semiconductor device physics, USB protocol

Master of Science Dissertation (Thesis)

February 2010 A Test-bench driven, automated design approach for high performance PLL for
serial communication application
Advisors : Prof. Dr-Ing W Krautschneider (Hamburg University of Technology, Germany)
Dipl-Ing. Reimund Wittmann (IPGEN Rechte GmbH, Bochum, Germany)
Designed and implemented CDR-PLL and Synthesizer PLL in 180nm CMOS Technology
Developed and verified time efficient automated design approach for both PLLs
Developed configurable IP of both PLLs
Designed technology independent and configurable layouts of PLL
EDA tool used : Mentor Graphics, Eldo simulator, 1STONE design management tool, MATLAB
Computer Skills
Programming C, C++ ,Verilog, VHDL, AMPLE, MATLAB-script, JAVA(learning)
Operating systems Windows XP & Vista, Linux (Ubuntu and Mandriva)
EDA tools Cadence IC DFII, Mentor Graphics, MATLAB, Electric, Hspice, ELDO,
Xilinx ISE

Academic Projects
January 2009 Digital control for DC-offset suppression with D/A Converter in biomedical ASIC
Advisor : Dr-Ing D. Schröder (Hamburg University of Technology, Germany)
System level design in MATLAB and RTL implementation using Verilog-HDL coding
Synthesis and verification of design using Cadence IC DFII, Technology CMOS 350nm
Summer 2009 RTL design using Verilog-HDL of Currency coveter ASIC
Summer 2009 Design and simulation of acceleration sensor.
Summer 2009 Fabrication of Integrated Optical Fiber and diodes
Winter 2008 Design, simulation and implementation of Two stage Op-amp in 350nm CMOS technology
winter 2005 Sun-tracker

Scholarships, Certificates and Awards

April 2008 Scholarship for the students with an excellent academic performance at TUHH
December 2006 Gold medal from Sardar Patel university and BVM Engineering college
for securing highest rank at end of Bachelor study in Electronics branch
2002-2006 5 Gold/Silver Medals for excellent academic performance during Bachelor study
2006 GATE Examination : 88 percentile

Languages
Gujarati Mother tongue
English Fluent
Hindi Fluent
German Basic Knowledge, Learning intermediate German

Subhash Patel
June 26, 2010
Master of Science in Microelectronics & Microsystems
Hamburg University of Technology (TUHH), Hamburg, Germany
Grades
Exam Grade ECTS
Electronics Devices 1.3 3
Submicron Devices 1.0 3
Circuit Design 1.3 4.5
Laboratory : Circuit Design -analog- 1.7 2.5
Microelectronics Materials 1.3 3
2-D Microelectronic Systems 1.3 3
Optoelectronic II 1.0 3
Laboratory : Circuit Design -digital- 1.7 2.5
Microsystem Technologies 1.3 3
Microsystem Engineering 2.7 3
Laboratory : Microsystem Design 1.7 3.75
Laboratory : Semiconductor & Microsystem Technologies 1.7 3.75
Fiber & Integrated Optics 1.7 3
Digital Filter 2.3 3
Mobile Communication 2.3 4.5
Communication Network I 2.0 4.5
Digital Video Signal Coding 1.3 3
Digital Audio Signal Processing 1.7 4.5

International Business Management 4.0 2.0

International Law 1.0 2.0
Project Management 1.7 3.0
European Culture 3.0 2
German Language A - 4.0

Seminar - 2.5
Internship - 0
Project 1.3 15
Thesis 1.0 30

Total 121
Gpa 1.4
 Bachelor of Engineering in Electronics
BVM Engineering College, Sardar Patel University, Vallabhvidyanagar
Grades
Exam Grade CR
Mathematics I B 4
Engineering Graphics B 4
Engineering Mechanics A 5
Basic Electronics & Electrical Engineering A 5
Introduction to Computer Technology I B 4
Basic Civil Engineering A 5
Basic Mechanical Engineering A 5
Mathematics II B 4
Electrical Engineering I A 5
Fundamental of Electronics B 5

Electronic Circuit I A 5
Network Analysis I A 5
Mathematics III A 4
Introduction to Computer Technology II A 5
Material Science B 5
Electrical Measurement I B 5
Electronics Circuit II A 5
Electromagnetic A 4
Digital Circuits B 5
Pulse and Switching Circuit A 5

Network Analysis II A 4
Wave Propagation & Antennas A 5
Digital Computer Organization A 5
Communication Engineering I B 5
Integrated Circuit Application A 5
Control System Engineering I A 5
Industrial Electronics A 5
Microprocessors I A 5
Computer Aided Circuit Analysis A 5
Economics and Management B 4

Communication Engineering II A 5
Electronics Instrumentation A 5
Microprocessors II A 5
Digital Communication I A 5
Digital Signal Processing A 5
Communication Theory B 4
IC technology & Design A 5
Process Control Instrumentation A 5
Optoelectronic A 5
Embedded System design A 5
Total 191
CPI 9.49
Equivalent % 81.79
Equivalent 4 Point GPA 3.87
Class First - With Distinction