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2. The output of a logic circuit depends upon the sequence in which the input is applied .the circuit
a) always 0 b)always 1
c) T flip-flop d) D flip-flop
10. When an inverter is placed between the inputs of an S-R flip-flop, the resulting flip-flop is a
c) T flip-flop d) D flip-flop
11. Which of the following input combinations is not allowed in an S-R flip-flop?
a)S=0,R=0 b)S=0,R=1
c)S=1,R=0 d)S=1,R=1
12. The functional difference an S-R flip-flop and J-K flip-flop is that
a) J-K flip-flop is faster than S-R flip-flop b) J-K flip-flop has a feedback path
c)J-K flip-flop accepts both input 1 d)J-K flip-flop does not required external clock
c) the inputs are complementary d)any one of the above input combinations is present
27. How many flip-flops are needed to divide the input frequency by 40?
29. The minimum number of flip-flops required for a mod -12 ripple counter is
30. The maximum number that can obtained by a ripple counter using five flip-flop is
33. In a counter circuit consisting of four J-K flip-flops, all the flip-flops get triggered simultaneously .this counter circuit
34. In a 4-bit binary ripple counter, for every input clock pulse
35. A 4 bit binary ripple counter uses flip-flops with propagation delay time of 25 ns each. The maximum possible time required
for change of state will be
36. A4 bit synchronous counter uses flip-flops with propagation delay time of 25 ns each. The maximum possible time required
for change of state will be
38. A 4-bit preset table up-counter has present input 0101.the presetting operation takes place as soon as the counter becomes
maximum, i.e .1111.the modulus of this counter is
40. The output frequency of amod-16 counter, clocked from a 20 -kHz clock input signal is
41. The output frequency of amod-12 counter is 6 kHz .its input frequency is
43.
A ripple counter using negative edge triggered flip flop as shown above. The flip-flops are cleared to 0 at R input.The feed
back logic Is to be degined to obtain the count sequence shown in the same figure.The correct feed back logic is
45. The given shows a ripple counter using positive edge triggered flip flops. If the present state of the counter Q 2Q1Q0= 011 .
Then its next state Q2Q1Q0 will be
46. Two flip-flops are to be connected as a synchronous as shown below that goes through the following Q 1Q0 sequence 00
01 11 10. The inputs D0&D1 respectively should be connected as
47. For the circuit shown in figure the counter state Q1Q0 will follows the sequence
48. What are the counting stages (Q1,Q2)for the counter shown below? Assume k2=1
(a) 11, 10, 00, 11, 10. (b) 01, 10, 11, 00, 01.. (c) 00, 11, 01, 10, 00. (d) 01, 10, 00, 01, 10.
49. Assuming all the flip flops are in reset condition only, the count sequence observed at Q A in the circuit shown as shown figure
50. Two D Flip-flops are connected as a synchronous counter that goes through the following Q B QA sequence 00 11 01
10 00 .The connections of the inputs DA and DB are
51. The output of the two flip-flops Q1,Q2 in the figure shown initialized to 00, The sequence generated at Q1 upon application
of clock signal is
(a) Toggle flip-flop (b)JK Flip flop (c) SR LATCH (D)Master-slave D FLIP-FLOP
53. The mod-n counter using synchronous binary up counter with synchronous clear input is shown in figure. The value of n
is----------------------
54. The figure shows a binary counter with synchronous clear input. With the decoding logic circuit the counter works as
(a) Mod-2 counter (b)mod-4 counter (c) mod-5 counter (d)mod-6 counter
55. The circuit shown consists of J-K Flip Flops, each with an active low synchronous reset input. The counter corresponding to
this circuit is
(a) Mod-5 counter (b) mod-6 counter (c) mod-7counter (d) mod-8 counter
56. A three bit pseudo random number generator is shown. Initially the value of output Y= Y 2 Y1 Y0. The value of output after
three clock pulses.
57. In the following sequential ckt the initial state of the circuit is Q0Q1=00. The state Q1Q0 immediately after 333 rd clock
pulse is
58. The figure shown is a digital circuit constructed using negative edge triggered J-K Flip-Flops. Assuming a starting state of
Q2Q1Q0=000. This state Q2Q1Q0=000 will repeat after ------------------ number of clock pulses
59. Assume that all the digital gates in the circuit shown in the figure are ideal, the resistor and the supply voltage is 5V. The D
flip-flops D1, D2, D3, D4 and D5 are initialized with logicvalues 0,1,0,1 and 0, respectively. The clock has a 30% duty cycle R
10k.
60. For the circuit shown in the figure, the delay of the bubbled NAND gate is 2 ns and that of the counter is assumed to be zero.
If the clock (Clk) frequency is 1 GHz, then the counter behaves as a
61. The current state QA QB of a two JK flip-flop system is 00. Assume that the clock rise-time is much smaller than the delay of
the JK flip-flop. The next state of the system is
62. A 4-bit shift register circuit configured for right-shift operation in is shown. If the present state of the shift register is ABCD
= 1101, the number of clock cycles required to reach the state ABCD = 1111 is _________.