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Amit Ashara
ABSTRACT
The IEEE Standard 1149.1-1990, IEEE Standard Test Access Port and Boundary-Scan Architecture
(JTAG) is a method for verifying designs and testing printed circuit boards after assembly. It is used as the
primary means for transferring data to a nonvolatile memory of an embedded system and debugging
embedded software.
This application report describes the physical connections for JTAG and design considerations to be taken
into account for a custom board. It also shows how to use the JTAG interface on the TM4C12x
LaunchPad for debugging the on-board microcontroller using an external debugger, or by using the on-
board debugger for debugging an off-board microcontroller.
NOTE: This document applies to TM4C12x Series microcontrollers. All screen captures reflect the
TM4C12x devices.
Contents
1 Introduction ................................................................................................................... 2
2 Overview of JTAG Protocol................................................................................................. 2
3 JTAG Debug Probes ........................................................................................................ 6
4 Using JTAG Debug Probes With TM4C12x .............................................................................. 9
5 TM4C12x JTAG Interface Specific Behaviors .......................................................................... 20
6 Debugging JTAG Connection Failure.................................................................................... 26
7 Conclusion .................................................................................................................. 28
8 References .................................................................................................................. 28
List of Figures
1 Test Access Port State Machine........................................................................................... 3
2 Point-to-Point Connection .................................................................................................. 4
3 Daisy Chain Connection .................................................................................................... 5
4 XDS560v2 Debug Probe Special Consideration ........................................................................ 8
5 TI 14-Pin Header............................................................................................................. 9
6 CTI 20-Pin Header ......................................................................................................... 10
7 ARM 10-Pin Header ....................................................................................................... 10
8 ARM 20-Pin Header ....................................................................................................... 11
9 Preparing EK-TM4C123GXL for External Debug Probe .............................................................. 12
10 Connecting External Debug Probe to EK-TM4C123GXL ............................................................. 13
11 Preparing EK-TM4C123GXL as a Debug Probe ....................................................................... 14
12 Preparing EK-TM4C123GXL as a Debug Probe ....................................................................... 15
13 Connecting External Debug Probe to EK-TM4C1294XL .............................................................. 16
14 Preparing EK-TM4C1294XL as a Debug Probe ....................................................................... 17
15 Connecting EK-TM4C1294XL as a Debug Probe for Off-Board TM4C12x ........................................ 18
16 JTAG Adapter Schematic ................................................................................................. 19
LaunchPad, Code Composer Studio are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
List of Tables
1 JTAG Header Pin Out ....................................................................................................... 6
2 Pin Connectivity .............................................................................................................. 7
3 Software Support for Debug Probe........................................................................................ 9
4 Debugging JTAG Failure on Software Download ...................................................................... 28
1 Introduction
JTAG defines a Test Access Port (TAP) and Boundary Scan Architecture for digital integrated circuits and
provides a standardized serial interface for controlling the associated test logic. It can be used to test the
interconnections of assembled printed circuit boards and obtain manufacturing information on the
components. It also provides a means of accessing and controlling the design for test features such as I/O
pin observation and control, scan testing, and debugging.
The JTAG port on TM4C12x is comprised of four pins:
Test Clock (TCK)
Test Mode Select (TMS)
Test Data In (TDI)
Test Data Out (TDO)
Even though the TM4C12x devices support Serial Wire Debug (SWD) mode, this application report
focuses on JTAG, which is a more widely adopted interface.
At power on, the TAP state machine (see Figure 1) is initialized to be in Test Logic Reset state. It moves
from one state to another based on the TMS value (shown as logic 0 or 1 on the transition arrow) with
every TCK. Once the state machine enters the Shift state, the TDI pin is used to serially shift in the IR or
DR. At the same time, the value captured in the shift register during the Capture state is shifted out on to
the TDO. When the Update state is executed, the value shifted in during the Shift state is updated to the
TAP for the next JTAG cycle.
NOTE: The pull up values mentioned in Table 2 are only for guidance. If there is a strong noise
source close to the JTAG traces or reset pin, then the pull up resistor value needs to be
decreased to make it less susceptible to noise coupled from traces.
3.3.2 XDS200
XDS200 is an intermediate debug probe that has better performance than XDS100 and lower cost than
XDS560v2.
3.3.3 XDS560v2
XDS560v2 is a high performance debug probe and is provided by multiple vendors. When setting
XDS560v2 as the debug probe, ensure that the Connection Properties has the option JTAG TCLK
Frequency (MHz) set to TCLK looped-back with a user-specified limit (see Figure 4).
3.3.5 I-jet
The I-jet debug probe is provided by IAR systems for IARs embedded workbench IDE.
3.3.6 ULINK2
The ULINK2 debug probe is provided by ARM for Keil uVision IDE.
Since there is no standard header available, the header needs to be wired to the external debug probe as
shown in Figure 10. The following steps must be followed for correct operation.
1. Connect the header pin EXTDBG to GND on the EK-TM4C123GXL. This is required so that when the
board is powered up, the ICDI detects a logic-low level and tri-state the JTAG pins allowing external
debug probe to drive the signal.
2. Connect the header pin GND to GND on the debug probe
3. Connect the header pin TCK to TCK on the debug probe
4. Connect the header pin TMS to TMS on the debug probe
5. Connect the header pin TDI to TDI on the debug probe
6. Connect the header pin TDO to TDO on the debug probe
7. Connect the header pin RST_N to reset on the debug probe
8. Make sure that the power selector is moved to DEVICE side
9. Connect the USB cable on the USB device connector
Now the external debug probe can be used to debug the main MCU on the EK-TM4C123GXL.
Since there is no standard header available, wire the header to the off-board TM4C12x (see Figure 12).
The following steps must be followed for correct operation:
1. Ensure that header pin EXTDBG is unconnected
2. Connect the header pin GND from EK-TM4C123GXL to GND on the external board
3. Connect the header pin TCK from EK-TM4C123GXL to TCK on the off-board TM4C12x
4. Connect the header pin TMS from EK-TM4C123GXL to TNS on the off-board TM4C12x
5. Connect the header pin TDI from EK-TM4C123GXL to TDI on the off-board TM4C12x
6. Connect the header pin TDO from EK-TM4C123GXL to TDO on the off-board TM4C12x
7. Connect the header pin RST_N from EK-TM4C123GXL to RST_N on the off-board TM4C12x
8. Make sure that the power selector is moved to DEBUG side
9. Connect the USB cable on the USB debug connector
Since there is no standard header available, wire the header to the off-board TM4C12x (see Figure 15).
The following steps must be followed for correct operation:
1. Connect the header pin GND from EK-TM4C1294XL to GND on the external board.
2. Connect the header pin TCK from EK-TM4C1294XL to TCK on the off-board TM4C12x.
3. Connect the header pin TMS from EK-TM4C1294XL to TNS on the off-board TM4C12x.
4. Connect the header pin TDI from EK-TM4C1294XL to TDI on the off-board TM4C12x.
5. Connect the header pin TDO from EK-TM4C1294XL to TDO on the off-board TM4C12x.
6. Connect the header pin RST_N from EK-TM4C1294XL to RST_N on the off-board TM4C12x.
7. Connect the USB cable on the debug connector.
Now the on-board ICDI can be used to debug an off-board TM4C12x device.
4. Press the Unlock button in LMFlashProgrammer. Press Yes in the pop up message box and then
press OK in the information message box (see Figure 18).
5. After some time, a pop up Information box will ask to release the reset. Release the reset and press
OK in LMFlashProgrammer utility (see Figure 19).
4. Type dbgjtag.exe f @xds200 Y unlock,mode=tiva if you are using XDS200 (see Figure 21).
When the button Test Connection is pressed, Code Composer Studio executes the JTAG instruction of
BYPASS that checks whether the JTAG physical connection integrity can be established. The result is
shown in a window (see Figure 23).
If the JTAG IR and DR Integrity scan-test succeeds, it means that the device core is out of reset and may
not have initialized itself. If, however, the integrity scan-test fails, the issue is in the power up process.
The following steps must be followed to make sure every known cause is eliminated till the source of the
issue is found:
1. Check with a digital multi-meter that the VDD and VDDA supply rails are 3.3 V.
(a) If not, then check the power supply aspect of the design.
2. Check with a digital multi-meter that the VDDC rail is 1.2 V.
(a) If not and providing a power from an external power source, make sure that the current limit is set
around 150 mA.
3. If the VDDC rail is at 1.2 V, make sure that the capacitance on the rail is as per the device-specific
data sheet and the layout of the capacitors are as per the system design guidelines and application
reports (see Section 8).
4. Check whether the JTAG header is correctly mounted and the TDIS pin (if available) is connected to
GND.
5. Check on the JTAG header the VTREF pin is 3.3 V.
6. Check whether the Reset Pin of the microcontroller is at 3.3 V.
(a) If not, connect an external pull up.
7. If using an external crystal oscillator, connect an oscilloscope on pin OSC0.
(a) If the crystal is not oscillating, check the solder on the crystal and capacitors.
(b) Always use the recommended crystals as per the device-specific data sheet.
8. If not using an external crystal oscillator, make sure that the pin OSC0 is connected to GND.
9. If using a TM4C129x device with integrated PHY, make sure that the RBIAS resistor is populated as
per device-specific data sheet recommendation.
7 Conclusion
This application report provides details on the JTAG interface of TM4C12x microcontrollers, the debug
probes and the software tools that can be used to erase, program, debug and unlock the microcontroller.
Also this document provides sample schematics for connecting different JTAG header pinouts with the
TM4C12x microcontroller and an in-depth description on using TM4C12x LaunchPads as a debug probe.
Finally, this document provides a detailed explanation on how to debug a JTAG connection failure, which
is critical when bringing up an application-specific embedded system design.
8 References
The following related documents and software are available on the TM4C web page:
Tiva C Series TM4C1294 Connected LaunchPad Evaluation Kit User's Guide
Tiva C Series TM4C123G LaunchPad Evaluation Board User's Guide
System Design Guidelines for the TM4C123x Family of Tiva C Series Microcontrollers
System Design Guidelines for the TM4C129x Family of Tiva C Series Microcontrollers
Processors wiki for JTAG
XDS100 wiki page
XDS110 wiki page
XDS200 wiki page
XDS560 wiki page
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