Inherited Connections PDF

Virtuoso Inherited Connections Tutorial
Document Revision Version 3.0
October 2005
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Contents
Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Typographic and Syntax Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
How Tools Interpret Net Names Ending with ! . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
How Netlisting Uses Switch and Stop View Lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2
Setting Up the Tutorial. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
How To Send Feedback About the Tutorial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
About the Tutorial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Required Database and Software Releases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Setting Up to Run the Tutorial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Downloading the Tutorial Files and Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Modifying the Tutorial .cshrc_inhConn File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Accessing the Tutorial Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3
Basic Concepts of Inherited Connections in a Hierarchy . . . . 25
Starting the Cadence Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
A Simple Example of an Inherited Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Defining a Net Expression for Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Defining a netSet Property to Override the Net Expression Default . . . . . . . . . . . . . . 30
Verifying Circuit Operation with Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Saving Your ADE Session and Quitting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
How the System Resolves Inherited Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Descend Path and Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
October 2005 3
Net Expressions with the Same Default Net Name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
About Multiple Power Supplies/Multiple Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Resistive Divider Using Inherited Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Descending Into the dividers_top Cellview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Querying an Instance for Inherited Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Displaying Property Names that Evaluate to the Default Net Name . . . . . . . . . . . . . 48
Displaying Cellviews and Paths for Evaluated Net Names . . . . . . . . . . . . . . . . . . . . . 50
Simulating the Resistive Dividers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4
Inherited Connections in Components . . . . . . . . . . . . . . . . . . . . . . . . . 59
Comparing Three- versus Four-Terminal Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Comparing the nmos symbol and spectre Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Comparing the nmos3 symbol and spectre Views . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Instantiating the nmos and nmos3 Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Adding a Net Expression to a Device Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Copying the nmos Transistor and Adding a Net Expression . . . . . . . . . . . . . . . . . . . 67
Creating a Test Schematic with nmos_mod . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Setting Up and Running a dc Sweep . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Plotting Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Creating a Netlist and Running a Simulation (Net/Sim #1) . . . . . . . . . . . . . . . . . . . . 78
Setting Up to Overlay Plots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Examining How Inherited Connections Push Net Names . . . . . . . . . . . . . . . . . . . . . . . . 79
Adding a Bulk Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Defining the vbulk Design Variable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Rerunning Netlisting and Simulation (Net/Sim #2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Overriding the Net Expression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Adding a Wire Name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Rerunning Netlisting and Simulation (Net/Sim #3) . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Saving Your ADE Session and Quitting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
5
Inherited Connections in an Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Creating Schematics Containing Inherited Connections . . . . . . . . . . . . . . . . . . . . . . . . . 89
Creating an Inverter with Inherited Connections on Supply Pins . . . . . . . . . . . . . . . . 90
October 2005 4
Creating an Inverter Symbol View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Create a Test Schematic for the Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Creating a Netlist and Running a Simulation (Net/Sim #1) . . . . . . . . . . . . . . . . . . . . 96
Creating an Inverter Symbol without Power Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Creating an Inverter String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Defining netSet Properties to Override Inherited Connections . . . . . . . . . . . . . . . . 104
Adding Another Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Creating a Netlist and Running a Simulation (Net/Sim #2) . . . . . . . . . . . . . . . . . . . 110
Making and Simulating a Ring Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Creating an Inverter Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Generating Layout Components from a Schematic . . . . . . . . . . . . . . . . . . . . . . . . . 120
Displaying Incomplete Nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Placing a Layout Template Instance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Placing Generated Components into the Layout Template . . . . . . . . . . . . . . . . . . . 128
Completing the Layout or Using the Provided Layout . . . . . . . . . . . . . . . . . . . . . . . 129
Verifying the Inverter Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Running Assura DRC for the inv layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Running Assura LVS to compare the inv layout with the inv schematic . . . . . . . . . . 133
Running Assura RCX for inv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Generating an Abstract View for inv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Creating Pins for the inv Abstract View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Creating an inv Extracted View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Creating an inv Abstract View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Verifying the inv Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Creating LEF for inv (Optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Exit the Cadence Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Library Characterization for inv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Setting Up the Environment for Library Characterization . . . . . . . . . . . . . . . . . . . . . 144
Running the Library Characterization for inv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
6
Using Explicit Pins vs. Implicit Terminals . . . . . . . . . . . . . . . . . . . . . 151
Showing Conflict in the Resolution of Implicit Inherited Connections . . . . . . . . . . . . . . 152
Generating a Layout from a Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Placing the Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
October 2005 5
Checking Connectivity Flight Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Routing with the Virtuoso Chip Assembly Router . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Adding a Substrate Contact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Running Assura DRC on the TB_dividers_top Layout . . . . . . . . . . . . . . . . . . . . . . . 165
Running Assura LVS on the dividers_top Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Section Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Adding Inherited Connections to a Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Adding Implicit Inherited Connections (Implicit Terminals) to a Schematic . . . . . . . 169
Adding Explicit Inherited Connections (Explicit Pins) to Schematics . . . . . . . . . . . . 172
Running a Test Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Verifying MSFF and Generating Library Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Running Assura DRC for the MSFF Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Running Assura LVS for the MSFF Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Running Assura RCX for the MSFF Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Generating an Abstract View for MSFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Creating Pins for the MSFF Abstract View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Creating an MSFF Extracted View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Creating an MSFF Abstract View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Verifying the MSFF Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Creating LEF for the Library (Optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Exit the Cadence Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Library Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Setting Up the Environment for Library Characterization . . . . . . . . . . . . . . . . . . . . . 196
Running Library Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Generating a Verilog Model with Characterized Delays for the Library . . . . . . . . . . 200
Creating HTML Data Sheets for the Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
7
Using Inherited Connections within an Analog Cell . . . . . . . . . 201
Simulating a Simple Comparator with Inherited Connections . . . . . . . . . . . . . . . . . . . . 203
Overriding the Default Connection on the Bulk Terminals . . . . . . . . . . . . . . . . . . . . 207
Comparing the Provided Layout against the comp Schematic . . . . . . . . . . . . . . . . . 208
Run Assura DRC to Verify the Layout Design Rules are Met . . . . . . . . . . . . . . . . . . 210
Run Assura LVS to Verify the Layout Matches the Schematic . . . . . . . . . . . . . . . . . 210
October 2005 6
Create an Extracted View of the Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Create a Verilog-A Model for the Comparator from the av_extracted View . . . . . . . 212
Viewing Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Generating an Abstract View for comp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Creating Pins for the comp abstract view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Creating a comp Extracted View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Creating a comp Abstract View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Verifying the comp Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Creating LEF for the Library (Optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
October 2005 7
October 2005 8
Preface
Inherited connections are an extension to the connectivity model that allow you to create
signals and override their names for selected branches of the design hierarchy. This flexibility
allows you to use
Multiple power supplies in a design
Overridable substrate connections
Parameterized power and ground symbols
Revision History
Revision History for Documentation
Version Date Changes Since Previous Version

v3.0 8/05 Added Chapter 7
v2.0 3/05 Added Chapter 6
v2.0 12/04 - Chapter 2: Added column to Table2-1 showing chapter numbers per require software;
3/05 updated IC software version to 5.1.41 USR1 and Assura to v3.1.3.
Chapter3: * Added section A Simple Example of an Inherited Connection on p. 24 -
33.
* Added instance to dividers_top schematic.
* Added section Querying an Instance for Inherited Connections on p. 45 -50.
Chapter 6: Added this new chapter, Using Explicit Pins vs. Implicit Terminals on
p. 143 - 197.
v1.3 Chapter 5: Added step to verify analog template on Symbol Generation Options form.
Added new chapter: Chapter 6, Explicit Pins vs. Implicit Terminals.
v1.2 10/5/04 Chapter 3: Corrections to output names (vout0 - vout4) on p.30-31, sections Figure 3-
1 Hierarchy of dividers_top Instance and Table 3-1 Power Connections for Resistive
Divider Instances; related corrections to equations on p.36.
Chapter 4: Added step 4 and graphic for nmos/nmos3 spectre views.
v1.0 9/04 Published on SourceLink for first time.
October 2005 9
Preface
Related Documents
The following documents give you more information about these associated tools.
For information about how to perform design tasks with the Virtuoso layout accelerator,
refer to the Virtuoso XL Layout Editor User Guide.
The Virtuoso Schematic Editor User Guide describes connectivity and naming
conventions for inherited connections and how to add and edit net expressions in a
schematic or symbol cellview.
The Virtuoso Layout Editor User Guide shows you how you can view or change
inherited connections information.
The Cadence Hierarchy Editor User Guide shows you how to use the hierarchy editor
to manage multiple components and views.
The Design Framework II User Guide provides basic information if you are not familiar
with Cadence terms and starting your system.
The Cadence Application Infrastructure User Guide provides additional information
about the architecture.
Typographic and Syntax Conventions

This section describes typographic and syntax conventions used in this manual.
text indicates text you must type exactly as it is presented.
z_argument Indicates text that you must replace with an appropriate

argument. The prefix (in this case, z_) indicates the data type
the argument can accept. Do not type the data type or
underscore.
[ ] Denotes optional arguments. When used with vertical bars, they

enclose a list of choices from which you can choose one.
{ } Used with vertical bars and encloses a list of choices from which
you must choose one.
| Separates a choice of options; separates the possible values

that can be returned by a Cadence SKILL language function.
Indicates that you can repeat the previous argument.
October 2005 10
Preface
=> Precedes the values returned by a Cadence SKILL language

function.
text Indicates names of manuals, menu commands, form buttons,

and form fields.
Important
The language requires many characters not included in the preceding list. You must
type these characters exactly as they are shown in the syntax.
October 2005 11
Preface
October 2005 12
1
Introduction
This manual explains inherited connections (both implicit and explicit), shows how to use
inherited connections, and makes recommendations about the best methodology to follow
when using inherited connections.
Inherited connections allow you to selectively override global signals in designs created in the
Virtuoso Schematic Editor and to make those overrides available to other Cadence tools
across the design flow.
There are two types of inherited connections: implicit and explicit.
Implicit Inherited Connection Explicit Inherited Connection
Implicit Explicit
Terminal Terminal
Associated with a wire; terminal Associated with a pin; terminal

name is implied. name is explicitly defined.
You create an implicit inherited connection when you associate an inherited connection
with a wire (signal). In this case, the terminal name is implied.
You create an explicit inherited connection when you associate an inherited connection
with a specific pin, and therefore with its associated terminal. In this case, the terminal
name is explicitly defined.
A pin always defines an explicit connection, with or without inherited connections.
Important
When you are creating a block that will be shared, distributed, or used by others,
(such as an IP block, standard cell library, or PDK elements), Cadence recommends
that you specify the interfaces for that block fully and unambiguously. This means
that the connections for such a block need to be created as explicit connections.
October 2005 13
Introduction
Note: A terminal is a database object, used to establish the logical connection between
different levels of hierarchy; a pin is a physical realization of a terminal. Every pin is
associated with one and only one terminal; a terminal can have multiple pins associated with
it.
Figure 1-1 Terminal-Pin-Net Data Model
term pins
pin
1 to many relationship
(logical) (physical)
term
net
1 to 1 relationship
term
pins
net
Inherited connections are especially useful for designs in which you want more than one
power supply using the same voltage and for creating overridable substrate connections and
parameterized power and ground signals. Inherited connections allow you to build one library
containing components potentially requiring different power and ground connections in
different parts of a design.
Global signals work best when the entire circuit contains just one type of power supply, such
as vdd!, and one type of ground, such as gnd!. For designs that have multiple power
supplies and grounds, using global signals creates the possibility of conflicting global signal
names; all signals in the design with the same name could be merged into a single,
electrically-equivalent signal across all the cellviews in the design hierarchy.
For example, if you used the global signal vdd! in a block, and other, unrelated blocks
created by other engineers also used vdd!, your vdd! signal could erroneously be
connected to the vdd! signals in the other blocks.
If you need separate power supplies in a hierarchical design, such as analog and digital, two
different power supplies with the same voltage, or two power supplies with different voltages,
such as +1.8 V and +2.2 V, you can associate an inherited connection with the signal by
defining a property name and a default global signal name. This lets you override the global
signal name further up in the hierarchy.
October 2005 14
Introduction
Inherited connections have two parts:

A net expression that contains a property name and provides a default global net name
One or more netSet properties providing a signal name that overrides the default global
signal name
You define an inherited connection with a net expression of the following format, where the
default signal name must be a global signal:
[@myPropertyName:%:defaultGlobalSignalName]
For example, [@myPower:%:vdd!]
To override the default, you define a netSet property at a higher level in the hierarchy. The
value of the netSet property overrides the signal name for all matching net expressions in
the hierarchy below, unless the netSet property is redefined in the intervening levels of
hierarchy. The signal specified by a netSet property does not have to be a global signal.
For example, you might assign vdd! as the default signal name and then override it with a
different signal name using a netSet property. The netSet override could be for a different
global net name, such as digPwr1!, or for a local net, such as digPwr2. (Note: no
exclamation point.)
How Tools Interpret Net Names Ending with !

The default net name in a net expression must be a global net name. The exclamation point
(!) is used as part of the net name to indicate to the tool that the net name is global. Some
tools interpret the exclamation point; other tools do not.
For example, the Virtuoso Schematic Editor Check and Save command uses the ! as an
indicator to set the internal database flag for the signal as global. However, the Virtuoso
Layout Editor does not interpret ! but treats it as any other character in the net name.
Because all connections are physically represented in the layout editor, global signals are not
treated as connected solely because their names indicate global signals. Rather, a physical
connection must exist to make an actual connection.
You can configure some tools, typically verification tools, including LVS, to interpret ! and
treat such net names as global.
Note: The overriding signal from the netSet property does not need to be global.
October 2005 15
Introduction
How Netlisting Uses Switch and Stop View Lists

It is important to understand how the Analog Design Environment (ADE) creates netlists
before working with inherited connections.
When ADE creates a netlist, it uses two lists. Each netlister has a:
Switch View List containing a list of view names used to replace the view name in the
current instance when netlisting. A view name in this list is called a switched view. You
direct the ADE netlister to use the view with the correct connectivity information by
specifying that view in the Switch View List field of the Environment Options form.
Stop View List containing view names used as the stopping view for netlisting. ADE
constructs this global list. The Stop View List for the Spectre simulator contains a
Spectre view, which defines the interconnects at the most basic or primitive level of the
hierarchy.
For each instance in the top cellview, ADE does the following:
The netlister reads the first view name in the Switch View List.
If the switched view for the current instance exists in the library, the netlister compares
the switched view name to the view names in the Stop View List (starting with the first
view in the Stop View List).
If the switched view name is found in the Stop View List, the netlister opens the cellview
of the instance and switches its view by replacing the existing view with the switched
view; the netlister adds the modified instance to the netlist as a primitive device, and no
further expansion of the instance occurs below this level.
If the switched view is not found in the Stop View List, the netlister does not modify the
view for the current instance.
If the switched view does not exist in the library, the netlister reads the next view name
in the Switch View List, and repeats the process above.
This process is shown in How the Netlister Expands Hierarchy on page 17.
October 2005 16
Introduction
Figure 1-2 How the Netlister Expands Hierarchy
Start with the top-level cell.
Read the first view in the

Switch View List.
Does the view exist No Read the next view in the

for this cell? Switch View List.
Yes
Choose the next cell instance
in current cellview.
Is the view on the No

Descend into view.
Stop View List?
Yes
Netlist the instance.
You can see the Switch View List with the ADE Setup Environment command. For the
Spectre simulator, the default Switch View List identifies views in the following order:
October 2005 17
Introduction
When the Spectre view exists, the netlister uses the connections defined in the Spectre view
to generate the netlist. The system switches the Spectre master into the netlist, replacing the
symbol master; hence, the view actually used in the netlist is referred to as the switched
master, while the view instantiated in the design is referred to as the instantiated master.
Note: For a master, the number of terminals in the switched view (in this case, the Spectre
view) can be greater than the number of terminals in the instantiated view (in this case, the
symbol view). The reverse is an error condition.
An example of how the netlister replaces the instantiated master with the switched master is
seen later in the tutorial, in the section titled, Instantiating the nmos and nmos3 Transistors
on page 63.
For more information about the Switch View List and Stop View List, see the Cadence
Analog Design Environment User Guide.
Four questions to ask yourself when creating a netlist with ADE:

What is my instantiated master?
What is my switched master?
How am I going to traverse the hierarchy (Switch and Stop View Lists)?
What do I expect the resulting netlist to contain?
October 2005 18
2
Setting Up the Tutorial
This chapter covers the following topics:

How To Send Feedback About the Tutorial on page 19
Required Database and Software Releases on page 20
Setting Up to Run the Tutorial on page 21
Accessing the Tutorial Documentation on page 23
How To Send Feedback About the Tutorial

Currently, this manual is available only from SourceLink. You can submit feedback by sending
an email to:
cdsdoc_feedback@cadence.com?subject=Virtuoso_Inherited_Connections_Flow_Guide
Note: If clicking on the link above does not open your mail tool, please use your mail tool to
send an email to cdsdoc_feedback@cadence.com with the Subject line Virtuoso
Inherited Connections Flow Guide
Your email should include the following information:

Document Name: Virtuoso Inherited Connections Flow Guide
Document Version: example: 3.0 (Document version number is on first page.)
Software Version: example: 5.1.41 USR2
Your Name: example: John Smith
Your Phone Number: (xxx) xxx-xxxx
Your Comments:
October 2005 19
About the Tutorial

The tutorial illustrates the recommended use models for inherited connections. The tutorial
presents basic concepts by parameterizing a signal name so that it can be overridden with
another name from higher in the design hierarchy. The tutorial does not cover all possible
uses of inherited connections.
The tutorial begins with a single component, an NMOS transistor, to examine how inherited
connections can be used to set bulk signal values. It then takes a simple inverter to layout to
show how inherited connections work in an integrated fashion across front-end and back-end
tools. The successive chapters explain the implications of using explicit versus implicit
inherited connections, and add to the complexity of the design to demonstrate how the basic
concepts can be extended throughout the full design process.
Required Database and Software Releases

The tutorial has been tested with the software versions listed in the table below. The table
contains the software and versions required to run the tutorial.
Table 2-1 Software and Versions Required for the Tutorial
Type This to Verify Required in these

Stream Name Version Number
Version Chapters
IC IC5.1.41 USR2 icfb -W Chapters 3-7
Assura ASSURA_3.1.3 assura -W Chapters 5, 6
USR1
Encounter SOC41_USR4 encounter -version Chapters 5, 6
SignalStorm (TSI) TSI41 slc -version Chapters 5, 6
Virtuoso Chip VCAR 11.2.41 vcar -W Chapter 6
Assembly Router USR1
Virtuoso VSdE4.1 USR1 vsde -version Chapter 7
Specification-
driven
Environment
October 2005 20
When you type each version command in a terminal window, the system returns a statement
similar to the following; in the example, the version number is in bold font.
Table 2-2 Testing Software Versions
Type to Verify Version System Returns Version Information

icfb -W sub-version 5.10.41_USR2.19.52
assura -W sub-version 3.1.3_USR1
encounter -version @(#)CDS: First Encounter v04.10-s324_1 (32bit)
02/18/2005 15:54 (Solaris 5.8)
....
....
slc -version SignalStorm - Library Characterization -
Version v04.10-p022_1 - sun5 32-bit (05/20/2004
20:57:47)
vcar -W Virtuoso Chip Assembly Router V11.2.41.01 made
2004/12/01 at 09:16:00
vsde -version VSdE 04.10.USR1.150 Wed Nov 3 20:51_38 PST 2004
lion
Setting Up to Run the Tutorial

The following sections tell you how to set up your system for the inherited connections tutorial.
Downloading the Tutorial Files and Documentation

Download the tutorial files and documentation by doing the following:
1. Log into SourceLink.
2. Go to the following URL:
http://sourcelink.cadence.com/docs/files/Tutorials/inheritedconnectiontutorial.html
3. Download the inhConn_tutorial_3p0.dir.tar.Z database.
4. Uncompress the .tar.Z file by typing
uncompress inhConn_tutorial_3p0.dir.tar.Z
October 2005 21
5. Untar the .tar file by typing

tar xvf inhConn_tutorial_3p0.dir.tar
The following directory is created:

inhConn_tutorial_3p0
This directory contains everything necessary to run the tutorial.
Modifying the Tutorial .cshrc_inhConn File

Set the Cadence install directory environment variables in the tutorial .cshrc_inhConn
file to your local installation directories. These variables are
Table 2-3 Environment Variables Required for the Tutorial
Stream Name Environment Variable

IC CDSHOME
Assura ASSURAHOME
Encounter ENCOUNTER
SignalStorm TSIHOME
VCAR CCTHOME
VSDE ACV_ROOT
For example, modify the CDSHOME environment variable to point to the latest CDBA IC 5.1.41
USR2 release:
setenv CDSHOME /cds/IC5141_USR2
Other variables must be set as shown in the tutorial .cshrc_inhConn file. For example,
CDS_Netlisting_Mode must remain set to Analog. In the .cshrc_inhConn file, change
only the lines described below. Leave all other lines unchanged.
1. Edit the .cshrc_inhConn file and modify path for the CDSHOME, ASSURAHOME,
ENCOUNTER, TSIHOME, and ACV_ROOT variables to point to the appropriate software.
2. Uncomment the setenv statements for these variables by removing the pound
characters (#).
3. Save the .cshrc_inhConn file.
4. In the tutorial directory, source the .cshrc_inhConn file by typing
source .cshrc_inhConn
October 2005 22
Accessing the Tutorial Documentation

Access the Virtuoso Inherited Connections Flow Guide by opening the Portable
Document Format (.pdf) documentation file, which is located in the ./doc directory:
1. From the tutorial directory, change to the tutorial documentation directory:
cd ./doc
2. Verify the version number of the documentation file.

The documentation filename has the following format:
inhconntut_versionNumber.pdf
3. Start the Acrobat Reader software so that it opens the documentation file, by typing
acroread inhconntut_3p0.pdf
October 2005 23
October 2005 24
3
Basic Concepts of Inherited Connections
in a Hierarchy

Starting the Cadence Software on page 26
A Simple Example of an Inherited Connection on page 26
Defining a Net Expression for Power on page 27
Defining a netSet Property to Override the Net Expression Default on page 30
Verifying Circuit Operation with Simulation on page 32
How the System Resolves Inherited Connections on page 35
Descend Path and Evaluation on page 39
Net Expressions with the Same Default Net Name on page 41
About Multiple Power Supplies/Multiple Voltages on page 41
Resistive Divider Using Inherited Connections on page 41
Descending Into the dividers_top Cellview on page 42
Querying an Instance for Inherited Connections on page 48
Displaying Property Names that Evaluate to the Default Net Name on page 48
Displaying Cellviews and Paths for Evaluated Net Names on page 50
Simulating the Resistive Dividers on page 54
This chapter starts by showing you how to create an inherited connection and override it at a
higher level in the hierarchy with a netSet property. It then explains how the system resolves
more complex inherited connections and includes an example of a design using multiple
power supplies with different voltages to better illustrate how inherited connections work.
October 2005 25
Basic Concepts of Inherited Connections in a Hierarchy
Starting the Cadence Software

Before running the tutorial, you must always source the .cshrc_inhConn file that you
modified in Modifying the Tutorial .cshrc_inhConn File on page 22.
1. Change to the top-level directory containing the tutorial files.
2. In the tutorial directory, source the .cshrc_inhConn file by typing
source .cshrc_inhConn
3. Verify the path to the Cadence software your system is pointing to by typing
which icfb
If the system returns the correct path, continue to the next step; otherwise, edit the
.cshrc_inhConn file in the tutorial directory to point to the correct software version and
source your .cshrc_inhConn file again.
4. Start the Cadence software for the full tutorial flow by typing:
icfb &
The software starts and the Command Interpreter Window (CIW) opens.
A Simple Example of an Inherited Connection

The system evaluates a net expression by moving up a branch of hierarchy, looking for a
netSet property with the same property name; in looking for a match, the system traverses
all branches that include a net expression. When it finds a match, the system uses the
netSet property value (instead of the default net name) as the signal to be inherited. When
it does not find a match, the system uses the default net name defined in the net expression.
In this example, you create an inherited connection with a net expression on a schematic, and
then override its default net name with a netSet property at a higher level of hierarchy. You
also verify that the inherited connection passed the overriding net name down the hierarchy
by running a simulation.
October 2005 26
Defining a Net Expression for Power

1. Open the following schematic:
Library: tutorial
Cell: divBy2
View: schematic
2. Change the display options to show the net expression:
a. Choose Options Display.
b. In the Display Options form,

For Net Expression Display, choose expression only.
Click OK.
3. Create a net expression for the supply voltage by doing the following:
a. In the divBy2 schematic window, choose Add Net Expression.
b. In the Add Net Expression form,
October 2005 27
For Property Name, type POWR.

For Default Net Name, type vdd!.
For Entry Style, choose manual.
You are prompted to point at a location for the net expression.

4. Attach the net expression by doing the following:
a. Click above the top of the wire coming out of the upper resistor.
Click above this wire.
You are prompted to point at a pin or wire to attach the net expression.
October 2005 28
b. Click on the wire coming out of the upper resistor.
Click on this wire.
The divBy2 schematic should now look like this:
Notice the format of the net expression:

[@POWR:%:vdd!]
where the
@ sign indicates the property name: POWR
% sign is a place-holder for an inherited signal name, if any
vdd! is the default global signal name
October 2005 29
* indicates that the connection is inherited

The default global signal name (vdd!) is used to connect to the wire unless another signal
name is assigned to the property name POWR further up in the hierarchy.
5. Cancel the Add Net Expression form.
6. Check and save the divBy2 schematic.
7. Close the divBy2 schematic window.
Defining a netSet Property to Override the Net Expression Default

Define a netSet property to override the power signal inside the divBy2 instance by doing
the following:
Library: tutorial
Cell: divBy2_test
View: schematic
This cell contains an instance of the divBy2 symbol cellview, and the power supply is
POWR4. You add a netSet property to the divBy2 instance to pass the supply signal
name down to the POWR property in the divBy2 cell, overriding its default net name of
vdd! with POWR4.
October 2005 30
2. Select the divBy2 instance.

3. Choose Edit Properties Objects (or press q).
4. In the User Property section, click Add.
5. In the Add Property form,
a. for Name, type POWR.
b. For Type, choose netSet.
c. For Value, type POWR4.

The form should look like the following:
d. Click OK.
The property name POWR is added to the Edit Object Properties form, with its local
value set to POWR4.
October 2005 31
6. In the Edit Object Properties form, for the POWR property, set Display to both.
7. Click OK.
The netSet property is displayed on the schematic, just above the divBy2 instance.
8. Deselect the divBy2 instance.

9. Check and save the divBy2_test schematic. Ignore the two warnings found along with
the yellow box indicators on the schematic for the floating net out. Close the Schematic
Check display.
Verifying Circuit Operation with Simulation

To verify that the inherited connection passed the supply voltage into the resistor divider as
expected, you run a short simulation on the resistor divider. The output voltage on the signal
named out should be half the voltage of the supply.
1. In the divBy2_test schematic window, start the Virtuoso Analog Design Environment
(ADE) by choosing Tools Analog Environment.
October 2005 32
2. Verify that the model library file is set to inhConnLib.scs by choosing Setup Model
Libraries in the ADE form.
3. Cancel the Model Library Setup form.

4. Set up a transient analysis of 1ns by
a. In the ADE form, choosing Analyses Choose.
b. In the Choosing Analyses form, typing 1n for Stop Time and clicking on OK.
5. Select the in and out signals for plotting by doing the following:
a. In the ADE form, choose Outputs To Be Plotted Select on Schematic.

You are prompted to select the outputs on the schematic.
b. In the divBy2_test schematic, click the wire named POWR4 and the wire named out,
then press Esc.
The ADE form should look like this:
October 2005 33
6. In the ADE window, to generate the circuit netlist and run the simulation, choose
Simulation Netlist and Run.
When the simulation completes, a wavescan display appears. It should look similar to
this:
The wavescan display shows that POWR4 is 2.0 volts and out is 1.0 volt, which
demonstrates how an inherited connection passes a signal name as a property down the
design hierarchy.
7. Close the netlist window and exit the wavescan window.
Saving Your ADE Session and Quitting

Save the state of your session, then you can reload it to use again.
1. In the ADE window, choose Session Save State.
October 2005 34
2. In the Saving State form,
a. In the Save As field, type divBy2_test.
b. Click OK.
3. In the ADE form, choose Session Quit.
4. Close the divBy2_test schematic window.
How the System Resolves Inherited Connections

To illustrate how the system evaluates inherited connections for a more complex case, the
example below shows three levels of hierarchy, starting at the lowest-level, which is cell_C.
cell_C consists of 2 two-input nand gates. Read through the example on the next few pages;
performing the steps is not necessary.
For simple cases, like the one shown in A Simple Example of an Inherited Connection on
page 26, when the system finds a match, it stops looking.
Symbol for cell_C Schematic for cell_C
I1
I2
In the example, descend into the schematic and create a wire in cell_C.
Schematic for cell_C
I1
I2
Create wire here, in cell_C.
October 2005 35
On the new wire, define a net expression with the property name myProp_1 and the default
value of vdd! for power.
I1
I2
Create net expression [@myProp_1:%:vdd!]

on the unconnected wire in cell_C.
With the display option set to show net expressions, the following is displayed:
[@myProp_1:%:vdd!]
I1
I2
Now create the next higher level of hierarchy, cell_B, containing two instances of cell_C.
Schematic for cell_B
I1 of cell_C I2 of cell_C
October 2005 36
And add a netSet property to cell_C I1 that sets myProp_1 to the global signal abc!,
which displays as follows:
myProp_1 = abc!
The arrow shows that the netSet property, myProp_1 = abc!, applies to instance I1 of
cell_C. Add one more level of hierarchy: cell_A, containing one instance of cell_B and
one instance of cell_C.
Schematic for cell_A
I1 of cell_B I2 of cell_C
Add a netSet property to I1 of cell_B, setting myProp_1 to the global signal xyz!, which
displays as follows:
myProp_1 = xyz!
October 2005 37
From the top down, the three levels of hierarchy look like the following:
myProp_1 = xyz!
Highest level of hierarchy
myProp_1 = abc! Middle level of hierarchy

[@myProp_1:%:vdd!]
I1
I2
Lowest level of hierarchy
There is more than one possible descend path to a particular instance through the three
levels of hierarchy. Different instance lineages can result in different values for the net
expression in cell_C.
October 2005 38
Descend Path and Evaluation

The path that the system follows to descend from the top level of hierarchy to a specific
instance below is know as an instance lineage or descend path. A different instance
lineage could produce a different override valueor no override at all.
Descend Path Result of Evaluation

/I1(cell_B) / I1(cell_C) myProp_1 = abc!
/I1(cell_B) / I2(cell_C) myProp_1 = xyz!
/I2(cell_C) myProp_1 = vdd!
Here is an illustration showing all three levels of hierarchy:
cell_A
myProp_1 = xyz! cell_B: I1

myProp_1 = abc!
cell_C: I1
cell_C: I2 cell_C: I2
I1 I1 I1
I2 I2 I2
To resolve the value of a net expression, the system starts searching for a matching netSet
property at one level above the lowest-level cell containing the net expression, and continues
up the hierarchy looking for a matching property name. Once a matching netSet property is
found, all net expressions beneath that level are resolved to the value of matching netSet
property. netSet properties higher in the hierarchy do not override netSet properties below
them in the hierarchy.
The table below explains how the system evaluated the net expression for each instance
lineage in the example:
October 2005 39
Descend Path How Net Expression Is Evaluated Result of Evaluation

/I1(cell_B) / I1(cell_C) Starting with cell_C, the system myProp_1 = abc!
looks for a netSet property of the
name myProp_1 in the next higher
level of hierarchy in the descend path,
cell_B I1, and finds
myProp_1 = abc!
The system stops looking as soon as
it finds a matching netSet property
that is set to a net name, and uses
the value abc! for the global signal in
cell_C.
/I1(cell_B) / I2(cell_C) Starting with cell_C, the system myProp_1 = xyz!
name myProp_1 in cell_B I2. It
finds none, looks up one more level
up to cell_A. At cell_A, the system
finds the netSet property
myProp_1 = xyz!
The system stops looking and uses
the value xyz! for the global signal in
cell_C.
/I2(cell_C) Starting with cell_C, the system myProp_1 = vdd!
name myProp_1 in cell_A. The
system does not find a netSet
property, stops searching, and uses
the default value, vdd!, for the global
signal in cell_C:
myProp_1 = vdd!
October 2005 40
Net Expressions with the Same Default Net Name

When defining net expressions within a cellview, you cannot assign the same default net
name to more than one, unique property name; doing so would result in an error when you
check and save the design with the Virtuoso Schematic Editor. When resolving a net
expression in the local context of a single cellview (rather than in the context of a complete
hierarchy), the system uses the local signal corresponding to the default net name from the
net expression to store the whole net expression.
However, you can assign the same default net name to different property names when the
net expressions are in different cellviews.
For example, the following net expressions defined in the same cellview would produce
errors. The system would try to associate two different net expressions with the same signal,
vdd!.
[@vdd_a:%:vdd!]
[@vdd_b:%:vdd!]
If the net expressions above are defined in different cellviews, there is no conflict.
About Multiple Power Supplies/Multiple Voltages

You can use inherited connections when separate power supplies are needed in a
hierarchical design, such as analog and digital, multiple power supplies with the same
voltage, or multiple power supplies with different voltages. Although you usually want only a
single voltage, the resistor example in this chapter uses multiple voltages to better illustrate
how inherited connections work.
In later sections of the tutorial, for typical transistor-level schematics, inherited connection
netSet properties are used as in the most common situation: to implement multiple supplies
and multiple grounds that have the same voltage.
Resistive Divider Using Inherited Connections

Using inherited connections to connect different power supplies to the same circuit allows you
to designate specific power supplies by overriding the net expression default net name at
higher levels in the hierarchy.
If you do not use inherited connections to define overridable net names, create a different
master cell for each instance that uses a different power supply. With inherited connections,
October 2005 41
you can define various netSet properties to determine the net name for the same master
cell when placed in different instances.
The circuit of a resistive divider that you use in the following steps shows how inherited
connections can be used to connect the same master cell to different power supplies in
different instances.
Descending Into the dividers_top Cellview

Library: tutorial
Cell: dividers_top
View: schematic
October 2005 42
2. Choose Options Display and set Net Expression Display to value[expression].
This basic circuit is a simple resistive divider, used to divide the supply voltage by two. In
this circuit, three instances of the divBy2Inh cell are used at different levels of hierarchy
and connected to different power supplies using inherited connections.
Next, you descend into the dividers2, divBy2Inh, and divBy2b schematics, to see
that the bottom level contains resistors.
3. Descend into each instance until you can see the resistors.
The resistive divider cells, divBy2a and divBy2b, do not have power supplies defined
with inherited connections. These cells are similar to divBy2Inh; the only difference is
their power supply connections.
October 2005 43
The following illustration shows the relationship between all of the instances, down to the
level of their resistors:
October 2005 44
Figure 3-1 Hierarchy of dividers_top Instance
dividers_top
hSupA = POWR1! vout0
vdd = POWR3!
I0 dividers2 vdd = POWR4! [@hSupA:%:POWR4!]
I0 dividers1 I1 divBy2Inh
vdd_inherit
POWR4! [@vdd:%:vdd!]*
I0 divBy2a I1 divBy2Inh
1K
vdd! vdd_inherit vout3
1K 1K
1K
1K 1K vout1
I2 divBy2b
vcc
1K
vdd = POWR1! [@hSupA:%:POWR2!] vout4
I1 divBy2Inh
vdd_inherit
1K
vout2
1K
vdd = POWR4! [@hSupB:%:POWR4!]

1K I3 divBy2Inh
vdd_inherit
1K
vout5
1K
October 2005 45
4. Close the dividers_top schematic window.
Below is a summary of the power supply connections for the three resistive divider instances.
The slash ( / ) indicates the top level of the dividers_top instance hierarchy:
Table 3-1 Power Connections for Resistive Divider Instances
Instance Name Connects to Description of Power Supply

/I0/I0/I0 vout0 Power supply is implemented by the vdd
instance from the basic library, so the power
divBy2a
supply for this instance is vdd!.
Note: divBy2a and divBy2b are similar
circuits, each connected to a different power
supply.
/I0/I0/I1 vout1 Power supply is implemented by the
vdd_inherit instance from the basic
divBy2Inh library, which has the net expression
[@vdd:%:vdd!].
Going up one level of hierarchy
(dividers1), there is no netSet property.
Therefore, the power supply remains at the
default of vdd!.
Going up two levels of hierarchy
(dividers2), there is no netSet property.
Therefore, the power supply remains at the
default of vdd!.
At the top level (dividers_top) there is the
netSet property vdd=POWR3!. The net
expression default is overridden by the
POWR3!, so the power supply for this
instance is POWR3!.
October 2005 46

/I0/I1 vout2 Power supply is implemented by the
divBy2Inh
library, which has the net expression
[@vdd:%:vdd!].
At next higher level of hierarchy
(dividers2), there is the netSet property
vdd=[@hSupA:%:POWR2!].
At the top level of hierarchy
(dividers_top), there is the netSet
property hSupA=POWR1!. The net
expression default is overridden by the
POWR1!, so the power supply for this
instance is POWR1!.
/I1 vout3 Power supply is implemented by
divBy2Inh library, which has the net expression
[@vdd:%:vdd!].
(dividers_top), which is the top level,
there is the netSet property
vdd = [@hSupA:%:POWR4!].
The hSupA netSet property refers to a net
expression that is not overridden at this level
in the hierarchy, so the power supply for this
instance defaults to POWR4!.
/I2 vout4 Power supply is implemented by the vcc
instance from the basic library, so the power
divBy2b
supply of this instance is vcc!.
October 2005 47

/I3 vout5 Power supply is implemented by the
divBy2Inh
library, which has the net expression
[@vdd:%:vdd!].
(dividers_top), which is the top level,
there is the netSet property
vdd = [@hSupB:%:POWR4!].
The hSupB netSet property refers to a net
expression that is not overridden at this level
in the hierarchy, so the power supply for this
instance defaults to POWR4!.
Querying an Instance for Inherited Connections

You can query an instance to display the net expression properties that have not been
overwritten by a netSet property, along with their default net names.
You can query an instance to display a list of the net names resulting from the overriding of a
net expression default net name by a netSet property higher up in the local hierarchy. And,
for each net name in the list, you can display the cellviews containing the related net
expressions and the paths to the instance and/or cell names where the property was first
defined in a net expression.
Displaying Property Names that Evaluate to the Default Net Name

Library: tutorial
Cell: TB_dividers_top
View: schematic
October 2005 48
The TB_dividers_top schematic opens.
2. Select the dividers_top instance.

3. Choose Edit Net Expression Available Properties.
The Net Expression Available Property Names form appears.
October 2005 49
For the selected instance, the form shows all net expression property names that have
not yet been overridden by a netSet property, hence the term Available.
Looking from the top level in the dividers_top hierarchy, the properties hSupA and
hSupB have not been overwritten (reset), and therefore still evaluate to their default net
names of POWR4!.
vdd = [@hSupA:%:POWR4!] vdd = [@hSupB:%:POWR4!]

I1 divBy2Inh I3 divBy2Inh
[@vdd:%:vdd!]* [@vdd:%:vdd!]*
1K 1K
1K 1K
There is one more net expression with the same property name at a different level in the
dividers_top hierarchy, vdd = [@hSupA:%:POWR2!], that is redefined by the
netSet property hSupA = POWR1!, so it is not listed in the form. For an illustration
showing the complete hierarchy of dividers_top, see Hierarchy of dividers_top
Instance on page 45.
4. In the Net Expression Available Property Names form, click Cancel.
Displaying Cellviews and Paths for Evaluated Net Names

1. Choose Edit Net Expression Evaluated Names.
October 2005 50
The Net Expression Evaluated Names form appears.
For the selected instance, the form lists the net names (Evaluated Name) resulting from
the overriding of a net expression default net name by a netSet property defined higher
in the hierarchy. For the dividers_top instance, there are three evaluated net names:
POWR3!, POWR1!, and POWR4!.
For each evaluated net name, you can list the cellviews containing net expressions that
evaluate to that net name due to an overriding netSet property higher in the hierarchy.
2. In the Net Expression Evaluated Names form, click POWR1!.
At the bottom of the form, the following buttons become active:
3. Click List Cellviews with Selected Evaluated Name.
October 2005 51
The Cellviews with Evaluated Net Expression Name form appears.
The form shows all cellviews containing net expressions that evaluate to the net name
you clicked on ( POWR1! ). There is only one cellview listed, divBy2Inh, for which the
property vdd and default value of vdd! are defined.
For each evaluated net name, you can list the paths to the instance and/or cell names
where the property was first defined in a net expression.
4. In the Cellviews with Evaluated Net Expression Name form, click Cancel.
5. In the Net Expression Evaluated Names form, click Power4! and then List
Occurrences for Selected Evaluated Name.
October 2005 52
The Occurrence paths to Evaluated Name form appears.
The form shows the paths to all occurrences of net expressions that evaluate to the net
name you clicked on, POWR4!. There are two paths listed:
/I0/I1/
/I0/I3/
At the bottom of the form, the Display occurrence paths with cyclic field lets you
choose how to display the paths: by instance names, cell names, or instance and cell
names.
6. Display the paths by cell names by, in the Display occurrence paths with field,
choosing cell names.
The paths changes to the following:
7. In the Occurrence paths to Evaluated Name form, click Cancel.
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8. In the Net Expression Evaluated Names form, click Cancel.
Simulating the Resistive Dividers

Now you netlist and simulate the resistive divider circuit to see how the same master cell
(divByInh), which uses inherited connections for its power supply, can be used to generate
several different outputs, based on the resolution of the net expression.
1. In the TB_dividers_top schematic window, start the Analog Design Environment (ADE)
by choosing Tools Analog Environment.
2. In the ADE form, verify that the model library file is set to inhConnLib.scs,
a. Choose Setup Model Libraries.
The end of the path should point to: /inhConnLib.scs.
b. In the Model Libraries form, click OK.

3. In the ADE form, choose Analyses Choose.
4. In the Choosing Analyses form,
October 2005 54
a. For Stop Time, type 1n.
b. Click OK.
5. In the ADE form, choose the output signals for plotting:
a. Choose Outputs To Be Plotted Select on Schematic.
b. In the TB_dividers_top schematic, for the dividers_top instance, click the wires
named vout0, vout1, vout2, vout3, vout4, and vout5, then press Esc.
Click on these wires.
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The ADE window should look like this:
Save the Analog Design Environment session state if you want to take a break from the
tutorial and continue later. Upon your return, reload the saved session state prior to using
the ADE functionality.
6. In the ADE form, save the state of the ADE setup for future use:
a. Choose Session Save State.
b. In the Save As field, type: TB_dividers_top.
c. Click OK.
7. In the ADE form, create a netlist of the TB_dividers_top schematic and simulate it by
choosing Simulation Netlist and Run in the schematic window.
October 2005 56
After a few moments, a WaveScan Window appears with results similar to those shown
below.
In the WaveScan Window, notice the voltage value (along the Y axis) for each signal.
October 2005 57
The voltages for the outputs of the six voltage dividers are 0.9v, 1.5v, 1.0v, 2.0v,
2.5v, and 2.0v, which were computed as follows:
vdd 1.8v
vout0 = ---------- = ---------- = 0.9v
2 2
POWR3! 3v
vout1 = --------------------- = ------ = 1.5v
2 2
POWR1! 2v
vout2 = --------------------- = ------ = 1.0v
2 2
POWR4! 4v
vout3 = --------------------- = ------ = 2.0v
2 2
vcc 5v
vout4 = ---------- = ------ = 2.5v
2 2
POWR4! 4v
vout5 = --------------------- = ------ = 2.0v
2 2
8. Close the netlist window and exit the wavescan window.
9. Quit ADE by choosing Session Quit.
10. Close the TB_dividers_top schematic window.
October 2005 58
4
Inherited Connections in Components

Comparing Three- versus Four-Terminal Devices on page 60
Comparing the nmos symbol and spectre Views on page 60
Comparing the nmos3 symbol and spectre Views on page 61
Instantiating the nmos and nmos3 Transistors on page 63
Adding a Net Expression to a Device Pin on page 66
Adding a Net Expression to a Device Pin on page 66
Creating a Test Schematic with nmos_mod on page 73
Setting Up and Running a dc Sweep on page 74
Plotting Outputs on page 77
Creating a Netlist and Running a Simulation (Net/Sim #1) on page 78
Setting Up to Overlay Plots on page 79
Examining How Inherited Connections Push Net Names on page 79
Adding a Bulk Connection on page 79
Defining the vbulk Design Variable on page 81
Rerunning Netlisting and Simulation (Net/Sim #2) on page 81
Overriding the Net Expression on page 82
Adding a Wire Name on page 82
Rerunning Netlisting and Simulation (Net/Sim #3) on page 83
Saving Your ADE Session and Quitting on page 84
October 2005 59
Comparing Three- versus Four-Terminal Devices

While four terminal connections provide the most flexibility, you might want to use three-
terminal symbols for nmos transistors. Bulk connections for nmos transistors in positive
voltage CMOS processes are usually connected to ground, so there is no need for four
terminals.
In some cases, however, you might want to either define an inherited connection to override
the default bulk connection or use four-terminal nmos transistor symbols. For example, this
would apply to an input stage with an nmos transistor pair, within a pwell floating above
ground, where the bulk is connected to the source and not to ground.
Comparing the nmos symbol and spectre Views

From the inhConnLib library, open the symbol and spectre views of the nmos transistor:
1. Choose Tools Library Manager.
2. In the Library Manager window, select inhConnLib, nmos, and symbol.
3. Open the symbol view by choosing File Open.
4. Repeat for the spectre view.
Figure 4-1 nmos symbol View
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Figure 4-2 nmos spectre View
Notice that for both the symbol and spectre views, there are four terminals.
5. Close the nmos windows.
Comparing the nmos3 symbol and spectre Views

To discover how the hidden bulk terminal gets assigned a signal name, examine the three-
terminal nmos3 transistor symbol and spectre views and compare them to the four-terminal
nmos transistor views to see how the terminals are defined.
From the inhConnLib library, open the symbol and spectre views of the nmos3 transistor:
1. In the Library Manager window, select inhConnLib, nmos3, and symbol.
2. Open the symbol view by choosing File Open.
3. Choose Options Display and set Net Expression Display to value only.
4. Repeat for the spectre view.
October 2005 61
Figure 4-3 nmos3 symbol View
Figure 4-4 nmos3 spectre View
Notice that the nmos3 symbol view has only three terminals, while the nmos3 spectre
view has one more terminal, the bulk node, bulkn.
Note: You direct the Virtuoso Analog Design Environment netlister to use the view with
the correct connectivity information by specifying that view in the Switch View List. ADE
then uses the Switch View List to determine which view to use for the netlist. In this case,
the netlister uses the spectre view rather than the symbol view. For more information, see
How Netlisting Uses Switch and Stop View Lists on page 16.
October 2005 62
5. Look at the properties of the bulk pin in the nmos3 spectre view:
a. Select the bulk terminal by clicking on it.
Click on bulk terminal.
b. Press q to display the Edit Object Properties form.
The bulk terminal has a net expression property. The property name is bulkn, and it has
a default net name of gnd!. The bulk terminal is connected to the global signal gnd!,
unless you connect it to something else.
6. Close the Edit Object Properties form and the nmos3 windows.
Instantiating the nmos and nmos3 Transistors

Compare the symbol and schematic instances of the nmos and nmos3 transistors by doing
the following:
1. Create a new schematic cellview in the tutorial library:
October 2005 63
a. In the CIW, choose File New Cellview.
b. In the Create New File form, choose tutorial for Library Name, type myTest1 for
Cell Name, and type schematic for View Name.
c. Click OK.
The myTest1 cellview opens.
2. Instantiate the symbol views from inhConnLib for the nmos transistor:
a. In the myTest1 schematic window, choose AddInstance (or press i).
b. In the Add Instance form, click Browse.
c. In the Library Browser window, click inhConnLib, nmos, and symbol.
d. Click in the myTest1 schematic window to place the nmos symbol instance.
3. Repeat the steps above to place the nmos3 symbol instance.
4. Repeat the steps above to place the nmos and nmos3 spectre instances.
October 2005 64
The myTest1 schematic window looks similar to this.
Instantiated (symbol views)
Switched (spectre views)
The instantiated masters (symbol views) differ for the nmos and nmos3 instances: the
nmos3 symbol view has only three terminals. The switched masters (spectre views)
match: both nmos and nmos3 spectre views have four terminals. For more information
about the instantiated master versus the switched master, see How Netlisting Uses
Switch and Stop View Lists on page 16.
Note: When you netlist a design built with ordinary symbol views, the netlister instead
uses the spectre view to define terminals because the spectre view is listed in the Stop
View List. There is a bulkn inherited connection in the nmos3 spectre view which would
be switched in during netlisting to connect the bulk.
5. Press the Esc key to end the Add Instance command.
6. To see that, by default, bulkn connects to gnd!, in the myTest1 schematic window,
select the bulk terminal of the nmos3 spectre view and press q.
October 2005 65
The Edit Object Properties form appears, showing that bulkn connects to gnd!.
7. Click Cancel to close the Edit Object Properties form.

8. Close the tutorial myTest1 schematic window. When asked to save the schematic, click
either Yes or No.
Adding a Net Expression to a Device Pin

Inherited connections let you assign a net expression to either a wire or a pin to cause a
default net name to be passed to the connecting wire. You can also override the default value
by defining a netSet property higher up in the hierarchy.
You add a net expression to a four-terminal nmos transistor, instantiate it to create a test
schematic, and then simulate the design to show the effects of the net expression.
First you make a copy of the nmos transistor and add a net expression to the bulk pin on the
copy of the nmos transistor. This makes physical connections to the bulk pin optional and
allows the use of inherited connections. You then explore the effect of the net expression and
netSet properties by simulating the design with the modified nmos symbol.
October 2005 66
Copying the nmos Transistor and Adding a Net Expression

To add a net expression to a primitive pin without affecting the inhConnLib library, make a
copy of the nmos transistor and all of its views in the tutorial library, and then add the net
expression to the copy.
Copying the nmos Transistor to Create nmos_mod
Copy the nmos transistor from inhConnLib to the tutorial library by doing the following:
1. In the CIW, choose Tools Library Manager, unless the Library Manager is already
open.
2. In the Library Manager form, click inhConnLib and nmos cell.
3. Right-click over the nmos cell, and select Copy from the pop-up menu.
4. In the Copy Cell form,
a. For the To Library, choose tutorial.
October 2005 67
b. For the To Cell, type nmos_mod.
c. Click OK.
October 2005 68
The Copy Problems form appears.
5. In the Copy Problems form, click OK.

The system copies all views for the nmos cell from the inhConnLib library to the
nmos_mod cell in the tutorial library.
October 2005 69
Adding a Net Expression to nmos_mod

1. Open, for edit, the symbol view of the nmos_mod cell in the tutorial library, which looks
similar to this:
bulk pin
2. Choose Options Display and set Net Expression Display to value only.
3. Add a net expression to the bulk pin by doing the following:
a. Choose Add Net Expression.

The Add Net Expression form appears.
b. For Property Name, type BULK.
c. For Default Net Name, type gnd!.
October 2005 70
d. Click to place the net expression label near the bulk pin.
The net expression looks like this:
[@BULK:%:gnd!]
You are prompted to point at a pin to attach the net expression.
e. Click the bulk pin. The display changes to B* to indicate that the bulk pin, B, has a
net expression attached to it.
f. Press the Esc key to end the command.
B*
October 2005 71
4. Verify that the default value for the bulk terminal is gnd! by selecting the bulk terminal
and pressing q to display the Edit Object Properties form.
5. Cancel the Edit Object Properties form.

6. Check and save the nmos_mod symbol master by choosing Design Check and
Save.
7. Close the nmos_mod symbol window.
October 2005 72
Creating a Test Schematic with nmos_mod

Follow these steps to create this schematic:
1. Create a new schematic cellview in the tutorial library and name it myTest2.
2. From the tutorial library, instantiate the symbol view of the nmos_mod transistor.
3. From the analogLib library,
a. Instantiate the symbol view of gnd.

b. For power,
Add a vdc power supply between the gate and source, with dc voltage set to
vgate.
Add a vdc power supply between the drain and source, with dc voltage set to
vsup.
4. Connect the nmos_mod transistor to the power sources.
5. Check and Save your design.
Notice that
The bulk terminal shows connection to gnd!. The asterisk (*) after gnd! means that the
connection is currently going to the default net name defined in the net expression.
October 2005 73
The schematic extractor does not report a floating pin for the bulk terminal. This is
because the net expression in the symbol provides a value for connectivity, even when
there is no physical wire making a connection to the pin.
Setting Up and Running a dc Sweep

Set the path to the model libraries, define the design variables, and set up a dc sweep on the
vsup power source for 0 4 volts, by doing the following:
1. In the myTest2 schematic window, choose Tools Analog Environment.
2. Verify that the model library file is set to inhConnLib.scs by choosing Setup Model
3. Cancel the Model Library Setup form.

4. Define the design variables by doing the following:
a. In the Analog Design Environment form, choose Variables Copy From Cellview.
The two variables, vsup and vgate appear in the Design Variables section.
b. In the Analog Design Environment form, choose Variables Edit.
October 2005 74
c. In the Editing Design Variables form,

In the Table of Design Variables column, click vsup to select it, type 4 for
Value (Expr), and click Apply.
In the Table of Design Variables column, click vgate to select it, type 1 for
Value (Expr), and click OK.
5. Set up the dc sweep for multiple simulations from 0 to 4 by doing the following:
a. In the Analog Design Environment form, choose Analyses Choose.

The Choosing Analyses form appears.
b. In the Choosing Analyses form,

For Analysis, turn on dc.
For Sweep Variable, turn on Design Variable.
For Variable Name, type vsup.
October 2005 75
For Start-Stop, type 0 for Start and 4 for Stop.
Click OK.
October 2005 76
The Choosing Analyses form disappears. The Analyses section of the ADE form looks like
this:
Plotting Outputs
Plot the drain terminal of the nmos_mod transistor by doing the following:
1. In the Analog Design Environment form, choose Outputs To Be Plotted Select on
Schematic.
At the bottom of the Analog Design Environment form, the system prompts
> Select on Schematic Outputs to Be Plotted
2. In the myTest2 schematic window, click the drain terminal of the nmos_mod transistor.
Click on the drain terminal.
The system adds the following line to the Outputs section of the Analog Design
Environment form:
3. Press the Esc key to end the selection of outputs for plotting.
October 2005 77
4. In the Outputs section of the Analog Design Environment form, double-click on the
NM0/D line to display the Setting Outputs form.
5. In the Setting Outputs form,
a. Make sure Plotted is turned on.
b. Turn on Saved.
c. Click OK.
The plotting outputs are now set.
Creating a Netlist and Running a Simulation (Net/Sim #1)

Create a netlist from the myTest2 schematic by doing the following:
1. In the Analog Design Environment form, choose Simulation Netlist Create.
2. In the netlist window, look at the following line:
bulk pin connection
NM0 (net07 net010 0 0) nmos1 w=(2u) 1=180n as=1.2p ad=1.2p ps=5.2u pd=5.2u \
m=(1)*(1) region=triode
The bulk terminal is connected to the 0 net, where 0 represents the global signal gnd!.
3. Close the netlist window.
4. In the Analog Design Environment form, choose Simulation Run.
October 2005 78
The WaveScan Window shows one signal for NM0/D.
5. Keep the WaveScan Window open, but close the simulation results window.
You now change the bulk node voltage using a physical override, then compare the simulation
results.
Setting Up to Overlay Plots

You can see all of your plots in the same WaveScan Window if you continuously keep the
WaveScan Window open and choose the Append mode:
1. In the ADE window, in the lower right-hand corner, set Plotting Mode to Append.
Examining How Inherited Connections Push Net Names

Inherited connections push the name of the net (not a numerical value) to any connected wire.
You connect the bulk to a power supply and examine the value that is assigned to the wire.
Adding a Bulk Connection

For many applications, the source and bulk of an nmos transistor are connected to ground,
so the difference between the two is zero. In some cases, either the bulk is in a separate well
October 2005 79
connected to a different voltage, or the source is elevated from ground (as in a cascode
connection), so the source-to-bulk voltage is negative. This has the effect of increasing the
threshold voltage on the MOSFET, thereby reducing the drain current.
You can simulate the effect above by adding a supply to the bulk and setting it to a negative
value. Be aware that inherited connections push their default values onto connected wires
that are not assigned a user-defined name.
The following sections show the proper way to handle an inherited connection on a bulk
terminal.
Modify the myTest2 schematic to match this picture by following these steps:
1. From the analogLib library,
a. Add the symbol view of the resistor, res, to the right of the bulk node.
b. Add the symbol view for a vdc power supply between the bulk node and ground, and
set the dc voltage to vbulk.
c. Connect the resistor and vbulk supply as shown above.

2. Check and save your design.
October 2005 80
Defining the vbulk Design Variable

You have added a third design variable to the myTest2 schematic. Before netlisting and
simulating again, define a value for the design variable, vbulk.
1. In the Analog Design Environment form,
a. Choose Variables Copy From Cellview.
b. Choose Variables Edit.
c. In the Editing Design Variables form,

In the Table of Design Variables column, click vbulk to select it.
For Value (Expr), type -0.2.
Click OK.
Rerunning Netlisting and Simulation (Net/Sim #2)

1. In the Analog Design Environment window, choose Simulation Netlist and Run to
create a new netlist and rerun the simulation.
2. Look at the WaveScan Window.
Although you applied a different bulk voltage of -0.2 V to the design, the waveforms for
both circuits share the same curves. Now you explore what happened.
October 2005 81
3. In the Analog Design Environment window, select Simulation Netlist Display.

bulk terminal connection
NM0 (net07 net010 0 0) nmos1 w=(2u) 1=180n as=1.2p ad=1.2p ps=5.2u pd=5.2u \
m=(1)*(1) region=triode
The bulk terminal is still connected to ground because the net expression pushed its
default net name to the unnamed net between the resistor and the bulk node in the
schematic. Therefore, you have the same simulation as before.
5. Keep the WaveScan Window open, but close the netlist and simulation results windows.
Overriding the Net Expression

When you have an inherited connection, and you want to make sure that the right voltage gets
assigned to a connected wire, name the wire. For instance, if the value that the inherited
connection pushes to the wire is the global signal gnd!, the simulator sees the wire as
shorted to ground. You can override this by naming the wire.
Adding a Wire Name

When you assign a name to a wire, your assigned name overrides the default value of any
net expression that would otherwise apply.
To override the net expression default of gnd!, you add a name to the wire connecting the
vbulk power source to the bulk terminal.
1. In the myTest2 schematic window, choose Add Wire Name.
The Add Wire Name form appears.
2. In the Add Wire Name form, for Names, type b1.
October 2005 82
3. In the myTest2 schematic window, click on the wire that connects the vbulk power
source to the bulk terminal.
Click here to name wire.
4. Press the Esc key to end the Add Wire Name command.
5. Check and save your design.
Rerunning Netlisting and Simulation (Net/Sim #3)

1. In the Analog Design Environment window, select Simulation Netlist Create.
bulk pin connection
NM0 (net07 net010 0 b1) nmos1 w=(2u) 1=180n as=1.2p ad=1.2p ps=5.2u \
pd=5.2u m=(1)*(1) region=triode
The bulk terminal is now connected to the b1 net.

3. Resimulate the design.
October 2005 83
The vbulk signal is offset from the other two signals.
Overlaying the three waveforms shows that first two signals are the same. The signal,
created by adding the name b1 to the net, overrides the default value (gnd!) of the net
expression on the bulk terminal. The bulk terminal is now connected to the resistor
instead of to gnd!.
With the bulk wire named b1, the voltage on the net is allowed to be -0.2 V as you would
expect, rather than being pushed to ground by the net expression on the bulk terminal.
In a design with multiple power sources, where there could be a conflict caused by
inherited connection net expressions pushing default values on to nets, you can avoid
potential conflicts by naming the affected nets.
4. Close the simulation results and WaveScan windows.
Saving Your ADE Session and Quitting

Save the state of your session. You can reload it to use again.
1. In the ADE window, choose Session Save State.
2. In the Saving State form,
October 2005 84
a. Type a unique name in the Save As field, such as myTut2_completed.
b. Click OK.
4. Close the myTest2 schematic window.
October 2005 85
October 2005 86
5
Inherited Connections in an Inverter
You can use inherited connections to connect different instances of the same cell to different
power supplies. For example, inherited connections let you design a system with one block
running at 1.8 volts and another block running at 2.2 volts. Instead of maintaining different
sets of cells in your library for each voltage and having to hardwire the power connections of
every cell to the desired voltage, you can create a single block with inherited connections and
define netSet properties on instances of that block to pass connections down to its cells.
Of course, you can only do multi-voltages when the base schematic contains transistors
compatible with both voltages. If your design used 1.0 and 2.5 volts in a 90nm process, for
example, you would use different base transistors for each voltage. The example used in this
tutorial uses multi-voltages for illustrative purposes to demonstrate the concepts of inherited
connections, but there are practical limits to such an application. In real-life designs, you
would create separate base schematics where the transistors and components are optimized
for specific voltages.
In this chapter, you create an inverter that uses inherited connections on its power pins so
that, after placing several instances in a schematic, you can make the power connections
using properties, rather than by hardwiring them. To prove this concept, you create an inverter
chain, test it, and then form it into a ring oscillator.
Finally, you create a physical layout for the inverter, retaining the inherited connections, and
then verify that the layout meets design rules and matches the schematic. As a last step, you
perform a library characterization on the inverter to show that the inherited connection works
through the entire design process.

Creating Schematics Containing Inherited Connections on page 89
Creating Schematics Containing Inherited Connections on page 89
Creating an Inverter Symbol View on page 91
Create a Test Schematic for the Inverter on page 93
Creating an Inverter String on page 101
October 2005 87
Defining netSet Properties to Override Inherited Connections on page 104

Adding Another Power Supply on page 109
Making and Simulating a Ring Oscillator on page 114
Creating an Inverter Layout on page 120
Generating Layout Components from a Schematic on page 120
Placing a Layout Template Instance on page 126
Placing Generated Components into the Layout Template on page 128
Displaying Incomplete Nets on page 125
Completing the Layout or Using the Provided Layout on page 129
Verifying the Inverter Layout on page 130
Running Assura DRC for the inv layout on page 131
Running Assura LVS to compare the inv layout with the inv schematic on page 133
Running Assura RCX for inv on page 134
Generating an Abstract View for inv on page 135
Creating Pins for the inv Abstract View on page 137
Creating an inv Extracted View on page 139
Creating an inv Abstract View on page 139
Verifying the inv Abstract on page 141
Creating LEF for inv (Optional) on page 141
Exit the Cadence Software on page 143
Library Characterization for inv on page 144
Setting Up the Environment for Library Characterization on page 144
Running the Library Characterization for inv on page 146
October 2005 88
Creating Schematics Containing Inherited Connections

In this section, you create an inverter with inherited connections on its power pins, create a
symbol view for it, and see how inherited connections push the default signal name onto the
supply wire from the net expression defined for the inverter schematic. Then, you
Use the Analog Design Environment to plot the input and output pins, create a netlist,
and run a simulation
Create another symbol view, this time without power and ground pins, and place two of
each type of symbol view to form a chain of inverters
For the third and fifth inverters, define netSet properties to override the default values
of the inherited connections defined for the inverter cellview
Add a wire name to the power net connecting the first three inverters
This is called a physical override. A physically named wire always takes priority over
lower-level inherited connections; over both the default value of net expressions, and
over the value of instance netSet properties, if any.
Allow the fourth inverter to take on the default values from the inherited connections
Netlist again and notice how all the inverter grounds and power pins are connected
Finally, modify the inverter string to form a ring oscillator and simulate it
Then observe the various output voltages to see how power supplies have been used in
the simulation.
October 2005 89
Creating an Inverter with Inherited Connections on Supply Pins

Follow these steps to create this schematic:
1. Create a new schematic view for the inv cell in the tutorial library.
2. Add PMOS and NMOS instances:
a. Choose AddInstance and click Browse.
b. From the inhConnLib library,

Choose the symbol view of pmosInh, change its total width to 2.02u, and
instantiate it.
Choose the symbol view of nmosInh, change its total width to 0.85u (850n), and
instantiate it.
There are net expressions on the bulk pins that say floatingbulk!.
3. Choose AddPin and add input ( A ) and output ( Y ) pins.
For the power and ground pins, you create inherited connections by defining net
expressions on the Add Pin form.
October 2005 90
4. In the AddPin form add a pin for power by doing the following:
a. For Pin Names, type POWR and GRND.
b. For Direction, choose InputOutput.
c. Turn on Attach Net Expression.
d. For Property Name, type POWR.
e. For Default Net Name, type vdd!.
f. Click to place the POWR pin.

5. Add a pin for ground and define a net expression with Property Name set to GRND and
Default Net Name set to gnd!.
The default net names displayed in the schematic changes from POWR to vdd! and
from GRND to gnd! after you check and save the design.
6. Add wires as needed to connect the pins.
7. Check and save the inv schematic.
After you check and save, the displays on the bulk pins showing the net names change to
vdd! and gnd!, which are the default net names pushed to the wires by the inherited
connections defined for the POWR and GRND pins.
Creating an Inverter Symbol View

1. Choose DesignCreate CellviewFrom Cellview and click OK.
2. In the Symbol Generation Options form,
a. Remove GRND from the Top Pins field.
b. Type GRND in the Bottom Pins field.
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The Symbol Generation Options form should look like this:
Note: The tutorial .cdsenv file sets the schematic tsgTemplateType to analog, so
the analog template is loaded automatically.
3. Click OK.
4. If a dialog box appears asking to overwrite base cell CDF, click No.
The inv symbol view should look like this:
October 2005 92
When you create a symbol view from the inv schematic, the system copies the net
expressions attached to the schematic POWR and GRND pins to the symbol pins.
5. Add the name inv to the symbol by selecting Add Note Note Text and typing inv in
the note box. Then click in the center of the symbol to place the name.
6. Check and save the inv symbol view.
7. Close the symbol and schematic windows.
Create a Test Schematic for the Inverter

Follow these steps to create this test schematic:
1. Create a new schematic cellview in the tutorial library and name it invtest.
2. From the tutorial library, add an instance of the symbol view of inv.
3. From the analogLib library, add instances of the
gnd symbol
vdc symbol and assign a dc voltage of 2.2.
October 2005 93
vpulse symbol and assign the following values:
Voltage 1 0.0
Voltage 2 1.8
Delay time 1n
Rise time 200p
Fall time 200p
Pulse width 5n
Period 10n
The system adds an s to the time fields to represent seconds.

4. Add wires as needed.
5. Choose AddWire Name and name the input wire in and the output wire out.
6. Check and save the schematic.
Because the output wire is not connected to anything, the system issues two warnings
about floating output. Ignore the warnings.
Inherited connections push the global signal name vdd! onto the supply wire from the
net expression defined for the inverter schematic.
7. Check the net name by selecting the supply output wire and pressing q.
Click on supply wire.
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The Edit Object Properties form shows the net name for the supply output wire is vdd!.
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Check the behavior of the inverter by performing a simple transient simulation. The output
should be a square wave that is inverted compared to the input.
1. Start the Analog Design Environment (ADE) by choosing ToolsAnalog Environment.
2. Verify that the model library file is set to inhConnLib.scs by choosing SetupModel
3. Choose a transient analysis of 50ns by
a. In the ADE form, choosing AnalysesChoose.
b. In the Choosing Analyses form, typing 50n for Stop Time and clicking on OK.
4. Select the in and out signals for plotting:
a. In the ADE form, choose OutputsTo Be PlottedSelect on Schematic.
b. In the invtest schematic, click the wire named in and the wire named out, then
press Esc.
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The ADE window should look like this:
Save the Analog Design Environment session state if you want to take a break from the
tutorial and continue later. Upon your return, reload the saved session state prior to using
the ADE functionality.
5. In the ADE form, save the state of the ADE setup for future use by choosing Session
Save State and typing in the Save As field, invtest1.
6. In the ADE form, create a netlist of the invtest schematic by choosing Simulation
NetlistCreate in the schematic window.
7. Look in the netlist for the inverter subcircuit, shown in the following lines:
subckt inv A Y inh_GRND inh_POWR

NM0 (Y A inh_GRND inh_GRND) nmos1 w=(850n) 1=180n as=510f ad=510f \
ps=2.9u pd=2.9u m=(1)*(1) region=triode
PMO (Y A inh_POWR inh_POWR) pmos1 w=(2.02u) 1=180n as=1.212p ad=1.212p \
ps=5.24u pd=5.24u m=(1)*(1) region=triode
The connections to the inverter signals inh_GRND and inh_POWR are hardwired to
gnd! and vdd! in the schematic. The netlist also shows this for the inverter
instantiation:
I0 (in out 0 vdd!) inv
The value of vdd! is forced by the dc voltage supply.

v0 (vdd! 0) vsource dc=2.2 type=dc
8. In the ADE form, run a simulation by choosing SimulationRun.

9. In the WaveScan Window, choose Axis Strips to split the display.
October 2005 97
The display should look like this (colors have been changed for visibility):
If you only see one of the waveforms, set the display for two strips by double-clicking on
the trace, and setting the Trace Attribute, Strip Chart Visible Rows to 2.
The output is the inverse of the input, and swings from 0 to 2.2 volts. If your waveform
does not look like this, check the schematic and the settings for the power supply and
pulse generator.
10. Close ADE by choosing SessionQuit.
11. Leave the invtest schematic window open, you use it later.
October 2005 98
Creating an Inverter Symbol without Power Pins

Frequently, digital blocks have symbols without power and ground connections explicitly
drawn. Inherited connections can be used to convey power and ground to the circuit.
To show this, you make a copy of the symbol view of the inverter and remove the power and
ground pins from the copy, then set up the cross-view checker to specify that this mismatch
is intentional.
1. In the Library Manager,
a. Click tutorial for library, inv for Cell, and symbol for View.
b. Right click over symbol and choose Copy from the pop-up menu.
c. In the Copy View form, for To, change the View field from symbol to symbol2, and
click OK.
2. Open the tutorial symbol2 view and
a. Delete the POWR and GRND pins and their connecting wires.
The symbol2 view should look like this:
b. To save the tutorial inv symbol2 view, choose DesignSave. (Do not check and
save yet).
c. Close the tutorial inv symbol2 Symbol Editing window.
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Setting Up the Cross-View Checker
Set up the cross-view checker options to ignore the deleted POWR and GRND pins on the
second version of the symbol view.
1. Open the tutorial inv schematic view.
2. In the inv schematic window, choose CheckOptions.
3. In the Schematic Check Options form,
d. For Views To Check, add symbol2.
e. For Ignore Terminals, click specify and type POWR GRND.
f. For For Views, type symbol2.

The Cross View Check Options section of the Schematic Check Options form
should look like this:
g. Click OK.
4. In the tutorial inv schematic window, choose CheckCurrent Cellview.
The schematic check should complete with no errors because you specified that the
cross-view checker should ignore POWR and GRND for the symbol2 view.
5. Save and close the tutorial inv schematic window.
October 2005 100

Creating an Inverter String

In the tutorial invtest schematic window, follow the steps in the sections below to create a
string of inverters showing the various ways inherited connections can be used to supply
voltages to individual cells.
1. To the right of the original inverter from the tutorial library, add two more instances of the
symbol view of inv and two instances of the symbol2 view of inv, as shown below:
symbol
views
symbol2
views
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2. Connect the four instances together in a string, and add the following wire names to the
output of each inverter: out2, out3, out4, and out5.
3. Connect the POWR pin on the second inverter to the POWR pin on the first inverter, and
the POWR pin on the third inverter to the POWR pin on the second inverter, thereby
connecting both inverters to the vdc power source of 2.2 volts.
1 2 3
Leave the ground pins on the two inv symbol instances unconnected; they default to the
inherited connection value of gnd!.
Adding a Wire Name to the Power Net
Add a physical override to the power net connecting the first three inverters by naming the
wire. A physically named wire always takes priority over lower-level inherited connections,
over both the default value of net expressions and the value of netSet properties.
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Add a wire name, vtop, to the power net connecting the first three inverters.
Your inverter chain should now look like this:
1 2 3
4 5
Currently,
The first (left-most) inverter is hardwired to the ground symbol, and its supply is
connected to the wire named vtop, so the inherited connections to GRND and POWR
are overridden.
October 2005 103

The second and third inverters are connected to gnd! from the default value for the
inherited connection, and their power supplies are also connected to vtop.
The fourth and fifth inverters have no POWR or GRND pins, so the POWR and GRND
connections defined inside the symbol views default to the net expression values of vdd!
and gnd!, respectively.
Defining netSet Properties to Override Inherited Connections

Now you define netSet properties on the third and fifth inverters to override the default
values of the inherited connections you originally defined for the inv cellview.
Although inherited connection net expressions and netSet properties push their values onto
connecting wires, naming a wire is a physical override that takes priority over all lower-level
inherited connections (both net expressions and netSet properties).
This section shows that even though you have defined a netSet property, when you name
the connecting wire, the net name on the wire overrides the net name from the netSet
property.
Note: The value of a netSet property does not have to be a global signal.
Adding netSet Properties to the Third Inverter
You define a netSet property for the third inverter, to override the default value defined
earlier with a net expression.
To add a netSet property to the third inverter,

1. Select the third inverter (inv symbol) and edit its object properties (press q).
Select third inverter.
1 2 3
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2. In the Edit Object Properties form, click Add.

3. In the Add Property form, add a property for power:
a. Change the property type to netSet.
b. For Name, type POWR.
c. For Value, type vdd!.
d. Click OK.
4. In the Edit Object Properties form,
a. For the POWR user property, set Display to both.
b. Click OK.
5. Deselect the third inverter by clicking in an empty area of the schematic.
6. Check and Save the schematic. Note that while the POWR property on the third inverter
is set to vdd!, the evaluated value shown attached to the pin is now vtop. This is because
even though you defined the netSet property POWR = vdd!, your user-defined wire
name of vtop overrides the netSet property, since the third inverter is still physically
connected to vtop.
Evaluated Value
3
October 2005 105

Adding netSet Properties to the Fifth Inverter
To show how inherited connections provide power and ground connections using default net
names, do not modify the fourth inverter with a netSet property. However, you add a netSet
property to the fifth inverter (the last inv symbol2 instance).
4 5
No netSet property Add netSet to fifth

on fourth inverter. inverter.
1. Select the fifth inverter (the last inv symbol2 instance).

2. Add netSet properties to the fifth inverter using the following values (click Edit
PropertiesObjectsAdd), and set Display to both:
Name POWR
Value vtop
and
Name GRND
Value gnd!
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The fifth inverter now looks like this:
The value of gnd! overrides the default. In this case, the default value and the netSet
value are both gnd!, but these values do not have to be the same.
3. Check and Save the invtest schematic. Note that a wire named vdd! appears in the
lower left corner of the schematic, which is created when a netSet exists but a wire with
the name of the default value does not yet exist. The inverter string now looks like this:
Connects to
vtop, gnd!.
1 2 3
4 5
Connects to vdd!, gnd!. Connects to vtop, gnd!.
October 2005 107

Note: The instance names (e.g. I3) shown in the schematic above may be different than your
instance names depending on in which order you placed them. If you select the third inverter
symbol, for instance, and query its properites, the Instance Name shown in the Edit
Properties form is the same name that shows up in the netlist.
To summarize the various inherited connections used in this inverter chain schematic:
The first (left-most) inverter is still hardwired to the ground symbol, and its supply is
connected to the wire named vtop, so the inherited connections to GRND and POWR
are overridden.
The second inverter is still connected to gnd! from the inherited connection, and its
power supply is also connected to vtop.
The third inverter is connected to gnd! from the inherited connection. It is also
connected to vtop because the wire name vtop physically overrides netSet property
POWR=vdd!. Zoom in to see the vtop label if necessary.
netSet property
value is vdd!. 3 Evaluated net name
is vtop.
The fourth inverter has no POWR or GRND pins, so the POWR and GRND connection
defined inside the symbol views defaults to the net expression value of vdd! and gnd!,
respectively.
The fifth inverter is connected to gnd! from a netSet property, which matches the
default value of its net expression. It is also connected to vtop from a netSet property,
which overrides the net expression default value of vdd!
October 2005 108

Adding Another Power Supply

The vdd! supply is still needed to complete the schematic.
1. On the left side of the schematic, place another symbol view of the vdc power supply
from the analogLib library with dc voltage set to 1.8.
2. Add a wire stub to the positive terminal of the new vdc power supply and name it vdd!
3. Connect the negative terminal of the new vdc power supply as shown below.
4. Check and Save the inverter string schematic. With a vdd! wire defined, the floating wire
with the label vdd! disappears.
Since the output wire, out5, is not connected to anything, the system issues two
warnings about floating output. Ignore the warnings.
October 2005 109


1. Start the Analog Environment if it is not already running and load the state file (invtest1).
2. Netlist the design using Simulation Netlist Create.
3. Examine the netlist that is displayed, and notice
All the inverter GRND pins (third in the port list after the Instance Name) are
connected to node 0.
The inverter POWR pins (fourth in the port list) are connected to either vdd! or
vtop.
I5 (out4 out5 0 vtop) inv

I4 (out3 out4 0 vdd!) inv
V1 (in 0) vsource type=pulse val0=0.0 val1=1.8 period=10n delay=1n \
rise=200p fall=200p width=5n
V2 (vdd! 0) vsource dc=1.8 type=dc
V0 (vtop 0) vsource dc=2.2 type=dc
I2 (out out2 0 vtop) inv
I0 (in out 0 vtop) inv
On the third inverter,

the wire named vtop is the physical override of the netSet property value vdd!.
4. Choose a transient analysis of 50ns:
a. In the ADE form, choose AnalysesChoose.
b. In the Choosing Analyses form, type 50n for Stop Time and click OK.
5. Add outputs to be plotted for out2, out3, out4, and out5.
6. In the ADE form, save the state of the ADE setup for future use by choosing Session
Save State and typing in the Save As field, invtest2.
October 2005 110

7. Run the simulation.
Only out4 (and the input, in) should swing between 0 and 1.8 volts because it is
connected to vdd!. The other outputs should swing between 0 and 2.2 volts, because
they are connected to vtop.
October 2005 111

8. Split the waveforms by choosing Axis-Strips.

9. If necessary, scroll to make the waveforms for out4 and out5 visible.
10. Notice that out5 cycles to 2.2 volts for vtop and out4 cycles to 1.8 volts for vdd!.
11. Display all six waveforms simultaneously by doing the following:
a. Click on a wave form.
b. Choose Trace Edit.
c. Change Strip Chart Visible Rows to 6.
d. Click OK.
October 2005 112

Notice how the output signals in the WaveScan Window cycle to voltages based on the
use of inherited connection net expressions, netSet properties, and the physical
override of a wire name.
12. Keep the ADE window open, but close the WaveScan, netlist and simulation log file
windows.
October 2005 113

Making and Simulating a Ring Oscillator

Now you modify the inverter string to form a ring oscillator. When you simulate the ring
oscillator, you can see how power supplies have been used in the simulation by observing the
various output voltages.
A ring oscillator is composed of an odd-numbered string of inverters with the final output
connected to the input. The period of oscillation is twice the delay through the chain. To create
a ring oscillator from the tutorial invest schematic, follow these steps:
1. Delete the vpulse generator and its wire stubs, including the wire name in.
The left side of your invtest schematic should now look like this:
2. Connect the out5 output signal from the fifth inverter to the input of the first inverter.
October 2005 114

Your schematic should look like this:
3. Check and save your invtest schematic.

4. In the ADE window, set up an initial condition to help the oscillator get started:
a. Choose SimulationConvergence AidsInitial Condition.
b. Leave the Node Voltage set to 0 and keep the Select Initial Condition Set form
open.
The system prompts you to select initial condition voltages.
c. With the Select Initial Condition Set form open, move the cursor into the tutorial
invtest schematic window and select the out signal (wire named out).
October 2005 115

The system places a large marker ( ) over the out signal and inserts /out for
Node Name in the Select Initial Condition Set form.
d. In the Select Initial Condition Set form, click OK.

5. In the ADE window, create a new netlist for the invtest schematic design.
In the netlist that is displayed, notice the new line for the initial condition, ic out=0,
which appears immediately before the simulatorOptions line in the netlist:
ic out=0
simulatorOptions options
6. Run the simulation.
October 2005 116

The waves in the WaveScan window might be very dense, like this:
October 2005 117

7. Zoom in to make individual traces visible by using Zoom X-Zoom, or by drawing a box
around a small area of the traces with the right mouse button depressed. Keep
expanding until the traces show only a couple of cycles:
8. Split the waveforms by choosing Axis Strips.
October 2005 118

9. If only one wave form is visible, choose Trace Edit, set Strip Chart Visible Rows to
5, and click OK.
10. Select one of the traces, and use a Delta Cursor to measure the period of the trace
between successive rising edges. The example above has a period of approximately 280
ps.
11. Select Trace.
12. Choose Check Delta Cursor.
13. Choose SessionQuit and close all windows except for the Library Manager. Save the
state if you have not done so earlier.
October 2005 119

Creating an Inverter Layout

You now create a layout for the inverter cell you created earlier.
Generating Layout Components from a Schematic

When generating from source, the system uses the inherited connections you defined for the
tutorial inv schematic to produce the correct power and ground terminal names.
1. Open the tutorial inv schematic view.
2. From the inv schematic window, select ToolsDesign SynthesisLayout XL.
3. In the Startup Option form, keep the default of Create New and click OK.
4. In the Create New File form, accept the default values and click OK.
The system opens a new layout window for the inverter.

5. From the tutorial inv layout window, choose Design GenFromSource.
October 2005 120

6. In the Layout Generation Options form, in the Layout Generation section, for
Generate, turn on I/O Pins, Instances, and Boundary.
7. In the Layout Generation Options form, to set the layer, width, and height for all four pins,
follow these steps.
Note: The top part of the I/O Pins section, where the Apply button is located, lets you
set values for all pins at once. The bottom part of the I/O Pins section, where the Update
button is located, lets you select one or more pins and update the values for the selected
pins only.
a. In the top of the I/O Pins section, make sure that the Layer/Master field is set to
Metal1 dg; if not, set it and click the I/O Pins Apply button.
Click on Apply in the I/O Pins section.
Notice the pin terminal names in the Name field (A, GRND, POWR, and Y): they are
the pin terminal names that you defined when you created the inverter schematic.
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Clicking on Apply changed the Layer/Master values for all pins to Metal1 drawing.
b. To change the width and height for only the GRND and POWR pins:
In the I/O Pins section, in the Name field, click on the GRND line.
To add the POWR pin the selected set, Shift-click on the POWR line.
Under the Update button, which is below the selected pins, in the Width and
Height fields, type the following:
For Width, type 3.96.
For Height, type 1.08.
Click on the Update button.
Click the Update button.

The width and height for GRND and POWR change from 0.3 to 3.96 and 1.08.
October 2005 122

8. In the Layout Generation Options form, in the Boundary section, create the place and
route boundary for the inverter cell by following these steps:
The Boundary section is located near the bottom of the Layout Generation Options form.
a. For the Layer field, choose prBndry dg.
b. To define the width and height of the boundary,

Change the top cyclic field from Utilization (%) to Boundary Width and type
in the value 3.96.
Change the bottom cyclic field from Aspect Ratio (W/H) to Boundary Height
and type in the value 7.92.
9. In the Layout Generation Options form, click OK.
October 2005 123

The Virtuoso XL layout editor places the components of inverter layout and pins in the
lower-right quadrant, and the boundary in the upper-right quadrant, at coordinates 0:0.
GRND and POWR pins
10. To check the properties of the POWR pin,
a. Click on the POWR pin and choose EditProperties.
b. In the Edit Rectangle Properties form, click Connectivity.
October 2005 124

c. Notice that the POWR pin has inherited the net expression from the schematic pin;
it is connected to the net vdd!.
d. Verify the GRND pin in the same way.
e. Click Cancel in the Edit Rectangle Properties form to return to the layout.
Although the net name ends with an exclamation point (!), in the Virtuoso Layout Editor,
the ! does not imply a global signal name. In this case, the signal is completely local to
this level of hierarchy, and connects only to the terminal and to the appropriate instance
terminals. For more information about the use of ! to indicate a global signal, see How
Tools Interpret Net Names Ending with ! on page 15.
Displaying Incomplete Nets

It can be useful to display the connections that remain unresolved. You can display them with
the Show Incomplete Nets command.
1. In the inv layout window, choose ConnectivityShow Incomplete Nets.
The following nets are listed as incomplete: A, Y, gnd!, and vdd!.
October 2005 125

2. In the Show Incomplete Nets form, click Select All and click OK.
3. As connections are completed, the flight lines (net connection lines) disappear.
Placing a Layout Template Instance

The layout of the power and ground rails, bulk connections, nwell, and prboundary (which
defines the extent of the cell) have already been prepared for you in the tutorial library in the
template cellview called layout-tmpl.
1. In the inv layout window, choose CreateInstance.
If you get warning about recursive instance, ignore it because you change the name.
2. In the Create Instance form, set the following:
Library: tutorial
Cell: inv
View: layout-tmpl
3. Force this instance to line up with the existing prBoundary by typing 0:0 in the Command
Interpreter Window (CIW) input line.
October 2005 126

The layout should now look like this, with the template on top, and the generated parts
underneath:
4. To see the entire cellview, in the inv layout window, choose WindowFit All, or press
the f key.
October 2005 127

Placing Generated Components into the Layout Template

Use the following illustration and these steps. It as a guide for placing the pmosInh, nmosInh,
and pins into the inverter layout template.
1. Change the editing snap mode to any angle,
a. Choose OptionsDisplay.
October 2005 128

b. In the Display Options form, for Snap Modes, set Edit to AnyAngle
Click on the Update button.
c. Click OK.
2. Select the pmosInh (the larger one) device and then the nmosInh device and move
each into place as shown in the figure above so that the respective mosfet source pin
(right side metal1 rectangle) abuts and lines up with the metal tab from the power rail (for
the pmosInh) or ground rail (for the nmosInh).
3. Select each pin and its label and move it into position in the layout template, as follows:
a. Overlay the A pin over the metal square on the left side of the template, and the Y
pin on the metal square on the right side.
b. Overlay the POWR pin on the top metal rail and the GRND pin on the bottom metal
rail.
Completing the Layout or Using the Provided Layout

The remaining steps are to connect both gates to the input pin A, and both drains to the output
pin Y using metal1 wires and a poly path with metal1-to-poly contact. Either complete the
layout yourself or use the completed layout (layout-rt) from the tutorial library.
Do one of the following:
a. If you want to connect up the devices yourself, connect both drains to the output pin
Y using metal1 paths. Connect both poly gates to each other with a poly path, and
to the input pin A with a metal1 path through the use of a metal1-to-poly contact.
When connecting the poly gates, use the following poly contact:
Library: inhConnLib
Cell: M1_POLY1
View: symbolic
October 2005 129

b. To use the tutorial inv layout-rt view which is a completed layout, do the following,
Open the tutorial inv layout-rt view for read-only.
Choose DesignSave As and save the layout-rt view as just layout.
When a dialog box asks if you want to overwrite the inv layout view, click Yes.
Close the inv layout-rt view.
Verifying the Inverter Layout

You now verify the layout for the inverter cell. DRC checks for violation of any process design
rules. LVS compares the layout against the schematic to see if they match. RCX extracts
parasitic resistors and capacitors that derive from the layout.
Note: The tutorial RCX numbers are based on using the routed view (tutorial inv layout-rt).
October 2005 130

Running Assura DRC for the inv layout

1. Use your own routed inv layout view, or open the tutorial inv layout-rt view as read-only.
2. In the inv layout window, choose AssuraRun DRC. If the layout window is too narrow,
widen the window until the Assura menu appears on the right-hand side.
3. To set values for the fields in the Run Assura DRC form, load the inv state file provided
with the tutorial before running Assura DRC:
a. At the top of the Run Assura DRC form, click Load State.
b. In the Assura DRC State form, click inv and then click OK.
c. If you are using the provided layout-rt view, change the View name to layout-rt.
October 2005 131

The Run Assura DRC form should look like this:
Load State button is here.
4. In the Run Assura DRC form, click OK.
a. If a dialog box appears, stating that DRC data already exists and asking if you want
to overwrite it, click OK.
b. If a dialog box appears, stating that a new job cannot be started while a run is active,
click Yes to stop viewing the earlier run.
A progress window appears, briefly.
5. If the DRC run completes successfully,
A dialog box appears, stating that run inv has completed successfully.
a. In the dialog box, click Yes to see the results.
b. When a dialog box appears stating no DRC errors found, click Close.
6. If there are errors in the DRC run, you can use choose VerifyMarkersExplain to
assist you in correcting violations. The errors must be fixed before continuing on. Zoom
in very closely to see small overlap errors if necessary.
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Running Assura LVS to compare the inv layout with the inv schematic
1. In the layout window, choose AssuraRun LVS.
Note: If the Assura menu choice, Run RCX, is grayed out, you must first run Assura
Open Run to open a previous run, or run DRC again.
2. Load the inv state file before running Assura LVS:
a. In the Run Assura LVS form, click Load State.
b. In the Assura LVS State form, click inv and then click OK.
c. If you are using the layout-rt view, change the Layout View name to layout-rt.
3. In the Run Assura LVS form, click OK.

4. If a dialog box appears, stating that LVS data already exists and asks if you want to
overwrite it, click OK.
The inverter should pass both DRC and LVS without errors indicating that it meets the
process design rules and that the layout and schematic match.
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5. When a dialog box appears, stating that the schematic and layout match, click Yes to
close the project and review the results.
The LVS Debug window appears.
6. In the LVS Debug window, choose FileQuit Debug Environment.
7. If there are error markers, examine them by choosing VerifyMarkersExplain.
Running Assura RCX for inv

Assura requires that you have a clean LVS run before allowing you to run RCX. You now
create an extracted SPICE netlist which includes all the parasitic resistors and capacitors
deriving from the layout. This is used to create a .lib file which can be used in digital
simulation.
1. To create an extracted view, in the layout window, choose AssuraRun RCX.
2. Load the inv state file before running Assura RCX:
a. In the Assura Parasitic Extraction Run form, click Load State.
b. In the Assura RCX State form, click inv and then OK.
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3. In the Assura Parasitic Extraction Run form, click Extraction and notice that Cap
Extraction Mode is set to Decoupled and Ref Node is set to GRND.
Click on Extraction.
These values were set by loading the inv state file.

4. In the Assura Parasitic Extraction Run form, click OK.
5. When a dialog box appears stating that RCX has completed successfully, click Close.
RCX created a SPICE netlist, containing an extracted netlist with parasitics, in the
inv.sp file. Copy this file into the LibGen library for use in the Running the Library
Characterization for inv on page 146 of this tutorial.
6. In the terminal window where you started icfb, copy the inv.sp file to the LibGen
directory with the following command:
cp ./av/inv/inv.sp ./LibGen
Generating an Abstract View for inv

Create an abstract view to demonstrate inherited connections and verify the abstract view
with the Encounter place and route tools.
1. Open the tutorial inv layout view if it is not open.
2. In the inverter layout window, choose ToolsAbstract Editor.
The Abstract menu appears on the window menu bar.
3. Choose AbstractCreate Abstract.
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The Create Advanced Abstract form appears.
4. Accept the default to generate from Cellview by clicking on OK.

Wait for the Abstract tutorial window to open. The Percent Complete window appears
briefly as the library opens.
5. Move the inv cell from the Block Bin to the Core Bin by following these steps:
a. With the inv cell selected, choose Cells Move.
b. In the Move Selected Cells form, click Core, then click OK.
October 2005 136

6. In the Abstract tutorial window, click Core for the Bin field. Note that Layout and Logical
have green check marks indicating those steps are completed.
Creating Pins for the inv Abstract View

You run the abstract generator on the inverter cell.
1. To import pin information, in the Abstract tutorial form,
a. Click inv for Cell.
b. Inform the abstract generator of the existing pins by choosing Flow Pins.
The Running step Pins for the selected cell(s) form appears.
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2. In the Running step Pins for the selected cell(s) form,
a. For Power pin names (regular expressions), replace any existing expression
with POWR vdd.
b. For Ground pin names (regular expressions), replace any existing expression
with GRND gnd.
3. At the bottom of the Running step Pins for the selected cell(s) form, click Run.
4. If an exclamation mark (!) appears in the Pins column of the Abstract tutorial form,
read the warnings in the Log section.
Ignore the four warnings about the prBoundary not enclosing all cell view geometry, net
expressions already existing, and terminal GRND and POWR having different types.
October 2005 138

Creating an inv Extracted View

1. In the Abstract tutorial form, create an extracted view by choosing Flow Extract.
2. At the bottom of the Running step Extract for the selected cell(s) form, click Run.
After the extraction process completes, you should see a check mark for inv in the
Extract column on the Abstract tutorial form.
Creating an inv Abstract View

1. In Abstract tutorial form, create the abstract view by choosing FlowAbstract.
October 2005 139

2. Click the Site tab, and for the Site name field, set the blank cyclic field to COREinh.
3. At the bottom of the Running step Abstract for the selected cell(s) form, click Run.
4. In Abstract tutorial form, look in the Abstract column for inv.
If there is a check mark, the abstract view contains no errors. If there is an exclamation
mark (!), read the warnings in the Log section of the form.
5. To see the newly-created abstract view in the Library Manager, refresh the list of views
by choosing ViewRefresh. Open the abstract view of the inv cell. This view contains
the metal layers (for avoidance in routers) plus the pin connectivity (for connection in
routers).
6. Close the tutorial inv abstract view.
October 2005 140

Verifying the inv Abstract

The abstract view can be verified by using the Encounter place and route tool from the
Abstract Editor.
1. In Abstract tutorial form, choose FlowVerify to verify the abstract.
2. At the top of the Running step Verify for the selected cell(s) form, click the Target
tab.
On the Target tab, set the cyclic field to Encounter.
3. At the bottom of the form, click Run to start Encounter to perform the verification.
It might take a few minutes for the abstract step to complete.
Ignore the warning about a locked process as well as the four warnings about the
prBoundary not enclosing all cell view geometry, net expressions already existing, and
terminal GRND and POWR having different types.
If there is an error in the verification step, look in the following directory:
./.abstract/verify
This directory contains all the files and the commands that were used to verify the test
structure in Encounter.
Creating LEF for inv (Optional)

To see the inverter as LEF, perform these steps:
October 2005 141

1. In the Abstract tutorial form, choose File Export LEF to create LEF.
2. In the Export LEF form, Change LEF Filename to inv.lef and click OK.
3. In the Abstract tutorial form, choose FileExit, and click Yes in the Exit dialog box.
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4. In the tutorial directory, look at the inv.lef file with an editor. MACRO inv defines the
pin dimensions and location, metal layer, and direction.
MACRO inv
CLASS CORE ;
FOREIGN inv 0 0 ;
ORIGIN 0.0000 0.0000 ;
SIZE 3.96 BY 7.92 ;
SYMMETRY X Y ;
SITE COREinh ;
PIN A
DIRECTION INPUT ;
PORT
LAYER Metal1 ;
RECT 1.7600 2.8200 2.1600 3.2200 ;
RECT 0.1800 2.8200 2.1600 3.1200 ;
END
END A
PIN Y
DIRECTION OUTPUT ;
PORT
LAYER Metal1 ;
RECT 2.4600 2.8200 3.7800 3.1200 ;
RECT 2.3600 4.3550 2.7600 6.1750 ;
RECT 2.4600 1.4600 2.7600 6.1750 ;
RECT 2.3600 1.4600 2.7600 2.1100 ;
END
END Y
PIN POWR
DIRECTION INOUT ;
PORT
LAYER Metal1 ;
RECT 0.00 7.38 3.96 8.46 ;
RECT 1.28 7.08 3.06 8.46 ;
RECT 1.58 4.36 1.98 8.46 ;
END
END POWR
PIN GRND
DIRECTION INOUT ;
PORT
LAYER Metal1 ;
RECT 0.00 -0.54 3.96 0.54 ;
RECT 1.57 -0.54 2.77 0.85 ;
RECT 1.58 -0.54 1.98 2.11 ;
END
END GRND
END inv
Exit the Cadence Software

Close all Cadence sessions.
October 2005 143

Library Characterization for inv

To assure the accurate simulation of a standard digital cell by a digital simulator, characterize
the cell by performing worst-case analog simulations on its netlist, which contains parasitic
components from the extracted layout. To obtain the best, worst, and typical delays for each
signal path (or group of paths) through a cell, you use high and low voltages, high and low
temperatures, and fast and slow process information.
Setting Up the Environment for Library Characterization

Before running SignalStorm, quit any related, active processes and then start the
SignalStorm daemons in a specific sequence.
Quitting Related Processes
To check for and quit all active ipsd and ipsc processes,
1. In a terminal window, check whether such processes are running by typing
ps -ef | grep ips
2. If ipsd or ipsc processes are running, type the following command for each process:
kill processID
3. Recheck for ips processes by typing:

ps -ef | grep ips
Starting the SignalStorm Daemons

1. Change to the top-level directory containing the tutorial files.
2. In the terminal window that lists the tutorial files, verify that you have access to the
necessary executables by typing each statement below:
which ipsd
which ipsc
3. If you do not have access to these executables, check the path or environment variable
that points to the path, or see your system administrator.
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4. To start the daemons that run the SignalStorm tools, type each of the following
commands, in sequence:
a. Type ipsd.
Text appears in the terminal window, showing the SignalStorm version number and
the Cadence copyright statement.
b. At your machine prompt, type ipsc.
c. After you see the message that service is starting, press Enter.
d. When you are returned to the prompt, type
ipsc -n spectre
Watch for the availability of the Spectre Circuit Simulator, which depends on
whether you have access to a license.
Note: You should see a message stating how many licenses are available for the
Spectre Circuit Simulator now. If you do not get a license, see your system
administrator.
e. After you see the message stating how many spectre licenses are available, press
Return.
5. To verify that an ipsc process is running for the Spectre Circuit Simulator, type ipsstat.
October 2005 145

The results should look similar to this, with your host system name replacing the one
shown below:
IPSC INFORMATION:
ipsc[0]: HOST: your_host_name PID: 18214 USER: user1 GROUP: your_group
TAG: 0 MAX NUM: 800 MAX LOAD: 2.000
IPSD INFORMATION(CONNECTED):
HOST: your_host_name STATUS: active #CPU: 1 LOAD: 0.005
USER INFORMATION:
NO USER ATTACHED
ipsc[1]: NOT FOUND
ipsc[2]: NOT FOUND
TAG: 0 MAX NUM: 800 MAX LOAD: 2.000 LICENSE: spectre
USER INFORMATION:
NO USER ATTACHED
ipsc[4]: NOT FOUND
IPSD INFORMATION(ALL IN THIS NETWORK):
HOST: your_host_name #CPU: 1 LOAD: 0.045
In the IPSC information, verify that the following lines give you a license for spectre:
If you see NOT FOUND messages for servers 1, 2, and 4, ignore them. You are now set up
to run library characterization.
Running the Library Characterization for inv

Normally, you would run library characterization on a whole library, but for the purpose of this
tutorial, you run it on a single cell: the inverter that contains inherited connections. The library
characterization process creates the inhConnLib.lib file, which is a characterization file
that can be used by other simulators, such as a digital simulator.
1. Change directories to the LibGen directory and look at the contents:
mos1.scs is the model file that includes the nmos1 and pmos1 Spectre models
from the inhConnLib library.
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corners.scs is a listing of the parameters the models use for the NOM, SLOW,
and FAST process corners.
setupFile.txt defines the supply, threshold voltage, load, and temperature to
be applied for the typical, best-case, and worst-case simulations. The threshold
voltages were derived from information in the models.
The batch.cmd file is the sequence of commands needed to generate the .lib
file by running simulations on the extracted netlist.
2. To run SignalStorm library characterization using the batch file, in the LibGen directory,
type
slc -S batch.cmd
The system displays text that shows it is running multiple simulations on the inverter,
using different models, temperatures, voltages, and load capacitances. The system then
displays the dswave window.
3. To expand the data so that you can see it more clearly, in the dswave window,
a. Choose ZoomZoomX.
b. Place the vertical line cursor immediately before the start of the traces (t=0) and click
left.
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c. Move the vertical line cursor just after the congested portion of the traces stops
(about 5-6N) and click left. The traces zoom to fill the graph.
The plot shows

In the upper graph, the voltage output transition from low to high
In the lower graph, the current drawn while the inverter is switching.
4. Examine the waveform display for the simulated transitions at the various corners.
5. In the dswave window, choose FileQuit.
6. Examine the results in the following files in the LibGen directory:
a. For a summary of the results of the simulations, see the char.rpt file
b. For the output of the characterization, see the inhConnLib.lib file
When running one of your own libraries, you would see an entire library of cells characterized
and listed.
October 2005 148

Generating a Verilog Model with Characterized Delays for inv
If you want a Verilog model with delays for the inv design, you can create one from the results
of the Library Characterization.
1. To create a Verilog file, in the LibGen directory, type
alf2veri -alf INV.alf -verilog inv.v
The system displays text about successfully reading and converting CELL INV.
2. Look at the inv.v file with a text editor. (Optional)
You have completed this portion of the Virtuoso Inherited Connections Tutorial, and have
seen how inherited connections are handled through schematic entry, layout, verification,
abstract generation, and library characterization.
October 2005 149

October 2005 150

6
Using Explicit Pins vs. Implicit Terminals
This chapter illustrates the reasons you should define explicit inherited connections when
your data is to be used by other tools in a design flow. When you are creating a block (or the
components of a block) that are to be shared, distributed, or used by other tools, Cadence
recommends that the interface for that block be fully specified. This requires defining all
inherited connections as explicit ports rather than as implicit terminals.
To define an explicit inherited connection, create a pin for every net expression. Associating
a net expression with a pin makes the inherited connection explicit; associating a net
expression with a wire leaves the inherited connection implicit. As seen in the last chapter,
even though a schematic has explicit pins for inherited connections, the matching symbol
view need not have the same pins.
Tools that compare a layout to a schematic, such as Layout Versus Schematic (LVS), do not
find matching pins in the schematic unless they are defined in the schematic with explicit pins.
Additionally, for implicit inherited connections, the Virtuoso Layout Accelerator (Virtuoso XL)
resolves conflicts between net expressions with different property names having the same
default net name by merging them together, which might not be the original intention of the
designer.

Showing Conflict in the Resolution of Implicit Inherited Connections on page 152
Generating a Layout from a Schematic on page 153
Placing the Pins on page 156
Checking Connectivity Flight Lines on page 158
Routing with the Virtuoso Chip Assembly Router on page 159
Adding a Substrate Contact on page 164
Running Assura DRC on the TB_dividers_top Layout on page 165
Running Assura LVS on the dividers_top Layout on page 166
Section Summary on page 167
October 2005 151

Adding Inherited Connections to a Schematic on page 169

Adding Implicit Inherited Connections (Implicit Terminals) to a Schematic on
page 169
Adding Explicit Inherited Connections (Explicit Pins) to Schematics on page 172
Running a Test Simulation on page 178
Verifying MSFF and Generating Library Files on page 181
Running Assura DRC for the MSFF Layout on page 182
Running Assura LVS for the MSFF Layout on page 183
Running Assura RCX for the MSFF Layout on page 184
Generating an Abstract View for MSFF on page 187
Creating Pins for the MSFF Abstract View on page 188
Creating an MSFF Extracted View on page 190
Creating an MSFF Abstract View on page 190
Verifying the MSFF Abstract on page 191
Creating LEF for the Library (Optional) on page 192
Exit the Cadence Software on page 194
Library Characterization on page 195
Setting Up the Environment for Library Characterization on page 196
Running Library Characterization on page 197
Generating a Verilog Model with Characterized Delays for the Library on page 200
Creating HTML Data Sheets for the Library on page 200
Showing Conflict in the Resolution of Implicit Inherited

Connections
The TB_dividers design was created with implicit inherited connections in Chapter 3, Basic
Concepts of Inherited Connections in a Hierarchy. Although the implicit inherited connections
work locally within the TB_dividers hierarchy itself, they may be processed differently by other
tools in the design flow. For example, when Virtuoso XL evaluates net expressions with
October 2005 152

different property names but the same default net name Virtuoso XL resolves them to the net
name. This could result in an unwanted short later in a higher-level assembly if the different
net expressions in the higher-level schematic are overridden with different net names. This
section shows you how to make inherited connections work correctly in Virutoso XL using
explicit pins for any cell that one might want to instantiate more than once.
Generating a Layout from a Schematic

1. Start the Cadence software if it is not already running.
icfb &
2. In the CIW, choose Tools Library Manager.

3. In the tutorial library, open the dividers_top schematic.
4. In the dividers_top schematic window, choose Tools Design Synthesis Layout

XL.
5. In the Startup Option dialog box, turn on Create New and click OK.
October 2005 153

6. In the Create New File form, verify that the Library Name is tutorial, the Cell Name is
dividers_top, the View Name is layout and the Tool is Virtuoso. Click OK to open the
TB_dividers layout window.
7. Use Virtuoso XL to generate a layout from the schematic by doing the following:
a. In the dividers_top layout window, choose Design Gen from Source.
b. In the Layout Generation Options form, for Generate, turn on Boundary.
c. Click OK.
The Resolve Inherited Connection Conflict form appears.
The form contains a cyclic field to let you choose which surviving net expression to
put on the POWR4! pin. The choices are [hSupA:%:POWR4!] and
[@hSupB:%:POWR4!] from the original two net expressions. However, by choosing
either value, Virtuoso XL merges both net expressions because their default net
values are the same (POWR4!).
Whatever value you choose, the result could be incorrect because for implicit
inherited connections like this, Virtuoso XL merges the two different nets into a
single net and puts one net expression on the connecting pin. For example, if you
choose [@hSupA:%:POWR4!] and define the netSet property hSupA=POWR6!,
then the other net, which has the net expression [@hSupB:%:POWR4!], is also
connected to POWR6!
October 2005 154

d. In the Resolve Inherited Connection Conflicts form, click OK.

8. Move the components into the boundary area by choosing Edit Place As In
Schematic in the dividers_top layout window. This arranges the parts similar to how they
appear in the schematic, and attempts to fit as many as possible within the prBoundary
box.
9. In the Virtuoso XL dialog box that states the command moves all components, click Yes
to continue. Use the f bindkey to zoom to view all the components and pins.
10. Stretch the boundary to include all parts that are outside the prBoundary by choosing
Edit Stretch, selecting the right edge of the boundary, and stretching it past the right-
most mosfet.
October 2005 155

11. Stretch the top boundary in the same way so that all the mosfets are within the
prBoundary.
Placing the Pins

Place the pins by doing the following in the layout window:
1. Choose Place Pin Placement.
2. Move the global pins to the left cell boundary by doing the following:
October 2005 156

a. Highlight all the global pins in the list by selecting them with the mouse while holding
down the shift key. (These global signals are POWR1!, POWR3!, POWR4!, gnd!,
vcc!, and vdd!.)
b. Change the Edge selector from Any to Left and click Apply.
Choose Left for Edge, then

click Apply.
The selected global pins move to the cell boundary.
c. Move the voutN pins to the top cell boundary by selecting them, changing the edge
to Top, and clicking Apply once more.
October 2005 157

d. The layout should now look similar to this:
e. Click Close in the Pin Placement window.
Checking Connectivity Flight Lines

Display flight lines between terminals by doing the following:
1. Choose Connectivity Show Incomplete Nets.
October 2005 158

2. In the Show Incomplete Nets form, select all net names and click OK.
3. Select the global power pin POWR4! and examine its connectivity property (q bindkey).
Note that the net name is no longer a property, but has been resolved to POWR4! for two
resistors from different instances which originally had two different property names,
hSupA and hSupB.
Note: As an option for a more compact layout, you can move the resistors next to the
pins to which they need to be connected.
Routing with the Virtuoso Chip Assembly Router

Use VCAR to route the dividers_top design, which then connects all the resistor terminals to
the proper power and output pins.
October 2005 159

Export TB_dividers_top to the Router
Export the design to the router by doing the following:

1. In the layout window, choose Routing Export to Router.
The tutorial provides the necessary icc.rules file to instruct the router what layers can be
used for routing, and a route.do file which controls the routing process.
2. In the Export to Directory field, type dividers_top at the end of the path.
Type dividers_top here.
3. In the Export to Router form, click OK.

4. In the Export from DFII dialog box, click OK to create the new directory.
October 2005 160

In a few moments the Virtuoso Chip Assembly Router window opens. Your route looks
similar to this:
5. When the routing completes, notice that POWR4! is connected to the terminal on two
different resistors, seen in the Show Incomplete Nets step above.
6. In the router window, choose File Write Session.
October 2005 161

7. In the Write Session form:
a. Turn on these fields: Force Include Placement, Include Global Paths, and
Merge Straight Paths.
b. Click OK.
8. If a dialog box appears stating that same net checking is turned off, click Yes to continue
to write out the result.
9. Exit the router and return to Virtuoso XL by doing the following:
a. In the router window, choose File Quit.
b. In the Quit dialog box, turn on Delete Did File.
c. Click Quit.
Import Routing Back to the TB_dividers_top Layout
Depending on your setup, the routed layout is automatically imported back into Virtuoso XL.
Redraw the layout to display the routing if necessary.
October 2005 162

1. If the layout does not automatically import back into Virtuoso XL, do the following:
a. In the dividers_top layout window, choose Routing Import from Router.

The Import from Router form shows the path to the dividers_top.ses file.
b. Click OK. Your Virtuoso XL might look a little different than the example below.
Resistor power
connection
Resistor power
connection
POWR4!
October 2005 163

Adding a Substrate Contact

To successfully complete the verification process, the substrate needs to connect to ground,
therefore, add a contact and connect it to gnd!.
Add an M1-PSUB contact to the gnd! wire in the layout by doing the following:
1. Choose Create Contact and select M1_PSUB.
2. Do one of the followoing
a. Click in the dividers_top layout window to place the contact on the gnd! wire, away
from other objects
or
b. Place the M1_PSUB contact in an open area of the substrate and add a metal1 path
to the gnd! wire where it is also metal1 (blue in color).
3. Check and Save the layout.
Click to place
M1_PSUB on gnd!.
October 2005 164

Running Assura DRC on the TB_dividers_top Layout

1. Verify the path to the Assura technology file by choosing Assura Technology.
2. If the path is not ./assura_tech.lib, add the correct path or browse to it using the
file selector button (...), then click OK.
3. Run the Assura Design Rules Checker by choosing Assura Run DRC.
4. Load the state file, dividers_top.
5. For Technology, verify inhConnLib is selected.
Note: The Run Name is automatically filled in by Assura.
6. Click OK to start the DRC process.

7. If a Save Cellviews dialog box appears, click OK to save all cells.
A Progress form appears.
October 2005 165

8. When the DRC run dialog appears announcing it completed successfully, click Yes to
view the results.
There should be no DRC errors reported.
Running Assura LVS on the dividers_top Layout

1. Run Layout Versus Schematic by choosing Assura Run LVS.
2. Load the state file, dividers_top.
3. Verify that the Technology is inhConnLib. The completed form should look like this:
a. Click OK to start the LVS verification process.
October 2005 166

A Progress form appears. When the LVS run completes, a report appears stating that the
schematic and layout match, as shown below:
4. In the dialog box, click Yes even though there are no errors.
5. In the No DRC errors found dialog box, click Close.
The LVS Debug form appears. Select the first line in the list to fill out the summary
section. Since there are no errors, the Summary section remains blank.
Note: If there are mismatch errors between the schematic and layout (which there
should not be) the Summary section shows the categories of mismatches, such as wiring
or devices. Selecting an error category, and clicking on Open Tool opens debug forms
that allow you to identify the particular errors found during LVS.
6. Close the dividers_top layout and schematic windows.
Section Summary
In this section, you have seen one of the complications that can occur when using implicit
inherited connections. When Virtuoso XL generates the pins in the layout, it resolves the
inherited connections so that hSupA and hSupB are both connected to POWR4! This would
October 2005 167

be fine as long as that was the desired connection for any and all instantiations. A better
approach would have been to use explicit inherited connects, where a separate pin is added
to allow each to be connected externally as desired.
October 2005 168

Adding Inherited Connections to a Schematic

The following example of a master-slave flip-flop shows that implicit terminals can be used
inside a top-level circuit that has explicit pins to define the interconnects to the outside world.
At this fully-defined top level, the circuit is capable of verification through Layout Versus
Schematic (LVS). You can use implicit terminals when embedding a subcircuit inside a top-
level circuit that is capable of being verified through LVS.
The master-slave flip-flop uses implicit terminals on subcircuit T-latches and explicit terminals
at the top level where the T-latches are instantiated. In this example, you define both implicit
and explicit inherited connections. The explicit inherited connections ensure that a
comparison of the schematic to the layout using LVS is unambiguous.
The master-slave flip-flop uses an input multiplexer, followed by two identical latch blocks with
transmission gates (T-gates) for switching between the input signal and the output signal on
each clock pulse.
Adding Implicit Inherited Connections (Implicit Terminals) to a Schematic

Implicit inherited connections are deferred by attaching net expressions directly to the wires
in the design. In the following example, you define implicit terminals by attaching net
expressions to the power and ground signal wires of the LATCH element used to build the
MSFF cell.
October 2005 169

1. From the tutorial library, open the MSFF_Latch schematic.
2. Add net expressions for the power and ground wires as follows:
a. Choose Add Net Expression.
The Add Net Expression form appears.
b. For the Property Name field, type POWR.
October 2005 170

c. For the Default Net Name field, type vdd!.
d. Add the net expression for power by clicking on the top wire in the MSFF_Latch
schematic window.
Click on this wire.
e. Repeat the steps above to add a net expression with the property name GRND and
a default net name of gnd! to the bottom wire.
Click on this wire.
October 2005 171

f. In the Add Net Expression form, click Cancel.

3. Check and save the MSFF_Latch schematic.
The MSFF_Latch schematic should look similar to the following:
4. Close the MSFF_Latch schematic window.
Adding Explicit Inherited Connections (Explicit Pins) to Schematics

You define explicit inherited connections, as explicit pins, for POWR and GRND. Because
they are explicit, the results of comparing the schematic to the layout with LVS are accurate.
October 2005 172

1. From the tutorial library, open the MSFF schematic.
Replace the three place-holder boxes with instances of the inv symbol2 view that you
created earlier, in Chapter 5, Creating an Inverter Symbol without Power Pins. You
created the symbol2 view without power and ground pins; it uses inherited connections
to convey power and ground to the circuit.
2. Replace the three boxes notated with Add inv symbol2 here with the inverter symbol2
view created in Chapter 5, Inherited Connections in an Inverter, as follows:
a. Delete the three place-holder boxes and their text.
a. Choose Add Instance (or type i) to open the Add Instance form.
b. For the Library, Cell Name, and View Name fields, type the following values:
Field Name Value

Library tutorial
Cell Name inv
View Name symbol2
c. Click to place three instances of inv symbol2, replacing the place-holder boxes.
d. Click Cancel.
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3. Reconnect the wires to the inv instances as needed by stretching each wire slightly and
making sure that the flight lines show connection between the wires and the pins.
4. Check and save your design to make sure you have not introduced any errors.
Ignore the warning about a floating output for pin Q.
Displaying Property Names for Available Net Expressions
Query a selected instance for all net expression property names that have not yet been
overridden by a netSet property.
1. In the MSFF schematic window, click an inv instance.
Click on an inv instance.
2. Select Edit Net Expression Available Properties, which opens the Net Expression
Available Property Names form.
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For the inv instance, the properties GRND and POWR have not been overwritten (reset),
and therefore still evaluate to their default net names of gnd! and vdd!. That is why they
are referred to as available.
3. Click Cancel.
4. Deselect the instance.
Adding Power and Ground Pins with Net Expressions
Define explicit power pins in the schematic to match the physical pins that Virtuoso XL creates
in the layout so that LVS declares a match for pins and nets between the schematic and the
layout.
Add pins to the schematic for POWR and GRND and define net expressions for each of them:
1. Choose Add Pin.
2. For Pin Names, type POWR GRND.
3. For Direction, choose inputOutput.
4. For Attach Net Expression, click Yes.

5. For Property Name, type POWR.
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6. For Default Net Name, type vdd!.
7. Place the POWR pin in the MSFF schematic by clicking above the CK pin.
Click here for POWR.
8. Repeat the steps above for the GRND pin, using gnd! as the default.
9. Place the GRND pin in the MSFF schematic by clicking below the SE pin.
Click here for GRND.
10. In the Add Pin form, click Cancel.

You do not need to wire the pins; they are used later to perform a Layout Versus
Schematic comparison of the MSFF layout.
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11. The MSFF schematic should now look similar to the following:
12. Check and Save the schematic. Notice that there are Warnings for the POWR and GRND
pins that these inherited terminals are not found in the MSFF symbol. This is addressed
in the next section.
Setting Up the Cross-View Checker
Because you added POWR and GRND to the MSFF schematic, set up the cross-view
checker so that it ignores the POWR and GRND pins in the MSFF schematic, as the MSFF
symbol view does not have POWR and GRND pins. If you omit this step, when you check and
save, you see the warning boxes over the POWR and GRND pins that you saw in the last
section.
1. Change the cross-view checking options for inherited connections by doing the following:
a. In the Schematic Editor, choose Check Options.
b. In the Cross View Check Options section of the Schematic Check Options form:
Turn on the Match Inherited Terminals field.
For the Ignore Terminals field, turn on specify and type in the following
terminal names:
POWR GRND
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c. In the For Views field, type symbol.
d. Click OK.
2. Check and save the MSFF schematic.
The schematic check should complete without warnings about POWR and GRND
because you specified that the cross-view checker should ignore POWR and GRND for
the MSFF symbol view.
3. Close the MSFF schematic window.
Running a Test Simulation

Run a simulation on the MSFF schematic to make sure the inherited connections connect the
power correctly and that you completed the schematic successfully.
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1. From the tutorial library, open the MS_test schematic.
2. In the MS_test schematic window, start the Analog Design Environment (ADE) by
choosing Tools Analog Environment.
3. In the ADE form, verify that the model library file is set to inhConnLib.scs:
a. Choose Setup Model Libraries.
The end of the path should point to: /inhConnLib.scs and Section should be
NN.
b. In the Model Libraries form, click OK.

4. In the ADE form, choose Analyses Choose.
5. In the Choosing Analyses form,
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a. For Stop Time, type 100n.
b. Click OK.
6. In the ADE form, choose the output signals for plotting:
a. Choose Outputs To Be Plotted Select on Schematic.
b. In the MS_test schematic, click the wires named in, clk, Q, and QN, then press
Esc.
The ADE form should look like this:
Save the Analog Design Environment session state now, you may want to reload it later.
7. In the ADE form, save the state of the ADE setup for future use:
a. Choose Session Save State.
b. In the Saving State form,

In the Save As field, type: MS_test
Click OK.
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8. Netlist and run a simulation by choosing Simulation Netlist and Run.

After a few moments, a WaveScan Window appears with results similar to those shown
below.
9. Split the waveforms by choosing Axis Strips.
10. Close the simulation output and WaveScan windows.

12. Close the MS_test schematic window.
Verifying MSFF and Generating Library Files

The first step in generating library files is to verify the MSFF layout using Assura Design Rule
Checker (DRC) and LVS. Then RCX is run to generate a SPICE netlist.
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Running Assura DRC for the MSFF Layout

1. From the tutorial library, open the MSFF layout.
2. Run Assura DRC by choosing Assura Run DRC.

3. In the Run Assura DRC form, for Run Name, type MSFF or leave it blank. Assura fills in
the name of the cell when it runs.
4. For the Run Directory field, type
./av/drc
5. For the Technology field, choose inhConnLib.
6. Click OK.
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A Progress form appears. When DRC completes successfully, a dialog box appears
saying so and asking if you want to view the results.
7. In the dialog box, click Yes.
There should be no DRC errors.
Running Assura LVS for the MSFF Layout

2. In the Run Assura LVS form, for Run Name, type MSFF or leave it blank. Assura fills in
the name of the cell when it runs.
./av/lvs

5. Uncheck the Binding File(s) box, if it is checked. No binding rule is needed here.
6. Click OK.
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A Progress form appears. When the LVS run completes, a dialog box appears stating
whether the schematic and layout match and asking whether you want to view the
results.
The layout and schematic should match. If they do not, return to the layout and figure out
what does not match the schematic.
7. In the dialog box that says the schematic and layout match, click Yes to see the results.
8. Close the LVS Debug window.
Running Assura RCX for the MSFF Layout

1. Run RCX by choosing Assura Run RCX.
Note: If you did not previously click Yes to see the LVS results, the Run RCX option is
grayed out. You can select Assura Open Run to open a previous LVS run which
allows you to run RCX.
2. For the Setup tab,
a. Make sure that Technology is set to inhConnLib and Rule Set is set to default.
b. For the Output field, choose Spice.
c. For the Name field, type MSFF.sp.
3. Click the Extraction tab.

a. For the Extraction Mode field, choose RC.
b. For the Name Space field, choose Schematic Names.
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c. For the Ref Node field, type GRND.
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4. Click the Netlisting Options tab.
a. For the Parasitic Capacitor Models field, choose Include as Comment.
b. Turn on Add Explicit Vias.
5. Click the Run Details tab.
a. Verify that Run Name is set to MSFF.
b. Verify that the path in the Run Directory field ends with
/av/lvs
6. In the Assura parasitic Extraction form, click OK.
October 2005 186

A Progress form appears. When the Assura RCX run completes, a dialog box appears
stating whether it completed successfully.
7. Close the dialog box.
Assura RCX writes a file named MSFF.sp in the inhConn_tutorial_versionNumber
directory in the terminal window where you started the icfb software.
8. In a terminal window, go to the inhConn_tutorial_versionNumber directory where
you started the icfb software and copy the MSFF.sp file to the LibGen directory with the
following command:
cp MSFF.sp LibGen
Generating an Abstract View for MSFF

1. If the tutorial MSFF layout view is not open, open this view.
2. In the layout window, choose Tools Abstract Editor.
3. Choose Abstract Create Abstract.
4. For the Generate From field, turn on Library, then click OK.
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The Percent Complete window appears briefly as the Abstract tutorial form opens with
the inv cell displayed.
5. If the MSFF cell does not appear under Core, select Ignore and the MSFF cell, and
choose Cells Move, and select Core as the destination for
Creating Pins for the MSFF Abstract View

Run the abstract generator on the MSFF cell.
1. In the Abstract tutorial form, import pin information by doing the following:
a. For the Cell field, click MSFF and then choose Flow Pins.
October 2005 188

with POWR vdd.
with GRND gnd.
4. If an exclamation mark (!) appears in the Pins column of the Abstract tutorial form for
MSFF, look at the warnings in the Log section.
Ignore the four warnings about the prBoundary not enclosing all cell view geometry, net
expressions already existing, and terminal GRND and POWR having different types.
October 2005 189

Creating an MSFF Extracted View

You should see a check mark for MSFF in the Extract column on the Abstract tutorial
form.
Creating an MSFF Abstract View

1. In Abstract tutorial form, create an abstract view by choosing Flow Abstract.
October 2005 190

2. Click the Site tab, and set the Site name cyclic field to COREinh.
4. In Abstract tutorial form, look in the Abstract column for MSFF.
If there is a check mark, the abstract view was generated without errors. If there is an
exclamation mark (!), look at the warnings in the Log section of the form.
5. Open the tutorial MSFF abstract view.
Note: To see newly created views using the Library Manager, you must refresh the list
of views by choosing View Refresh.
6. Check the POWR and GRND rails by selecting each rail and pressing the q bindkey to
examine its properties. Choose Connectivity, and verify that the inherited connections
for the POWR and GRND terminals have the right properties and defaults.
7. Close the tutorial MSFF abstract view.
Verifying the MSFF Abstract

When you verify the abstract view, the Abstract Editor uses the Encounter place and route
tools.
October 2005 191

1. In Abstract tutorial form, verify the abstract by choosing Flow Verify.

tab.
3. In the Target system selection cyclic field at the right side of the form, make sure
Encounter is selected.
4. At the bottom of the Running step Verify for the selected cell(s) form, click Run.
A Percent Complete dialog box appears, showing the run progress. It might take a few
minutes form the abstract step to complete.
Ignore the warning about a locked process as well as the four warnings about the
prBoundary not enclosing all cell view geometry, net expressions already existing, and
If there are any errors in the verification step, look in the following directory:
./.abstract/verify
structure in Encounter. The encounter.log file summarizes all the results. At the bottom
of the log file is the report about VERIFY CONNECTIVITY, which should say Found no
problems or warnings.
Creating LEF for the Library (Optional)

If you would like to see the inverter and MSFF as LEF, perform these steps:
1. In the Abstract tutorial form, create LEF by choosing File Export LEF.
October 2005 192

2. Change LEF Filename to inhConnLib.lef and click OK.
3. In the Abstract tutorial form, choose File Exit, and click Yes in the Exit dialog box.
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4. In the tutorial directory, edit the inhConnLib.lef file, and look at the MACRO MSFF
statement:
MACRO MSFF
CLASS CORE ;
FOREIGN MSFF 0 0 ;
ORIGIN 0.00 0.00 ;
SIZE 27.72 BY 7.92 ;
SYMMETRY X Y ;
SITE COREinh ;
PIN SI
DIRECTION INPUT ;
PORT
LAYER Metal1 ;
RECT 0.79 2.41 1.86 2.81 ;
RECT 0.79 2.11 1.19 2.81 ;
END
END SI
PIN SE
DIRECTION INPUT ;
PORT
LAYER Metal1 ;
RECT 1.01 4.09 1.85 4.49 ;
RECT 0.98 4.05 1.38 4.45 ;
END
END SE
PIN QN
DIRECTION OUTPUT ;
PORT
LAYER Metal1 ;
RECT 26.73 3.43 27.59 3.83 ;
RECT 26.68 4.85 27.08 6.67 ;
RECT 26.68 1.73 27.08 2.38 ;
RECT 26.73 1.73 27.03 6.67 ;
END
END QN
...
Exit the Cadence Software

Close all Cadence sessions.
October 2005 194

Library Characterization
To assure the accurate simulation of a standard digital cell by a digital simulator, the cell must
be characterize by performing worst-case analog simulations on its netlist, which contains
parasitic components from the extracted layout. To obtain the best, worst, and typical delays
for each signal path (or group of paths) through a cell, use high and low voltages, high and
low temperatures, and fast and slow process information.
SignalStorm library characterizer (SLC) looks through the extracted SPICE netlist of the
MSFF, which contains 42 interconnected MOSFETS and many parasitic resistors and
capacitors, and recognizes structures such as NAND and NOR gates and elementary flip-
flops. SLC then generates a list of test vectors that completely characterize the performance
of the logic combinations from all input pins to all output pins: propagation delays, setup and
hold times, and power draw.
In the case of the MSFF circuit, the SLC process results in 49 test vectors to be simulated at
best, typical, and worst corners, and produces an Advance Library Format (ALF) file and an
RPT file that summarize the results. The ALF file can then be converted into LIB format for
simulator use and into HTML format for data sheet use.
To show how the SLC can process an entire library of cells, you combine the SPICE netlists
for the inv cell and the MSFF cell into a single subcircuit file.
Note: To reduce the simulation time for the test vectors created when you characterize an
entire library of cells, use distributed processing for the SLC with more than one ipsd daemon
running.
In this tutorial, to reduce the simulation time for the single system shown in these steps,
The vector set has been reduced to characterize the propagation delay times, but not the
setup and hold times.
Only the typical process corner is simulated.
The reduction in simulation time in the example below is achieved by replacing the vector set
automatically generated by the SCL with an edited version and using an option in the
command file to limit the simulation to just the typical case. The steps to simplify the
characterization process for the purposes of this chapter are located in the
batchCells.cmd file.
October 2005 195

Setting Up the Environment for Library Characterization

Before running the SignalStorm library characterizer (SLC), quit any related, active
processes and then start the SignalStorm daemons in a specific sequence. Also check to see
that the LM_LICENSE_FILE variable is set as well as the CDS_LIC_FILE.
Check for and quit all active ipsd and ipsc processes by doing the following:
1. In the terminal window containing the tutorial directory,
inhConn_tutorial_versionNumber, check whether such processes are
running by typing
ps -ef | grep ips
2. If ipsd or ipsc processes are running, type the following command for each process:
kill processID
3. Recheck for ips processes by typing:

ps -ef | grep ips
4. Start the daemons for running the SignalStorm tools by typing each of the following
commands, in sequence:
a. Type ipsd.
Text appears in the terminal window, showing the SignalStorm version number and
the Cadence copyright statement.
b. Wait until you see your machine prompt, then type ipsc,
Although you are returned to your machine prompt quickly, wait until your system
displays text stating that service is starting.
c. After you see the message that service is starting, press Enter.
d. Wait until you see your machine prompt, then type

ipsc -n spectre
5. Watch for the availability of the Spectre circuit simulator, which depends on whether you
have access to a license.
You should see a message stating how many licenses are available for the Spectre circuit
simulator now.
If you do not get a license, see your system administrator.
After you see a message about Spectre licenses being available, press Return to
return to the prompt.
October 2005 196

6. Verify that an ipsc process is running for the Spectre circuit simulator by typing
ipsstat.
The results should look similar to this, with your host system name replacing the one
shown below:
IPSC INFORMATION:
TAG: 0 MAX NUM: 800 MAX LOAD: 2.000
USER INFORMATION:
NO USER ATTACHED
ipsc[1]: NOT FOUND
ipsc[2]: NOT FOUND
USER INFORMATION:
NO USER ATTACHED
ipsc[4]: NOT FOUND
IPSD INFORMATION(ALL IN THIS NETWORK):
HOST: your_host_name #CPU: 1 LOAD: 0.045
In the IPSC information, verify that the following lines produced a Spectre license:
You can ignore NOT FOUND messages for servers 1, 2, and 4. You are now set up to run
library characterization.
Running Library Characterization

Normally, library characterization is run on an entire library. Therefore, in this section of the
tutorial, library characterization is run on both the inv cell from Chapter 5, Inherited
Connections in an Inverter, and the MSFF cell from this chapter. The library characterization
process creates the inhConnLib.lib file, which is a timing characterization file that can be
used by digital simulators and place and route tools, such as SoC Encounter.
1. Change directories to the LibGen directory and look at the contents:
October 2005 197

inv.sp and MSFF.sp are the SPICE netlists extracted from the layout.
The inv.sp file is from Chapter 5, Inherited Connections in an Inverter.
mos1.scs is the model file that includes the nmos1 and pmos1 Spectre models
from the inhConnLib library.
corners.scs is a listing of the parameters the models use for the NOM, SLOW,
and FAST process corners.
setupFile.txt defines the supply and threshold voltages and temperatures to
be applied for the typical, best-case, and worst-case simulations. The threshold
voltages are derived from information in the models.
The batchCells.cmd file is the sequence of commands needed to generate the
inhConnLib.lib file by running simulations on the extracted netlists.
2. Create a merged subcircuit file by concatenating the inv.sp and MSFF.sp files using
the UNIX copy and cat commands in the LibGen directory, as follows:
a. Copy the inv.sp file to inhConnLib.sp by typing:

cp inv.sp inhConnLib.sp
b. Concatenate the MSFF.sp file to the inhConnLib.sp file, thereby placing both
subcircuits in the same file, by typing:
cat MSFF.sp >> inhConnLib.sp
where the two greater-than symbols ( >> ) are required for concatenation.
3. Run the SignalStorm library characterizer using the batchCells.cmd file by typing the
following in the LibGen directory:
slc -S batchCells.cmd
October 2005 198

It takes approximately 5 to 10 minutes for the characterization to complete. When the

characterization completes, the system displays a dswave window showing one of the
propagation delays through the MSFF flip-flop:
4. When the dswave window appears,
a. Examine the waveform for the simulated transitions at the various corners.
b. In the LibGen directory,

Look at the char.rpt file for a summary of the results of the simulations.
Examine the inhConnLib.lib file for the output of the characterization for
both the inv and MSFF cells.
5. Close the dswave window by choosing File Quit.
October 2005 199

Generating a Verilog Model with Characterized Delays for the Library

If Verilog models with delays for both the INV and MSFF designs are required, vreate these
models from the results of the library characterization.
1. Create a Verilog model file by typing the following in the LibGen directory:
alf2veri -alf inhConnLib.alf -verilog inhConnLib.v
The system displays text about reading and successfully converting both CELL MSFF
and CELL INV.
2. Open the inhConnLib.v file with a text editor and notice that both cells are included
as Verilog models, and notice how the propagation delays for the MSFF for high and low
transitions are inserted in the specify block.
Creating HTML Data Sheets for the Library

Create a data sheet in HTML format and view it with a web browser.
Create HTML data sheets for both the inv and MSFF cells by typing the following in the
LibGen directory:
alf2html -alf inhConnLib.alf
This command creates the directory ./slcLib. To view the data sheets, use your internet
browser to open the ./slcLib/index.html file and select the data sheet you want to view.
Summary
In this chapter, you used
Implicit inherited connections for power connections in a cell that is not likely to be
instantiated as an independent entity.
Explicit inherited connections for power connections for a higher level cell that would
likely be instantiated as an independent entity.
Using this approach provides a correct way to resolve all inherited connections across
multiple software tools, from schematic to layout to verification to abstract and library
characterization.
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7
Using Inherited Connections within an
Analog Cell
This chapter covers the use of inherited connections as power rails and as internal
connections within an analog cell. A simple mosfet comparator is used as an example
showing these usages. In the example, net expressions are attached to explicit pins on the
schematic for the power, and an inherited connection is attached to a bulk mosfet terminal on
the input transistors located inside an isolated well.
The principles shown in this chapter reinforce theory from previous chapters:
Cells that have a standalone and possibly multiple instantiation, use explicit pins on the
schematic, even if they are not contained in the symbol.
Attaching a label to a wire overrides the propagation of the inherited connection. The
example shows why a designer might want to use that methodology in particular cases.
Frequently, a designer wants to use a behavioral model during simulation, either because
The schematic does not exist yet and the designer wants to perform a system simulation.
or
To save time because a behavioral model runs faster than the schematic or a view
containing many parasitics extracted from a layout.
In this chapter, you create a behavioral model from an extracted layout that provides a more
accurate simulation than the schematic without parasitics would provide. This behavioral
model is generated using the Virtusoso Characterization and Modeling Environment (VCME).

Using inherited connections in an analog circuit for more than just power and ground
connections.
Using a wire name to over-ride a net expression.
Generating an extracted view containing inherited connections.
October 2005 201

Using Inherited Connections within an Analog Cell
Using an extracted view to create a Verilog-A model with VCME.

Creating an abstract for an analog cell.
The goal of this module is to show the proper use of inherited connections in analog
schematics and layouts, and how Virtuoso Characterization and Modeling Environment
(VCME) creates a correct model for the analog cell. The test circuit is a simple mosfet
comparator with the input devices in their own well.
Simulation of a provided comparator schematic using an inherited connection with a default

of gnd! on the input transistor bulk-source connection to an isolated well; and simulating with
and without a wire name label on that common connection. The power pin has a net
expression with a default of avdd! The ground pin has a net expression with a default of
agnd!

Simulating a Simple Comparator with Inherited Connections on page 203
Overriding the Default Connection on the Bulk Terminals on page 207
Comparing the Provided Layout against the comp Schematic on page 208
Run Assura DRC to Verify the Layout Design Rules are Met on page 210
Run Assura LVS to Verify the Layout Matches the Schematic on page 210
Create an Extracted View of the Layout on page 211
Create a Verilog-A Model for the Comparator from the av_extracted View on
page 212
Viewing Results on page 217
Generating an Abstract View for comp on page 221
Creating Pins for the comp abstract view on page 222
Creating a comp Extracted View on page 224
Creating a comp Abstract View on page 224
Verifying the comp Abstract on page 226
Creating LEF for the Library (Optional) on page 227
Summary on page 228
October 2005 202

Simulating a Simple Comparator with Inherited

Connections
The simple comparator circuit provided uses net expressions for power and ground, and for
the input nmos transistor bulk terminals. The differential input stage is placed in an isolated
pwell to provide more input range by reducing the bulk effect on the threshold voltage on the
nmos devices. However, if there is a net expression on the bulk terminal on those nmos
devices in the isolated pwell, a net name needs to be added to prevent the default bulk
terminal connection (usually gnd!) from being pushed to the common connection between
the bulk and source terminals. The simulations in this section compare performance without
and then with a net name on that common connection.
1. If the Cadence icfb software is not already running, start it by typing:
icfb &
2. In the CIW, choose Tools Library Manager.
3. In the tutorial library, open the comptest schematic.
This circuit provides a testbench for simulating the comp circuit. The differential input is
supplied a differential sinewave with a DC offset supply, Vb, which is set during
simulation. A common application is to convert a differential analog signal to a single-
ended digital signal. It is important to provide the maximum input range for any common
mode input to guarantee symmetrical timing on the output.
The supply voltage, Vsup, is set during simulation. Note that POWR is a netSet property
attached to the comp instance and is set equal to vdd, the supply voltage, while GRND,
another netSet property is set to gnd!, the test circuit ground. (The gnd next to the
October 2005 203

ground symbol is a symbol name, not the net name, which is set to gnd! as the pin name
of the symbol.)
netSet properties on the

comp instance
4. Descend into the comp circuit to examine the structure, in particular the input nmos
transistor pair that uses an isolated pwell with the bulk and source terminals connected
together and tied to the current source drain rather than to ground. The input pair uses
nmos_mod transistors created in an earlier chapter of the tutorial. They have a net
expression on the bulk terminal with a default value of gnd! If not connected to another
signal, the bulk terminals are connected to ground by default by the netlister, which forces
the sources to ground, reducing the input signal swing capability.
Note: The spectre view of the nmos_mod transistors is used during netlisting, so make
sure the spectre view has the same net expression as the symbol view. If this is not so,
then copy the symbol view of the nmos_mod transistor in the tutorial library to the spectre
October 2005 204

view of the nmos_mod transistor in the tutorial library.
Input Stage
5. Simulate the comptest schematic as it exists to obtain a reference simulation.
a. Start ADE from the comptest schematic, Tools Analog Environment.
b. Load the state file, state1, Session Load State to preload the models, a
simulation stop time of 15us, default values for Vsup and Vb, and the output signal,
out, into the ADE form. The ADE form should look like this:
October 2005 205

c. Netlist the circuit, Simulation Netlist Create, and examine the netlist to find
NM0 and NM1. The connections should look like the following:
Note how the inherited connections GRND, POWR and BULK are listed in the
pin list for the comp subcircuit. Now look down to where the comparator is
instantiated, and see how the connections are passed to it from the netSets on
the instance symbol:.
The comparator is I3, and the inh_GRND pin is passed the connection to 0
(gnd!), the inh_POWR pin is passed the connection to vdd, the signal name on
the power supply, and the inh_BULK pin is passed a connection to 0 again. To
see how the circuit operates with those connections, run a simulation where the
input DC bias is swept from 0 to +3v.
6. Choose Tools Parametric Analysis.
a. Insert Vb as the Variable Name, 0 as the From value, and 3 as the To value. Set the
Step Control to Linear Steps and the Step Size to 0.5.
b. Run the simulation by choosing Analysis Start from the Parametric Analysis
form.
c. When the simulation completes, examine the traces. The picture below has been
annotated with the step values. Note the bad simulation results for much of common
October 2005 206

mode input range (2-3 volts bad), where the output is flat because the input Vgs
turns both input mosfets on hard.
Overriding the Default Connection on the Bulk Terminals

The problem with the first simulation is that the inherited connections on the bulk terminals of
the nmos_mod transistors in the isolated pwell are pushing their default connection (gnd!) to
the common source connection, effectively grounding out the transistors and defeating the
current source. That can be easily fixed by placing an arbitrary net name on the common
connection. This label on the net stops the propagation of the inherited connection.
1. Open the comp schematic, and add a wire name label, b1, to the common bulk-source
connection on the input nmos_mod pair, NM0 and NM1, Add Wire Name. Check and
Save the schematic.
Net Name, b1
2. Create a new netlist in ADE, Simulation Netlist Recreate.
October 2005 207

3. Check the new netlist to see if the connection to the bulk terminal is now set to b1:
Note the changes in the comp subckt netlist. inh_BULK no longer appears as an external
node, because it is connected internally as b1, to which both NM0 and NM1 sources and
bulk terminals are connected. In the I3 instantiation of the comparator, there is no longer
any need to pass a value to inh_BULK, so the 0 (or ground) value does not appear at the
end of the pin list for I3.
4. Repeat the simulation as before using the Parametric Analysis.
Note the improved simulation results for most of input common mode range (0.5-2.5 volts
good):
5. When you are done comparing this set of waveforms against the previous set, close
ADE, Session Quit, and the comptest schematic, Window Close.
Comparing the Provided Layout against the comp Schematic

The comparator has been laid out using Virtuoso XL to generate and place the devices, and
create the guardrings and rails. The signals were routed by VCAR. The input nmos_mod pair
is enclosed in a double guard ring: the outer ring surrounds a deep well of Nburied diffusion,
while the inner ring connects to the isolated pwell. This is the ring connected to the bulk and
source terminals of the input pair, and assigned the name b1.
October 2005 208

1. From the Library Manager, open the layout view for the comp cell.
Power rail
Diode-
connected
pmos loads
Input pair of
nmos_mod
transistors
Output
pmos
Inner ring transistors
named b1
Outer ring
connected
to avdd!
Output
nmos
transistors
Input bias
transistors
Ground rail
a. Look at the properties of the POWR and GRND rails (q bindkey). Looking at the
Connectivity, you see that the Net Name for POWR is avdd!, and for GRND the Net
Name is agnd!.
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b. Look at the properties of the inner guard ring around the long input pair of nmos
transistors. Looking at the Connectivity, you should see that the Net Name on the
guard ring is b1.
Inner ring
named b1
Run Assura DRC to Verify the Layout Design Rules are Met
Use Assura to run DRC and LVS on the provided layout for the comp cell to prove the isolated
well is connected correctly with the default inherited connection over-ridden by the net name
on the common bulk-source connection to the isolated well; and that the power and ground
inherited connections are also correct.
1. Run Assura DRC by choosing Assura Run DRC.
2. In the Run Assura DRC form, leave the Run Name blank. Assura fills in the name of the
cell when it runs.
./av/drc

5. Click OK.
A Progress form appears. When DRC completes, a dialog box appears confirming a
successful run and prompting you to view the results.
6. In the dialog box, click Yes.
There should be no DRC errors.
Run Assura LVS to Verify the Layout Matches the Schematic

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2. In the Run Assura LVS form, leave the Run Name blank. Assura fills in the name of the
cell when it runs.
./av/lvs

5. Deselect the Binding File(s) box, if it is selected. No binding rule is needed here.
6. Click OK.
A Progress form appears. When the LVS run completes, a dialog box appears stating
whether the schematic and layout match and asking whether you want to view the
results.
The layout and schematic should match. If they do not, return to the layout and determine
what does not match the schematic.
7. In the dialog box that states the schematic and layout match, click Yes to see the results.
8. Close the LVS Debug window.
Create an Extracted View of the Layout

1. Use Assura RCX to generate an av_extracted view from the layout of the comparator.
a. Choose Assura RCX from the Virtuoso XL Layout Editor.
b. On the Setup tab, set the Output to Extracted View.
c. On the Extraction tab, set the Extraction Mode to RC and enter the Ref Node as
GRND.
d. On the Netlisting tab, set the Parasitic Capacitor Models to Include As Comment and
check Add Explicit Vias.
e. On the Run Details tab, set the Run Name to comp.
f. Click OK.
2. When the extraction completes, close the layout view.
3. Open up the av_extracted view in Virtuoso Layout Editor, select the POWR and GRND
pins, and verify that the net expressions have been carried over (Net Expression
Property is POWR and Default is avdd!; Net Expression Property is GRND and Default
is agnd!). Also check the Net Name of the inner guardring around the input pair: it should
be b1.
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4. Close the av_extracted view when you are done.
Create a Verilog-A Model for the Comparator from the av_extracted View
Use VCME to create a calibrated table model based on the extracted netlist including all the
parasitics that RCX identified. This is a more accurate model than the schematic alone
because it includes routing resistances and capacitances. To run VCME, VSDE41USR1 must
be installed.
1. Start VSdE from the CIW window, Tools VSdE.
2. In the Select Workspace form, choose Create New Workspace and click OK.
3. Assign the New Workspace a Name, such as extComp1 and click OK.
4. Click Next in the New Project Wizard, followed by Finish. There is no need to change
anything.
5. In the main VSdE workspace, right-click Characterization and Modeling, and select
Characterization and Modeling.
6. In the New Characterization and Modeling form, enter a VCME Name, such as
extComp1.
October 2005 212

a. Set the Test Type to Composer; and the For simulator to spectre.
b. In the Characterization and Modeling Flow section, choose Create calibrated

models.
c. Choose Empty test at the bottom of the form.
d. Click OK.
7. In the Spectre VCME Setup form, click the Advanced button, and add av_extracted
to the switchViewList.
8. Click Close.
October 2005 213

9. For Design Location, click Browse, and in the Select Design form, set the Library to
tutorial, and select the comp cell and the av_extracted view.
10. Click OK. Note that the design and cell pins are filled in on the VCME Setup form.
11. Near the bottom of the Spectre VCME Setup form, click the Create Base Test button.
12. In Model Library section of the Test Setup form, click the New (Insert) icon, and
Browse (...) to locate inhConnLib.scs in the /cdslibs/inhConnLib/models/
spectre directory. Add a space after the path and enter NN for the corner.
New
Browse
13. Click Apply and OK.
October 2005 214

14. Select the Function tab in the VCME Setup form. From the Function cyclic field chooser,
select Converter Comparator. Using the cyclic field choosers for each pin:
a. Set avdd to Vdd datatype, and verify the value is 3.0.
b. Set agnd to Vss datatype, and verify the value is 0.0.
c. Click the Advanced Button, and check Add Components under Pin Type
Options. This adds more options to the pin type selector.
d. Close the Advanced Function Options form.
e. Continuing in the Functions tab of the VCME Setup form, change the ibias Pin
Type to Current, and set the current level to -10u.
f. Set inn to Negative input.
g. Set inp to Positive input.
h. The Functions tab should look like this:
i. Click Apply.
October 2005 215

15. Select the Verilog-A tab of the VCME Setup form.
a. Set the Timing model method to 3D table.
b. Set the Input capacitance model method to unused. The Verilog-A tab should look
like this:
c. Click Apply.
16. Select the Sweeps tab on the VCME Setup form.
a. Set the Temperature Sweep By to 50.
b. Set the Vdd Voltage Sweep By to 0.3. The Sweeps tab should look like this:
c. Click Apply.
17. Select the Options tab on the VCME Setup form.
October 2005 216

a. Set Keep waveform files
b. The Options tab should look like this:
c. Click Apply.
18. In the VCME Setup form, click Generate and Run at the bottom left corner of the form,
and then on OK.
19. Click OK in the Characterization and Model(s) form.
20. The 37 simulation runs takes about 12 minutes on an Ultra10. When the simulation
completes, select the Results tab on the VSdE workspace.
Viewing Results
1. Click the Results tab in the bottom left corner of the VSdE workspace.
2. In the Results browser, expand both the configDCM/results (simulations of the
schematic) and the config_veriloga/results (simulations of the Verilog-A models).
3. Expand the extComp1_VerilogA_timing_sweep folder in both results folders.
4. Expand the extComp1_timing folder in both sweep folders.
5. Expand the inp_out_rise:delay folder in both timing folders.
6. Expand the dcm_global_avdd_value[2.7..3.3] folders in both delay folders.
7. Expand the dcm_global_avdd_value = 3 folder in both value folders.
October 2005 217

8. Expand the dcm_temperature[0..100] folder in both value=3 folders.

9. Select the dcm_temperature=50 signal in the configDCM/results value=3/
dcm_temperature[0...100] folder.
10. In the right hand panel, double-click the psfTR Simulation Data File(PSF) simulation data
file.
11. Double-click the out signal to send it to the WaveScan waveform viewer.
12. Do the same for the matching signal in the config_veriloga/results value=3 folder.
October 2005 218

13. Compare the waveforms between the schematic simulation results and the Verilog-A
simulation results. Note how close they match.
14. Browse the tabular data at the dcm_global_avdd_value=3 level (or other levels) and the
families of curves at the dcm_global_avdd_value[2.7..3.3] level (or other levels).
15. View the calibrated Verilog-A models from the Spectre VCME Setup window, by selecting
View VerilogA Calibrated Model. Note the inherited connections for the power.
Inherited
Connections
October 2005 219

16. The table files can be viewed from the VCME Setup window, by choosing View
VerilogA All Lookup Tables, or View VerilogA Lookup Table, and selecting
the particular table from the browser.
Table of offset vs. temperature

and supply voltage.
17. A comparison of CPU simulation time between simulating with the schematic and with
the Verilog-A model can be viewed from the VCME Setup window, by choosing View
VerilogA Performance Report. Note the nearly 7X increase in speed of simulation
time using the Verilog-A model for the comparator.
18. A comparison of the simulation results vs. the specification limits that VCME sets for the
comparator can be viewed as a report from View VerilogA Verification Report.
October 2005 220

This comparison can be viewed graphically by returning to the VSdE Workspace, and
clicking on the Files tab in the bottom left corner. Then expand the Spec Sheets folder,
and double-click the extComp1_VerilogA_model_verification sheet.
19. When you are done examining the model results, close all the VSdE windows.
Generating an Abstract View for comp

1. If the tutorial comp layout view is not open, open this view.
2. In the layout window, choose Tools Abstract Editor.
3. Choose Abstract Create Abstract from the pulldown menu.
October 2005 221

4. For the Generate From field, turn on Library, then click OK.
The Percent Complete window appears briefly as the Abstract tutorial form opens with
the comp cell displayed.
5. Select the comp cell in the Cell field, and choose Cells Move. Select Block as the
destination bin, and choose OK in the form. Click the Block bin to show the comp cell.
Creating Pins for the comp abstract view

Run the abstract generator on the comp cell.
October 2005 222

1. In the Abstract tutorial form, import pin information by doing the following:
a. For the Cell field, click comp and then choose Flow Pins.
with POWR avdd.
with GRND agnd.
4. If an exclamation mark (!) appears in the Pins column of the Abstract tutorial form for
comp, look at the warnings in the Log section.
You can ignore the three warnings about the net expressions already existing, and
October 2005 223

Creating a comp Extracted View

You should see a check mark for comp in the Extract column on the Abstract tutorial
form.
Creating a comp Abstract View

1. In Abstract tutorial form, create an abstract view by choosing Flow Abstract.
October 2005 224

3. In Abstract tutorial form, look in the Abstract column for comp
You should see a check mark for comp in the Extract column on the Abstract tutorial
form.
4. Open the tutorial comp abstract view.
Note: To see newly created views using the Library Manager, you must refresh the list
of views by choosing View Refresh.
October 2005 225

5. Check the POWR and GRND rails by selecting each rail pin and pressing the q bindkey
to examine its properties. Choose Connectivity, and verify that the inherited connections
for the POWR and GRND terminals have the right properties and defaults.
6. Close the tutorial comp abstract view.
Verifying the comp Abstract

When you verify the abstract view, the Abstract Editor uses the Encounter place and route
tools.
1. In Abstract tutorial form, verify the abstract by choosing Flow Verify.
tab.
3. In the Target system selection cyclic field at the right side of the form, make sure
Encounter is selected.
4. At the bottom of the Running step Verify for the selected cell(s) form, click Run.
A Percent Complete dialog box appears, showing the run progress. It might take a few
minutes form the abstract process to complete.
You can ignore the warning about a locked process as well as the four warnings about
the prBoundary not enclosing all cell view geometry, net expressions already existing,
and terminal GRND and POWR having different types.
If there are any errors in the verification step, look in the following directory:
./.abstract/verify
October 2005 226

structure in Encounter. The encounter.log file summarizes all the results. At the bottom
of the log file is the report about VERIFY CONNECTIVITY, which should say Found no
problems or warnings.
Creating LEF for the Library (Optional)

If you would like to see the comp as LEF, perform these steps:
1. In the Abstract tutorial form, create LEF by choosing File Export LEF.
2. Change LEF Filename to inhConnLib.lef and click OK.
3. In the Abstract tutorial form, choose File Exit, and click Yes in the Exit dialog box.
October 2005 227

4. In the tutorial directory, edit the inhConnLib.lef file, and look at the MACRO comp
statement:
Summary
Close all Cadence sessions when you are done. In this chapter, you
Discovered how to use a net name on a floating well tie to create the proper connections.
October 2005 228

Created a sophisticated Verilog-A model for a comparator with inherited connections

using the model generation capability of VCME.
Created an abstract for the comparator.
October 2005 229

October 2005 230

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Virtuoso Inherited Connections Tutorial

Document Revision Version 3.0

Version Date Changes Since Previous Version

Typographic and Syntax Conventions

text indicates text you must type exactly as it is presented.

z_argument Indicates text that you must replace with an appropriate

[ ] Denotes optional arguments. When used with vertical bars, they

| Separates a choice of options; separates the possible values

Indicates that you can repeat the previous argument.

=> Precedes the values returned by a Cadence SKILL language

text Indicates names of manuals, menu commands, form buttons,

There are two types of inherited connections: implicit and explicit.

Implicit Inherited Connection Explicit Inherited Connection

Associated with a wire; terminal Associated with a pin; terminal

A pin always defines an explicit connection, with or without inherited connections.

Figure 1-1 Terminal-Pin-Net Data Model

Inherited connections have two parts:

For example, [@myPower:%:vdd!]

How Tools Interpret Net Names Ending with !

How Netlisting Uses Switch and Stop View Lists

Figure 1-2 How the Netlister Expands Hierarchy

Start with the top-level cell.

Read the first view in the

Does the view exist No Read the next view in the

Is the view on the No

Netlist the instance.

Four questions to ask yourself when creating a netlist with ADE:

This chapter covers the following topics:

How To Send Feedback About the Tutorial

Your email should include the following information:

About the Tutorial

Required Database and Software Releases

Table 2-1 Software and Versions Required for the Tutorial

Type This to Verify Required in these

Table 2-2 Testing Software Versions

Type to Verify Version System Returns Version Information

Setting Up to Run the Tutorial

Downloading the Tutorial Files and Documentation

5. Untar the .tar file by typing

The following directory is created:

This directory contains everything necessary to run the tutorial.

Modifying the Tutorial .cshrc_inhConn File

Table 2-3 Environment Variables Required for the Tutorial

Stream Name Environment Variable

Accessing the Tutorial Documentation

2. Verify the version number of the documentation file.

This chapter covers the following topics:

Starting the Cadence Software

A Simple Example of an Inherited Connection

Defining a Net Expression for Power

2. Change the display options to show the net expression:

a. Choose Options Display.

b. In the Display Options form,

a. In the divBy2 schematic window, choose Add Net Expression.

b. In the Add Net Expression form,

For Property Name, type POWR.

You are prompted to point at a location for the net expression.

Click above this wire.

b. Click on the wire coming out of the upper resistor.

Click on this wire.

The divBy2 schematic should now look like this:

Notice the format of the net expression:

* indicates that the connection is inherited