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A MICRON
WHITE PAPER How Micron SSDs Handle Unexpected Power Loss
Programming NAND cells is an exercise in signal then decoded as 11 at L0 or 10 at L1. If the lower
distributions. As shown in Figure 1, V T is the page is programmed to L1, as shown in Figure 1, the
threshold voltage that is used to detect data bits upper-page program moves the signal to 00 at L2 or
in the cell. In this case, if the stored signal rests 01 at L3, as shown in Figure 2.
in the L0 distribution (a negative V T ), the data bit
is considered to be a value of 1 while a voltage The complication arises when the upper-page program
detected in L1 (a positive V T ) is considered to be a is interrupted while this signal is being moved up
value of 0. The scenario is complicated when the in voltage (to the right in Figure 2)like during an
adjacent upper page is programmed, as shown in unexpected power loss. The incomplete program could
Figure 2. end up incorrectly at any level or indeterminately in
between the detection levels, which may result in an
If the lower page is programmed to the L0 like in unfinished upper-page program, or worse, corrupted
Figure 1, the upper-page program moves the signal adjacent lower-page data that may have been
to L0 or L1, as shown in Figure 2. The new signal is programmed in the distant past.
1 LOWER PAGE 0
OV
L0 L1 L2 L3
VT
Figure 2: Possible MLC Signal Distributions Upper and Lower Pages Written
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A MICRON
WHITE PAPER How Micron SSDs Handle Unexpected Power Loss
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A MICRON
WHITE PAPER How Micron SSDs Handle Unexpected Power Loss
capacitive solution. As shown in Figure 4, instead amount of data protection not only ensures data
of standard surface-mount ceramic capacitors, integrity in unexpected power-loss events, but it
enterprise SSDs use larger tantalum capacitors, also enables the system designer to leave the SSDs
which store more energy to be discharged over a write cache enabled, giving a significant advantage
longer amount of time. in data throughput speeds.
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