AUTOMOTIVE
Designing an automotive or
industrial RADAR/LIDAR system
by Paul McCormack, National Semiconductor
This article outlines
the design
requirements
for an automotive
or industrial
RADAR/LIDAR system
and explains how
GIGAHERTZ sampling
ADCs maximise
dynamic performance
and accuracy.
I Laser range finding and sensing technology
continues to find its way into more and more
exciting applications as analog technology im-
proves in performance, cost and availability. Au-
tomotive system designers are currently devel-
oping sophisticated LIDAR systems, intelligent
enough to automatically controll vehicle speed
and braking systems according to traffic condi-
tions or foreseen problems. Such systems can
also control distance to other vehicles and ob-
stacles and even safety features such as airbags.
Advancements in this technology improve
driver comfort and, more importantly, safety.
This is just one of many applications made pos-
sible by recent developments in LIDAR system
technology. Applications range in diversity
from military rangefinding systems which can
operate over 100s of kilometres to vehicle detec-
tion systems at toll booths which operate only
over a few metres.
Irrespective of the application, the key analog
component in the front-end receive path of
such a system is the ADC used to digitize the
narrow pulses reflected from near and/or dis-
tant objects. Such ADCs need very fast sam-
pling rates combined with high dynamic per-
formance, large analog input bandwidth and
low power consumption. Nationals new GIGA-
HERTZ 8-bit ADC family can digitise analog
input signals at up to 3 GS/s while still main-
taining over 7.0 ENOB (effective number of
bits). The ADC08D1000, for example, achieves
over 7.5 ENOB while sampling at 1 GS/s to
Nyquist. Its input bandwidth of 1.7 GHz en-
ables direct RF conversion in many cases with-
out the need for expensive and complex down-
conversion circuit blocks. Its multiple ADC syn-
chronisation feature allows sampling frequen-
cies to be increased beyond 3 GS/s, if required,
to meet the demanding technical requirements
of high accuracy rangefinding systems. This
report will begin with a description of LIDAR
and a typical LIDAR system using a block
diagram to illustrate its main components.
The benefits of over-sampling the received sig-
nal are described before leading into a discus-
sion of the ADC08D1000. The CLC5526 is then
described as an example of a digital variable
gain amplifier that can be used to boost the
dynamic range of a LIDAR system analog
front-end. Finally, the most important and
interesting features of the ADC08D1000 for
LIDAR applications are also described.
LIDAR is an acronym for light detection and
ranging. LIDAR uses the same principle as
RADAR. The LIDAR instrument transmits
light out to a target. In the example of an auto-
motive system, the target may be another car or
any other obstacle in its path. The main com-
ponent in the transmitter stage is a laser capa-
ble of transmitting narrow pulses over the re-
Figure 1. Block diagram of a
typical LIDAR system
quired range of interest. The transmitted light
interacts with and is changed by the target.
Some of this light is reflected/scattered back to
the receiver where it is analyzed. The change in
the properties of the light enables some prop-
erties of the target to be determined. The time
for the light to travel out to the target and back
to the LIDAR module is used to determine the
range to the target. In many systems an ava-
lanche photo diode (APD) in the receiver is
used to convert the received light pulse to an
electrical signal. The electrical signal is then
generally amplified before digitization by an
ADC. The sampling frequency, analog input
bandwidth and dynamic performance of the
ADC influence the accuracy of range measure-
ment as well as the degree of information that
is extracted from the received signal about the
target object. The transmitted pulse is general-
ly attenuated (atmospheric conditions, etc.)
leading to a large difference in strength between
transmitted and received pulses. Objects in the
near vicinity of the transmitter can also reflect
full power signals back to the receiver. This
leads to demanding dynamic range require-
ments for the system. The receive system
should be sensitive enough to deal with full
power and very low reflected pulses. Dynamic
range requirements in the order of 100 dB are
not uncommon. This dynamic range is gener-
ally achieved by using a VGA (variable gain am-
plifier) or DVGA (digital VGA) in the front end
31
November 2005
 AUTOMOTIVE
Figure 2. Block diagram of the ADC08D1000.
Figure 3. Diagram of ADC08D1000, CLC5526, LM1086, LM86 and FPGA
prior to the ADC. We will see later how the
CLC5526 can boost the receiver channel dy-
namic range by 42 dB. Figure 1 shows a gener-
ic block diagram for a typical LIDAR system.
There are three basic generic types of LIDAR:
range finders; DIAL and Doppler LIDARs.
Range finder LIDARs are the simplest types.
They are used to measure the distance from the
LIDAR instrument to a solid object. The accu-
racy of this measurement is directly related to
the sample rate of the ADC used in the receive
module as shown in a later section. Differential
absorption LIDAR (DIAL) is used to measure
chemical concentrations (such as ozone, water
vapor, pollutants) in the atmosphere. Doppler
LIDAR is used to measure the velocity of a
target. When the light transmitted from the
LIDAR hits a target moving towards or away
from the LIDAR, the wavelength of the light
reflected/scattered of the target will be changed
slightly. This is known as a Doppler shift
hence Doppler LIDAR. If the target is moving
away from the LIDAR, the return light will have
a longer wavelength (sometimes referred to as
a red shift), if moving towards the LIDAR the
return light will be at a shorter wavelength (blue
shift). The necessity in Doppler systems to
accurately measure reflected light wavelength
32
November 2005
and also shape requires a receiver and therefore
ADC that can over-sample this received pulse.
Since the received pulse is very narrow, (nor-
mally in the order of nanoseconds), a very high
sampling ADC is required in the receive path to
achieve the required over-sample rate. The tar-
get can be either a hard target or an atmospher-
ic target the atmosphere contains many mi-
croscopic dust and aerosol particles which are
carried by the wind. Rain, snow and fog also
cause partial light reflections which the receiv-
er should be able to differentiate from solid
targets which are generally of most interest.
The range measurement accuracy that can be
achieved is directly related to the ADC sampling
frequency. The speed of light is: c = 3E+08 m/s.
Therefore light travels 100 m in 100 *
(1/3E+08) = 333.33 ns. At 1 GS/s, the ADC
clock period is 1 ns. In a 1 ns sampling instant,
light will travel 0.3 m or 30 cm. For example,
over a distance of 100 m, a measurement accu-
racy of 15 cm is achievable at 1 GS/s. The
error will increase as sampling frequency is re-
duced. As discussed previously, the velocity of
the target is measured by the change in wave-
length of a reflected light pulse. To measure the
change in wavelength of a 2...3 ns pulse, the
ADC should have a sample rate in the order of
1 GHz or higher. The shape of a received pulse
also contains information regarding the prop-
erties of the target. The shape can only be de-
termined by a considerable over-sampling
ratio. Over-sampling also benefits in the digital
domain in terms of processing gain which is
described towards the end of this article. The
ADC08D1000 is a high-performance pure
CMOS dual 1 GS/s ADC manufactured on a
state-of-the-art 0.18 m process. Its folding and
interpolating architecture, the fully differential
comparator design, the innovative design of the
internal sample-and-hold amplifier and the
self-calibration scheme enable a very flat re-
sponse of all dynamic parameters beyond
Nyquist, producing a high 7.5 ENOB with a
500 MHz input signal and a 1 GHz sample-rate
while providing a 10...18 BER.(bit error rate).
Each converter has an integrated 1:2 demulti-
plexer that feeds two LVDS buses and reduces
the output data rate on each bus to half the
sampling rate. A differential output data clock
(DCLK) is provided to enable data capturing in
the digital output circuitry. The main features
of the ADC can be identified in the block
diagram in figure 2.
The digital device used to capture and process
data is generally an FPGA in most applications.
Todays readily available off-the-shelf FPGAs
can handle LVDS data rates in the range of
500 Mbit/s to 1 Gbit/s. However, their cost in-
creases significantly as data rate handling capac-
ity increases. The 1:2 de-muxed outputs offer a
cost-saving advantage when the cost of the total
system is considered. The data clock outputs
(DCLK) are used to latch the output data into
the FPGA. Delayed and non-delayed (0 or
180) data outputs are supplied synchronous to
this signal to further ease data capture. To fur-
ther simplify data capture a choice of single
data rate (SDR) or double data rate (DDR) out-
puts is offered. With single data rate the output
clock (DCLK) frequency is the same as the data
rate of the two output buses. With double data
rate the DCLK frequency is half the data rate
and data is sent to the outputs on both input
clock edges.
The ADC08D1000 must be driven with a differ-
ential input signal. Operation with a single-
ended signal is not recommended. It is impor-
tant that the inputs either be AC-coupled to the
inputs with the VCMO pin grounded or DC-
coupled with the VCMO pin not grounded and
an input common mode voltage equal to the
VCMO output. A suitable device for driving the
analog inputs is Nationals CLC5526. The
CLC5526 is a high-performance, digitally con-
trolled, variable-gain amplifier (DVGA) with 8
gain settings ranging from -12 to +30 dB in
6 dB steps. The CLC5526 maintains a 350 MHz
bandwidth over its entire gain and attenuation
range from +30 dB to -12 dB. Digital control is
 AUTOMOTIVE

accomplished by a 3-bit parallel gain control input and a data valid pin
to latch the data. It can be used in conjunction with the ADC08D1000
and FPGA to boost the receive channel dynamic range. The DVGA, in
conjunction with the FPGA forms an automatic levelling loop that com-
presses the dynamic range of the input signal prior to sampling by the
ADC. By doing so, it extends the dynamic range of the ADC by as much
as 42 dB. In practice, the gain loop is implemented as follows. The FPGA
is used to measure the ADC output signal power and directly control the
CLC5526 gain based on this power measurement. This should be per-
formed in such a manner that the DVGA gain steps are user transparent,
i.e. the gain compensation function in the FPGA should remove the
DVGA gain steps at the output. The time alignment of this gain compen-
sation circuit should be adjusted to support the ADC latency, which is
13...14.5 clock cycles for the ADC08D1000. Figure 3 illustrates an exam-
ple of how the CLC5526 may be used to drive the differential inputs of
the ADC08D1000.

Digital filtering in the FPGA also provides additional dynamic range in

the form of processing gain (PG). PG is a function of ADC sampling rate.
ADC noise performance is typically limited by thermal noise. When an
ADC is specified, the noise bandwidth is normally defined as the Nyquist
bandwidth. This leads to an integrated noise-floor measurement relative
to full-scale (dBFS) in a 500 MHz bandwidth for the ADC08D1000.
When the ADC08D1000 output is digitally filtered, a much narrower
bandwidth is provided at the output. This filtering process provides noise Figure 4. Graph of ADC08D1000 sampling in DES mode
processing gain (PG) as a function of the bandwidth reduction.

The dual edge sampling (DES) feature causes one of the two input pairs
to be routed to both ADCs. The other input pair is deactivated. One of
the ADCs samples the input signal on one input clock edge (the duty cycle
correction circuitry allows a clock duty cycle of 80/20% even in DES
mode), the other samples the input signal on the other input clock edge
(also duty cycle corrected). The result is a 4:1 de-multiplexed output with
a sample rate that is twice the input clock frequency. Therefore, the total
sample rate with a 1 GHz clock is 2 GS/s and the output data rate is
500 Mbit/s on each of the parallel differential LVDS buses.

The ADC08D1000 has the capability to precisely reset its sampling clock
input to DCLK output relationship as determined by the user-supplied
DCLK_RST pulse. This allows multiple ADCs in a system to have their
DCLK (and data) outputs transition at the same time with respect to the
shared CLK input that they all use for sampling. This enables system de-
signers to achieve sampling frequencies in excess of 2 GS/s, i.e. two
ADC08D1000s could be interleaved in DES mode to achieve a total of
4 GS/s. This naturally requires careful circuit and board layout design, the
clock trace should be the same length between devices to precisely match
trace delays. Timing mismatches lead to increased harmonic distortion at
the converters output. In figure 4, the DES feature is illustrated with a
200 MHz input signal. The performance is so good that ENOB only drops
by 0.1 bits when the sampling frequency is doubled from 1 GS/s to 2 GS/s.

Some high-power laser transmitters may require temperature monitor-

ing and many standard analog or digital sensors can be used for this pur-
pose. Additionally, the ADC08D1000 has pins 34 and 35, Tdiode_P and
Tdiode_N, temperature diode positive (anode) and negative (cathode)
for die temperature measurement. The LM86 is just one example of Na-
tionals remote diode temperature sensors that can be used to measure
the die temperature of the ADC08D1000 using its dedicated on-chip p-
n junction. The LM86's diode inputs connect directly to pins 34 and 35
and it operates by forcing two small currents in a 10:1 ratio through the
on-chip p-n junction. The LM86 measures the voltage drop across the
junction with both currents and because the voltage across a p-n junc-
tion is proportional to temperature, the sensor can measure the exact die
temperature to within 1 C. I

33
November 2005