Escolar Documentos
Profissional Documentos
Cultura Documentos
Architecture
Javed Asghar, Technical Marketing Architect - Speaker
BRKARC-2003
Swiss Army Knife Built for Edge Routing World
Cisco ASR9000 Market Roles 1. High-End Aggregation &
Transport
Web/OTT
Multiservice Edge 2. DC Gateway Router
DC gateway 1. DC Interconnect
2. DC WAN Edge
Broadband 3. WEB/OTT
Gateway
3. Services Router
Large Enterprise 1. Business Services
WAN 2. Residential Broadband
3. Converged Edge/Core
4. Enterprise WAN
Other ASR9000 or Cisco IOS XR Sessions
you might be interested in
IOS-XR Overview
32-bit and 64-bit OS
IOS-XRv 9000 Virtual Forwarder
Netconf/Yang
ASR9000 Hardware Overview
ASR9k Chassis Portfolio Offers Maximum Flexibility
Physical and Virtual
Compact & Powerful High Density Service Edge
Flexible Service Edge
Access/Aggregation and Core
Small footprint with full IOS-XR Optimized for ESE and MSE with Scalable, ultra high density service
feature capabilities for distributed high M-D scale for medium to large routers for large, high-growth sites
environments (BNG, Pre-agg etc.) sites
ASR 9922
ASR 9912
ASR 9006
x86 ASR 9904
IOS XRv ASR 9001 / 9001-S
Now
Typhoon
Class Typhoon Skytrain Sacramento PowerPC
360G 55nm 65nm 65nm Quad Core
60 Gbps 60 Gbps 220 Gbps 1.5 Ghz
Future
Tomahaw
k Class Tomahawk Tigershark SM15 X86
800G 28nm 28nm 28nm 6 Core
240 Gbps 200 Gbps 1.20 Tbps 2 Ghz
Shipping since IOS-XR 4.2.1
ASR 9001 Compact Chassis May 2012
Side-to-Side airflow Front-to-back air flow with air flow
2RU baffles, 4RU, require V2 fan
Sub-slot 0 with MPA Sub-slot 1 with MPA
Supported MPAs:
Redundant Fixed 4x10G
(AC or DC) 20x1GE
Power Supplies 2x10GE
SFP+ ports
Field Replaceable 4x10GE
1x40GE
Fan Tray
Field Replaceable
ASR-9001 System Architecture Overview
MPAs
2,4x10GE
20xGE
1x40GE
Typhoon
FIA
ASIC
Switch Fabric
On-board SFP+ 10GE
2x10 SFP+ SFP+ 10GE LC RP
ports Internal CPU CPU
SFP+ 10GE EOBC
SFP+ 10GE
MPAs Typhoon
2,4x10GE
20xGE
FIA
1x40GE
ASIC
Switch Fabric
On-board SFP+ 10GE
2x10 SFP+ SFP+ 10GE LC RP
ports Internal CPU CPU
SFP+ 10GE EOBC
SFP+ 10GE
MPAs Typhoon
2,4x10GE
20xGE
FIA
1x40GE
Disabled by Default
Upgradable via License
RP CPU and linecard CPU same arch. as the larger systems
uses a single crossbar ASIC (just due to smaller bandwidth requirements)
Cisco ASR 9006 Overview
Feature Description
Total Capacity 3.68T
Front-to-back air flow
Capacity per Slot 920G
with air flow baffles,
13RU, vertical Slots 6 slots - 4 Line Cards and 2 RSPs
Rack size 10RU
Side-to-back airflow, 10 RU Power 1 Power Shelf, 4 Power Modules
2.1 KW DC / 3.0 KW AC supplies
Fan: Side to Side Airflow
Optional Baffle for Front-to-Back Airflow
2 Fan Trays, FRU
RSPs Integrated Fabric, 1+1 Redundancy
Line cards Tomahawk
Typhoon
VSM
SIP700 & SPAs
Cisco ASR 9010 Overview
Feature Description
Total Capacity 7.36T
Capacity per Slot 920G
Slots 10 slots - 8 Line Cards and 2 RSPs
Rack size 21RU
Power: 2 Power Trays
2.1 KW DC / 3.0 KW AC supplies
4.4 KW DC / 6.0 KW AC supplies
Fan: Front to Back Airflow
2 Fan Trays, FRU
RSPs Integrated Fabric, 1+1 Redundancy
Line cards Tomahawk
Typhoon
VSM
SIP700 & SPAs
Cisco ASR 9904 Overview
Feature Description
Total Capacity 6T
Capacity per Slot 3T
Front-to-back air flow with air flow Slots 4 slots - 2 Line Cards and 2 RSPs
baffles, 10RU Rack size 6RU
Power 1 Power Trays, 4 Power Modules
2.1 KW DC / 3.0 KW AC supplies
Fan Side to Side Airflow, Front-to-Back Optional
1 Fan Tray, FRU
RSPs Integrated Fabric, 1+1 Redundancy
Line cards Tomahawk
Typhoon
SIP700, VSM
2 Power Trays
P
L Fabric card 0 230G
1G/10G/40G/100G A
LC7
N
E
RSP1 230G Fabric card 4 230G
RPS440 RSP880
ASR 9006
Availability Q1CY12 Q1CY15
Processor Four Cores - 2.1GHz Eight Cores - 2.2GHz
NPU Bandwidth 60G 240G
Fabric Planes 5 7
Fabric Capacity 440G 880G
ASR 9904
Memory 6G for TR 16G for TR
12G for SE 32G for SE
SSD 2x 16GB Slim SATA 2x 32GB Slim SATA
LC Support Typhoon/Trident Tomahawk/Typhoon
ASR 9900 Route Processor
ASR 9922 Common for ASR 9912 and ASR 9922
Built for massive control place scale
Ultra High Speed Control Plane with Multi-Core Intel CPU
Huge Scale through High Memory options
Time and Synchronization Support
ASR 9912
RP1 RP2
Availability Q1CY12 Q1CY15
Processor Four Cores Eight Cores
2.1GHz 2.2GHz
NPU Bandwidth 60G 240G
Fabric Planes 5 7
Memory 6G for TR 16G for TR
12G for SE 32G for SE
SSD 2x 16GB Slim SATA 2x 32GB Slim SATA
LC Support Typhoon Tomahawk/Typhoon
Route Switch Processors and Route Processors
RSP used in ASR9904/9006/9010, RP in ASR9922/9912
9904/9006/9010 9922/9912 9922/9912
RSP880
RSP440 RP1 RP2
2nd Gen RP and Fabric ASIC 3rd Gen RP and Fabric ASIC
Intel x86 Intel x86 Intel x86 (Ivy Bridge EP) Intel x86 (Ivy Bridge EP)
Processors
4 Core 2.27 GHz 4 Core 2.27 GHz 8 Core 2GHz 8 Core 2GHz
SSD 2x 16GB Slim SATA 2x 16GB Slim SATA 2x 32GB Slim SATA 2x 32GB Slim SATA
nV EOBC
2 x 1G/10G SFP+ 2 x 1G/10G SFP+ 4 x 1/10G SFP+ 4 x 1/10G SFP+
ports
23
ASR 9900 - Switch Fabric Cards
ASR 9922 Common for ASR 9912 and ASR 9922
7 Fabric Card Slots
Decoupled, multi-stage switch fabric hardware
True HW separation between control and data plane
Add bandwidth per slot easily & independently
ASR 9912
Similar architecture to CRS
SFC110 SFC2
Availability Q1CY12 Q1CY15
Fabric Capacity 110G 230G
per SFC
Fabric Capacity 660G N+1 1.38T N+1
Per Line Card Slot 770G N+0 1.61T N+0
Fabric N+1 N+1
Redundancy
LC Support Typhoon Tomahawk/Typhoon
In-Service
Upgrade
New ASR-9922 and ASR-9006 V2 Fans
ASR 9922-FAN-V2
IOS XR 5.2.2
ASR 9006-FAN-V2
IOS XR 5.3.0
V2 Fan provides higher cooling capacity for ultra high density cards.
Motor and blade shape optimized to produce higher CFM.
New material capable of dissipating more heat
In service upgrade
PAYG Power
N+1 Redundancy for DC
N+N Redundancy for AC
Typhoon and Tomahawk LCs supported with V2
Plan for the future beyond 1T per slot with V3
Version AC DC Chassis
Notes: 9922 with 20 2x100G vs. 9912 with 5 8x100G 8-year facility
Year amortization with 1.7 PUE, 40C max, France power (USD $.19 per
kWh) N:N Power redundancy
Line Card System Architecture
1. Typhoon, Trident, SIP-700, VSM
2. Tomahawk
3. Inteface QoS
Modular SPA Linecard
20Gbps, feature ritch, high scale, low speed Interfaces
Scalability
Quality of Service
128k Queues Distributed Control and
Data Plane
High Availability
128k Policers
20Gbits, 4 SPA Bays IC-Stateful Switch Over
H-QoS Capability
L3 i/f, route, session
Color Policing protocol scaled for MSE MR-APS
needs
IOS-XR base for high
Powerful & Flexible QFP
scale and Reliability
Processor
Flexible uCode Architectue SPA Support
for Feature Richness SIP-700
ChOC-3/12/48 (STM1/4/16)
L2 + L3 ServicesL FR, PPP,
HDLC, MLPPP, LFI POS: OC3/STM1, OC12/STM4,
OC-48/STM16, OC192/STM64
L3VPN, MPLS, Netflow,
6PE/6VPE SPAs ChT1/E1, ChT3/E3, CEoPs, ATM
ASR 9000 Ethernet Line Card Overview
-L, -B, -E
First-generation LC
Trident NPU:
15Gbps, ~15Mpps,
bi-directional
A9K-40G A9K-4T A9K-8T/4 A9K-2T20G A9K-8T A9K-16T/8
-TR, -SE
Second-gen LC A9K-MOD160
Typhoon NPU:
60Gbps, ~45Mpps, A9K-MOD80
bi-directional
A9K-24x10GE A9K-2x100GE MPAs
(A9K-1x100G) 20x1GE
2x10GE
4x10GE
8x10GE
1x40GE
2x40GE
A9K-36x10GE
-L: low queue, -B: Medium queue, -E: Large queue, -TR: transport optimized, -SE: Service edge optimized
ASR 9000 80-360G Typhoon Class Linecards
Hyper Intelligence & Service Scalability
High Performance
Line rate performance on all line cards 24x10GE
STATS MEMORY
FIB MAC
LOOKUP Forwarding chip (multi core) FRAME MEMORY
MEMORY TCAM
-
CPU LC1
LC2
CPU
Data 3x10GE
SFP + 1NP 2
packet 3x10GE
SFP + NP
FIA 3x10GE
SFP +
NP
FIA
3x10GE
3x10GE
SFP +
NP 2
Fabric ASIC
Switch
SFP + NP
FIA 3x10GE
3x10GE NP
Fabric ASIC
Switch
NP SFP +
SFP + FIA
3x10GE
3x10GE
SFP +
NP
SFP + NP
FIA 3x10GE
3x10GE
SFP +
NP
SFP + NP FIA
3x10GE
3x10GE
SFP +
NP
SFP + NP
3x10GE FIA 3x10GE
NP
NP SFP +
SFP + FIA
3x10GE
SFP +
NP
33
Typhoon LC: 24x10G Ports Architecture
3x 10G
3x10GE 30G
Typhoon 60G
SFP +
3x 10G FIA 90G RSP 440 Switch
3x10GE
SFP +
Typhoon No Congestion Point
30G Fabric
3x10GE
3x 10G Non-Blocking everywhere
Typhoon 30G 60G Line cardlocal
SFP + Fabric
3x 10G FIA 90G Complex
3x10GE 30G (NextGen
Typhoon S/F ASIC)
SFP +
Typhoon NPU
3x 10G BW and Performance 8x55G
RSP 0
3x10GE
1. 120G and 90Mpps Typhoon
Uni-directional 30G 60G
SFP +
2. 60G and 45Mpps full-duplex (each direction ingress/egress)
3x 10G FIA 90G
3x10GE 30G
Typhoon
SFP +
3x 10G
3x10GE 30G 60G
Typhoon RSP 1
SFP +
3x 10G FIA 90G
3x10GE 30G
Typhoon
SFP +
Typhoon Line Card Architectures
36x10G Port LC 2x100G Port LC
MOD80 LC MOD160 LC
Trident vs. Typhoon Major Feature Scale
Queue Scale (per NP) 64K egress + 32K ingress 192K egress + 64K ingress
Policer scale (per NP) 32K/64K (-L,-B/-E) 32K/256K (-TR/-SE)
* It require scale profile configuration to reach maximum FIB or MAC on the Trident line
card. On Typhoon, FIB and MAC has dedicated memory
ASR9k Full-Mesh IPv4 Performance
ASR9010,
2x RSP-440
8x Typhoon 24x10G = 192 ports
Full mesh of flows = ~72,000 flows
(36k Full-duplex Flows)
ASR9k
. .
IXIA . . IXIA
Tx/Rx . . Tx/Rx
.
.
A9k-24x10GE L3 Multicast Scale Performance
Setup and Profile
Scale Profile:
1. Unidirectional Multicast
L3 sub-interface multicast
2. 2k (S,G) mroutes receiver facing ports
3. 24 OIFs per (S,G) mroute
port 0
ASR 9010 port 1
IXIA Multicast Receivers
A9k-24x10GE
A9k-24x10GE
.
IXIA Multicast Source port 10 10G IGMP Joins
.
.
.
port 21 IXIA Multicast Receivers
port 22
IXIA Multicast Receivers
port 23
IXIA Multicast Receivers
A9k-24x10GE L3 Multicast Scale
Throughput Performance Results
Mfps
140
180
120 160
100 140
80 120
109M 100
60 80
40 56M 60
40
20 29M 20M 20
15M 7M
0 3M 0
64 128 256 512 1,024 1,518 2,048 4,096 9,000
Frame Size
Agg Rx Throughput (Gbps) Agg Rx Throughput (Mfps)
Virtualized Services Module (VSM) Overview
Service-3 Service-4
ASR 9000 VSM
Service-1 Service-2 Data Center Compute:
VM-4 VM-3
VM-1 VM-2 4 x Intel 10-core x86 CPU
VMM 2 Typhoon NPU for hardware network processing
OS / Hypervisor
120 Gbps of Raw processing throughput
HW Acceleration
40 Gbps of hardware assisted Crypto throughput
Hardware assist for Reg-Ex matching
Virtualization Hypervisor (KVM)
Service VM life cycle management integrated into IOS-XR
DDR3
DDR3 DIMM Crypto Typhoon NPU
DIMM Crypto
Linecard
10GE/FCoE SFP+
local Fabric
Complex
RSP/
Data
RP 0
Path
Switch
Typhoon NPU
DDR3 Crypto
DIMM DDR3 Crypto RSP
DIMM /RP1
LAN/WAN/OTN
April 2015
(5.3.1)
LAN/WAN/OTN
April 2015
(5.3.1)
Flex 100G CPAK
Investment
Protection
Start with 10 GE
and upgrade to
100 GE in the
future
100 GE LR4 10x10 GE 2x40 GE 100 GE SR10
CPAK Options CPAK 100 GE ER4 CPAK 100 GE LR4 CPAK 100 GE SR10 CPAK
10x10-LR
Tomahawk LC: 8x100GE Architecture
Slice Based Architecture Ivy Bridge CPU
VoQ buffering, Fabric credits, mcast
hashing, scheduler for fabric and
FPOE, Auto-Spread, Complex
L2/L3/L4 lookups, all VPN types, all DWRR, RBH, replication
CPAK: Macsec Suite B+, G.709, OTN, feature processing, mcast replication, egress port
100G, 40G, 10G Clocking QoS, ACL, etc
240G 240G
PHY
Tomahawk Tigershark
NP FIA
240G 240G
PHY
Tomahawk Tigershark
NP FIA
Central XBAR
(SM15)
XBAR
240G 240G
PHY
Tomahawk Tigershark
NP FIA
240G 240G
Per Slice Power Management:
PHY
Tomahawk
(100-200W Power Savings)
Tigershark
PE1(admin-config)# hw-moduleNP FIA
power disable slice [0-3] location
Tomahawk Vs Typhoon Hardware Capability
Metric Tomahawk-SE Scale Typhoon SE Scale
MPLS Labels 1M 1M
2M @ FCS
MAC Addresses 2M
6M - future
4M(v4) / 2M(v6) - XR
FIB Routes (v4/v6) Search
10M(v4) / 5M(v6) possible in 4M(v4+v6)
Memory
future release
VRF 16K 8K/LC
Bridge Domains 256K/LC 64K/LC
TCAM TCAM (80Mb) TCAM (40Mb)
12GB/NPU 2GB/NPU
Packet Buffer
200ms 100ms
EFPs 256K/LC (64K/NP) 64K/LC
L3 Subif (incl. BNG) 128K (64K/NP) 20k/LC (sys)
MOD400 LC MOD200 LC
12x100G Tomahawk LC Skyhammer
High Level Differences:
Tomahawk 8x100G and 12x100G
8x100GE Octane 12x100GE Skyhammer
8-port 100GE with 4 NPU slices 12-port 100GE with 6 NPU slices
Compatible with all 99xx-series and 90xx-series chassis Support only for 99xx-series chassis
Has external TCAM for High Qos/ACL scale Has no external TCAM . Will use only 5Mb internal TCAM
ASR9000 NCS2k
Low Cost
Interconnect
SR10
CFP/CPAK SR10
transceiver CXP/CPAK
100GE Linecard Coherent Transponder
FCS
Mid-CY15
400G IPoDWDM LC Overview (Tomahawk Based LC)
Tomahawk based Linecard
Feature and scale parity with other TR and SE Tomahawk cards
2xCFP2 based DWDM ports (100G, 200G)
BPSK, QPSK, 16QAM modulation options
96 channels, ITU-T 50GHz spacing
FlexSpectrum support
HD FEC, SD FEC (3000+ km w/o regen)
20x10GE SFPP ports (SR, LR, ZR, CWDM, DWDM)
Flexible port options up to 400 Gbps total capacity
2 x 200G DWDM (CFP2) or
2 x 100G DWDM (CFP2) + 20 x 10G (SFP+) or
1 x 100G + 1x200G DWDM (CFP2) + 10 x 10G (SFP+)
OTN and pre-FEC FRR
Target FCS: mid-CY15 (5.3.2) for 100G DWDM
Tomahaw
Coherent HD-FEC
CFP2 Etna X240 k
FPGA FIA
200G capable
TCAM
#1 10GE SFP+
X240 SerDes
#20 10GE SFP+ Mux
SM15
NPMEM VOQ
Tomahaw
Coherent HD-FEC
CFP2 Etna X240 k
FPGA FIA
200G capable
TCAM
400Gbs IPoDWDM LC Internals Ivy Bridge
NPMEM
CPU Complex
VOQ
Tomahaw
#0
Coherent HD-FEC
CFP2 Etna X240 k
FPGA FIA
200G capable
TCAM
#1 10GE SFP+
X240 SerDes
#20 10GE SFP+ Mux
SM15
NPMEM VOQ
Tomahaw
Coherent HD-FEC
#1
CFP2 Etna X240 k
FPGA FIA
200G capable
TCAM
Tomahawk Per Slice MACSEC PHY Capability
MACSEC Security Standards Compliant with:
IEEE 802.1EA-2006
IEEE 802.1AEbn- 2011 (256-bit key)
IEEE 802.1AEbw-2013 (extended packet numbering)
MACSEC Links
MACSEC Links
Usecase #3 CE Port Mode MACSEC over L2VPN Usecase #4 VLAN Clear Tags MACSEC over L2VPN
Clear Frame
DA SA VLA PAYLOA FCS
N D
EFP1
Port 1 1
0
G Clear Frame
DA SA VLA PAYLOA FCS
Frame Encryption on Port 2 inside PHY N D
DA SA VLA
N
SEGTA
G
PAYLOA
D
ICV FCS EFP2 Fabric
1
Port 2 0
G PHY NPU
1
EFP3
Port 3 0
G
Encrypted EoMPLS PW
Frame bypass Port 3 MACSEC inside PHY
Phy Secure Channel VC DA SA VLA SEGTA PAYLOA ICV FCS
Loopback + Clear Tags DA SA VLA SEGTA PAYLOA ICV FCS Label N G D
N G D
(Cisco IPR)
Tomahawk MACSEC
Raw Performance
Tomahawk MACSEC
AES-GCN-256-bit Raw Performance (full-duplex) AES-GCN-256-bit Raw Scale
Per LC Slice 200Gbps Total MACSEC Ports 10G = 1,600
Raw Scale
Per System 40G = 320
Per LC Slot 800Gbps
100G = 160
Per Chassis ASR9006 = 3.2Tbps Total MACSEC SAs 10G Tx/Rx SAs = 51,200
ASR9010 = 6.4Tbps Per System 40G Tx/Rx SAs = 40,960
ASR9904 = 1.6Tbps 100G Tx/Rx SAs = 40,960
ASR9012 = 8Tbps
ASR9922 = 16Tbps
Customer Profile Tomahawk Performance
Generally target >3.3x performance of Typhoon system
Cust benchmark: 2x 100GE/Tomahawk NPU vs 6x 10GE/Typhoon NPU
Customer Tomahawk Typhoon LR Frame Performance Incr
Application Profile
Profile LR Frame @6x10G Ratio
128B Eth 196B Eth 225B Eth 233B Eth 449B Eth
149 123B Eth @
Tomahawk 240G @ @ @ @ @
mpps 174.6mpps
169mpps 115mpps 102mpps 104mpps 53.3mpps
178B Eth 300B Eth 205B Eth 316B Eth 445B Eth
45 148B Eth @
Typhoon 60G @ @ @ @ @
mpps 44.6mpps
37.8mpps 23.4mpps 33.4mpps 22.3mpps 16.1mpps
Perf Incr Ratio 4x 3.3x 4.48x 4.48x 3.07x 4.42x 3.91x 3.3x
All Platforms
9912, 9922
8x100GE
MOD400 12x100G
OTN*
8x100GE
Line Cards LAN PHY*
4x100GE 400G 8x100G
MOD200
OTN IPoDWDM 7-Fab
SFC2
Commons RSP880
RP2
Jan 2015 April 2015 August 2015 Nov 2015 Mar 2016
XR 5.3.0 XR 5.3.1 XR 5.3.2 XR 6.0.0 XR 6.1.0
* Some logical interface could apply qos policy, for example PWHE, BVI
** it could have main interface level simple flat qos co-exist with sub-interface level H-QoS on ingress direction
Tomahawk Line Card Port QoS Overview cont
Dedicated queue ASIC TM (traffic
manager) per NPU for QoS functions
NPU
-SE and -TR LC version has different queue FIA Switch
TM Fabric
buffer/memory size, different number of ASIC
queues
5 level hierarchy flexible queuing/scheduling support
5 level scheduling hierarchy:
Port groups (L0), Ports (L1), Logical Ports (L2), Subinterfaces (L3), Classes (L4)
Egress & Ingress, shaping and policing
Three strict priority scheduling with priority propagation
Flexible & granular classification, and marking
Full layer 2, full layer 3/4 IPv4, IPv6, mpls
5 Level Hierarchy QoS Queuing Overview
L0 L1 L2 L3 L4 L0, L1 level schedulers are automated
PG Port Logical Sub- Classes by TM, not user configurable
Port interfaces
Class
EFP1 C-VLAN Class Hierarchy levels used are determined
(S-Vlan
or Class
by how many nested levels a policy-
Vlans) C-VLAN Class map is configured for and applied to a
Port
given sub-interface
Class
EFP2 C-VLAN Class
(S-Vlan
or
Up to 16 classes per child/grandchild
Class
Vlans) C-VLAN Class level (L4)
Queue/Scheduler Hierarchy MQC Capabilities
L1 L2: 2-param L3: 3-param L4: 2-param
Shape (PIR, Shape Shape Shape, BRR W (Bw or BwR), Priority, WRED/Q-Limit
or Port BRR Weight Bandwidth
Shaper) (Bw or BwR) BRR W. Priority 1
P2
P3
Normal
Pri Qs
P1
P2
Normal
Pri Qs
QoS Classification Criteria
L2 Header Fields L3 Header Fields Internal Marking
L2 Inner/outer COS, Outer EXP Discard-class
Interfaces/EF inner/outer vlan, DSCP/TOS Qos-group
DEI TTL, TCP flags,
Ps Source/Destination MAC Source/destination L4 ports
address* Protocol
Or L3 match all/match any Source/Destination IPv4
Interfaces address*
Length/
Inter Frame Gap Preamble SFD DA SA VLAN Type Payload FCS
12 7 1 6 6 4 2 46-1500 4
Switch Fabric Architecture
1. Bandwidth and Redundancy Overview
2. Fabric QoS Virtual Output Queuing
Cisco ASR 9000 High Level System Architecture
At a Glance
Linecard
RSP/RP
CPU
CPU FIA
EP0 P
CPU Scalable & flexible
H
Y
NP FIA Slice based data plane
EP0 P
H
Y
NP FIA
SerDes
XBAR
Switch
SerDes Fabric
XBAR (SM15)
EP1 P Switch
H NP FIA Fabric
Y
EP1 P
(SM15)
Fully distributed &
H
Y
NP FIA Redundant system
Switch Fabric
integrated on RSP
or Separated
72
ASR 9006/9010 Switch Fabric Overview
3-Stage Non-Blocking Fabric (Separate Unicast and Multicast Crossbars)
Stage 1 Stage 2 Stage 3
Fabric frame format: Active-Active
Super-frame Fabric
Fabric load balancing:
Unicast
Unicast is per-packet
Multicast is per-flow Crossbar
8x55Gbps
fabric
fabric fabric
Arbiter FIA
FIA Multicast FIA
FIA RSP0
Crossbar FIA
FIA
Typhoon LC
Typhoon LC
fabric
8x55Gbps Egress Linecard
Ingress Linecard
Fabric bandwidth:
Arbiter
8x55Gbps =440Gbps/slot with dual RSP
RSP1 4x55Gbps =220Gbps/slot with single RSP
RSP440
73
ASR9k End-2-End System QoS Overview
End-to-End priority (P1,P2, 2xBest-effort) propagation
Unicast VOQ and back pressure
Unicast and Multicast separation
CPU CPU 4
NP PHY
2 3
NP PHY
FIA FIA
PHY NP Switch
Fabric
PHY NP1
1 2 3 4
Ingress Port 4 VOQ per each SFP virtual 4 Priority Egress Destination Egress Port
QoS port in the entire system Queues (DQs) per SFP (VQI) QoS
Up to 8K VOQs per TSK FIA virtual port, aggregated at
(vs 4k per SKT FIA) egress port rate
74
ASR9k Virtual Output Queuing (VoQ) System Architecture
VoQ Components (Where are they)
Egress NPU Backpressure and VoQ in Action
Result is No Head of Line Blocking (HOLB)
ASR9904 RSP880 Switch Fabric Architecture
Active/Active 3-Stage Fabric, Scale to 1.6Tbps LCs Fabric frame format:
Stage 1 Stage 2 Stage 3 Super-frame
Fabric load balancing:
Unicast is per-packet
Multicast is per-flow
Ingress Linecard 2x 5x 115Gbps
Egress Linecard
Fabric ~ 1.15Tbps
SM15
Arbiter
FIA FIA
FIA Fabric Fabric FIA
FIA SM15
RSP880
SM15 FIA
77
ASR90xx RSP880 and Mixed LC Operation
Fabric frame format:
Super-frame
Stage 1 Stage 2 Stage 3 Fabric load balancing:
Unicast is per-packet
Multicast is per-flow
Egress Linecard
Ingress Linecard Fabric 8x115Gbps
SM15
Fabric
Arbiter
FIA
FIA Fabric FIA
FIA RSP880 SM15 FIA
FIA
Tomahawk Line
Typhoon Linecard Card
Fabric
SM15
78
ASR90xx RSP440 and Mixed LC Operation
Fabric frame format:
Stage 1 Stage 2 Stage 3 Super-frame
Fabric load balancing:
Unicast is per-packet
Multicast is per-flow
Egress Linecard
Ingress Linecard 8x55Gbps
fabric
fabric Arbiter
FIA
FIA Fabric FIA
FIA RSP0 SM15 FIA
FIA
Tomahawk Line
Typhoon Linecard Card
fabric
79
ASR99xx Switch Fabric Card (FC2) Overview
6+1 All Active 3-Stage Fabric Planes, Scale to 1.6Tbps LCs
Fabric frame format:
Super-frame
5x2x115G bi-directional
Fabric load
= 1.15Tbps
balancing:
Unicast is per-packet
Multicast is per-flow
FIA
FIA
FIA Fabric Fabric FIA
SM15 SM15 FIA
FIA
Tomahawk Line Tomahawk Line
Card Card
80
ASR9922/12 SFC2 and Mixed Gen LCs
When using 3rd Gen Fabric Cards
(5-1)x2x115G bi-directional
= 920Gbps (protected)
FIA
FIA FIA
FIA Fabric
SM15 FIA
fabric FIA
Typhoon Linecard Tomahawk Line
Card
81
ASR9K Tomahawk Module
Fabric Redundancy and Bw Allocation Summary for 8x100G LCs with
RSP880s/SFCv2
Punt Switch
Control 3x10GE
SFP +
Typhoo
LPTS
n
FIA
packet 3x10GE
SFP +
NP
3x10G RP CPU: Routing, MPLS, IGMP, PIM,
E NP
Fabric ASIC
Switch
SFP +
3x10GE FIA HSRP/VRRP, etc
SFP +
NP
3x10GE
SFP +
NP LC CPU: ARP, ICMP, BFD, NetFlow,
FIA
3x10GE
SFP +
NP OAM, etc
3x10GE
SFP +
NP
FIA
3x10GE
SFP +
NP
84
Layer 3 Control Plane Overview
BGP OSPF
LDP RSVP-TE
Static
ISIS EIGRP
LSD RIB RP
3x
3x10GE
10G
Typho
SFP + on
3x10GE
3x
Typho FIA
10G Ingress
SFP + on FIA Typhoo 100
3x G 100GE
3x10GE
10G
Typho n
ASIC
Switch Fabric
SFP + MAC/P
on
HY
3x
Typho FIA Switch Egress
ASIC
Switch Fabric
3x10GE
10G Fabric Typhoo 100
SFP + on FIA
n G
3x
3x10GE
10G
Typho
SFP + on Ingress
3x10GE
3x
Typho FIA FIA Typhoo 100
10G n
SFP + on G 100GE
3x
Typho MAC/P
3x10GE
10G Egress HY
SFP + on
3x FIA Switch FIA Typhoo 100
3x10GE
10G
Typho Fabric n G
SFP + on
L3 Unicast Forwarding
Packet Flow (Simplified) Example
from wire
Rx LAG hashing
lookup key LAGID SFP Packet rewrite
LAG System headers added
L3: (VRF-ID, IP DA)
ECH Type:
L3_UNICAST
TCAM rxIDB L3FIB rx-adj rewrite
SFP
Packet Source L3 FIB Next-hop Switch Fabric Port
classification interface info lookup (egress NPU)
SFP
ACL and QoS Lookup
Ingress NPU also happen in parallel
Fabric
Tx LAG hashing
LAG
ECH Type:
L3_UNICAST
rewrite txIDB tx-adj L3FIB
=> L3FIB lookup
destination Next-hop L3 FIB
interface info lookup
to wire ECH type: tell egress NPU type of lookup it should execute
L3 Multicast Control Plane
ASR9k doesnt use inferior binary tree or root uniary tree replication model
FGID (Slotmask)
FGIDs: 10 Slot Chassis FGIDs: 6 Slot Chassis
Phy
Logical
Slot
Slot
Number Logical
5 Slot
LC 3
4 LC 2
LC 7
LC 6
LC 5
LC 4
RSP 0
RSP 1
LC 3
LC 2
LC 1
LC 0
3 LC 1
2 LC 0
9 8 7 6 5 4 3 2 1 0 1 RSP 1
0 RSP 0
3x
3x10GE
10G
Typho
SFP + on
3x10GE
3x
Typho FIA
10G Ingress
SFP + on FIA Typhoo 100
3x G 100GE
3x10GE
10G
Typho n
ASIC
Switch Fabric
SFP + MAC/P
on
HY
3x
Typho FIA Switch Egress
ASIC
Switch Fabric
3x10GE
10G Fabric Typhoo 100
SFP + on FIA
n G
3x
3x10GE
10G
Typho
SFP + on Ingress
3x10GE
3x
Typho FIA FIA Typhoo 100
10G n
SFP + on G 100GE
3x
Typho MAC/P
3x10GE
10G Egress HY
SFP + on
3x FIA Switch FIA Typhoo 100
3x10GE
10G
Typho Fabric n G
SFP + on
IOS-XR Architecture
1. 32-bit and 64-bit OS
2. IOS-XRv 9000 Virtual Forwarder
3. Netconf/Yang Programmability
Cisco IOS A Recap
Cisco IOS Cisco IOS-XE Cisco IOS-XR Cisco Virtual IOS-XR
Control Data Mgmt
Plane Plane Plane XR Code v1 XR Code v2
Hosted App 1
Hosted App 2
IOSd
NetFlow
SNMP
OSPF
LPTS
XML
BGP
NetFlow
QoS
NetFlow
ACL
PIM
SNMP
SNMP
OSPF
OSPF
LPTS
LPTS
BGP
BGP
XML
XML
QoS
ACL
QoS
ACL
PIM
PIM
System
IOS Blob Admin
Virtualization Layer
Admin Config
RP/0/RP0/CPU0:router(admin-config)#
sdr backbone location 0/5/*
pairing reflector location 0/3/* 0/4/*
Cisco IOS XR (Virtualized)
Distributed system architecture
Cisco Virtual IOS-XR
Scale, fault isolation, control plane expansion
XR Code v1 XR Code v2
Enhanced OS Infrastructure
Scale, SMP support, 64-bit CPU Support, Open Source apps
Virtualization
NetFlow
NetFlow
SNMP
SNMP
OSPF
OSPF
LPTS
LPTS
BGP
BGP
XML
QoS
XML
ACL
QoS
ACL
PIM
PIM
System
ISSU, control and admin plane separation, simplifies SDR
Admin
Architecture
ISSU and HA Architecture
Provide Zero Packet Loss (ZPL) and Zero Topology Loss (ZTL) to Distributed Infra Distributed Infra
avoid service outages Kernel Kernel Kernel
Linux, 64bit Linux, 64bit Linux, 64bit
Fault Management
Carrier class fault handling, correlation and alarm management
Available since IOS XR 5.0 on NCS6K Virtualization Layer
Other platforms rollout NCS4K, ASR9K, Skywarp, Fretta,
Sunstone and Rosco
IOS-XRv 9000: Efficient Virtual Forwarder
High-end Feature Rich Data Plane on x86
Innovative Virtual Forwarder IOS-XRv 9000
x86-optimized SW based hardware assists:
2x10G Line Rate FDX PCIe pass-through IOS-XRv Control Plane
SW hierarchical traffic manager with 3 level HQoS, High speed interface
512K queues @ 20G FDX performance per core classification
and fine grained load balancing
SW policers that is color aware and nearly IOS-XRv Virtual Forwarder
4x faster than DPDK based SW routers
Hierarchical QOS Scheduler
SW TCAM with logical super key & heuristic cuts RX & Traffic 30Gbps+ throughput
algorithms Interface Manager TM on a single CPU core
Classification & TX million Queues
Data plane optimized for fast convergence 20Gbps+ 3-Layer H-QOS
forwarder with features for IMIX traffic with features
(on a single socket) Forwarding
Forwarding and Feature Path
& Features
ACLs
Portable 64bit C-code (to ARM based platforms) uRPF
TCAM PLU Pkt. replication Marking, Policing
Common code base with Cisco nPower X family IPv4, IPv6, MPLS
Segment routing
BFD
SW based HW Assists
NETCONF/YANG Supported on XR
NETCONF NETwork CONFiguration Protocol
Network Management protocol defines management
operations
Initial focus on configuration, but extended for monitoring
operations
First standard - RFC 4741 (December 2006)
N
Latest rev is RFC 6241 (June 2011) E
Does not define content in management operations YANG Data T
C
YANG Yet Another Next Generation
Data modeling language to define NETCONF payload
O
Defined in the context of NETCONF, but not tied to NETCONF N
Addresses gaps in SMIv2 (SNMP MIB language) F
Previous failed attempt SMI NG
First approved standard - RFC 6020 (October 2010)
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