CpE 5210

Introduction to VLSI Design

Topic 1: Introductions

Chulsoon Hwang
EMC Laboratory
hwangc@mst.edu

1
Credits
Much of the information in the slides for this class have
been sourced from the web and the textbook

CMOS VLSI Design: A Circuits and Systems

Perspective, N. Weste, D. Harries, Addison-Wesley, 4th
edition, 2011.

Lecture notes 2011 David Money Harris

Lecture notes 2015 Daryl Beetner

2
Introduction

Integrated circuits: many transistors on one chip

Very Large Scale Integration (VLSI)

Complementary Metal Oxide Semiconductor (CMOS)

Fast, cheap, low-power transistor circuits

3
A Brief History
1958: First integrated circuit
Flip-flop using two transistors
Built by Jack Kilby at Texas Instruments

2010
Intel Core i7 processor
2.3 billion transistors
64 Gb Flash memory
> 16 billion transistors

4
Invention of the Transistor
Vacuum tubes ruled in first half of 20th century
Large, expensive, power-hungry, unreliable

1947: first point contract transistor

John Bardeen and
Walter Brattain
at Bell Labs

5
MOS Integrated Circuits
1970s processes usually had only nMOS transistors
Inexpensive, but consume power while idle
1980s-present: CMOS processes for low idle power

Intel 1101 256-bit SRAM Intel 4004 4-bit Proc

6
Moores Law
1965: Gordon Moore plotted transistor on each chip
Fit straight line on semi-log scale
Transistor counts have doubled every 26 months

Integration Levels

SSI: 10 gates

MSI: 1000 gates

LSI: 10,000 gates

VLSI: > 10k gates

http://www.intel.com/content/www/us/en/silicon-innovations/moores-law-technology.html 7
Feature Size
Minimum feature size shrinking 30% every 2-3 years

8
Corollaries
Many other factors grow exponentially
Ex: clock frequency, processor performance

9
Recent Microprocessor

Pentium 4 Core i7
180-65nm process 45-14nm process
10
Fun Facts
You could fit more than 4000 of 22nm transistors
across the width of a human hair
Human hair is 80-90 microns in diameter

Human
Hair

. ~90 m 22nm

.
feature

http://download.intel.com/newsroom/kits/22nm/pdfs/22nm_Fun_Facts.pdf 11
How Does an IC Look Like from the Inside?

Intel 90 nm Stack
12
A Wafer

Single die
The smaller the better

Wafer
The bigger the better

http://www.amd.com/ 13
Packages

14
Silicon Lattice
Transistors are built on a silicon substrate
Silicon is a Group IV material
Forms crystal lattice with bonds to four neighbors

15
Dopants
Silicon is a semiconductor
Pure silicon has no free carriers and conducts poorly
Adding dopants increases the conductivity
Group V: extra electron (n-type)
Group III: missing electron, called hole (p-type)

16
p-n Junctions
A junction between p-type and n-type semiconductor
forms a diode.
Current flows only in one direction

p-type n-type

anode cathode

17
Transistor Types
Bipolar transistors
npn or pnp silicon structure
Small current into very thin base layer controls large currents
between emitter and collector
Base currents limit integration density

Metal Oxide Semiconductor Field Effect Transistors

nMOS and pMOS MOSFET
Voltage applied to insulated gate controls current between
source and drain
Low power allows very high integration

18
nMOS Transistors
Four terminals: gate, source, drain, body
Gate oxide body stack looks like a capacitor
Gate and body are conductors
SiO2 (oxide) is a very good insulator
Called metaloxidesemiconductor (MOS) capacitor
Even though gate is no longer made of metal
Source Gate Drain
Polysilicon
SiO2

n+ n+
Body
p bulk Si
19
nMOS Operation
Body is usually tied to ground (0 V)
When the gate is at a low voltage:
P-type body is at low voltage
Source-body and drain-body diodes are OFF
No current flows, transistor is OFF

Source Gate Drain

Polysilicon
SiO2

0
n+ n+
S D
p bulk Si

20
nMOS Operation Cont.
When the gate is at a high voltage:
Positive charge on gate of MOS capacitor
Negative charge attracted to body
Inverts a channel under gate to n-type
Now current can flow through n-type silicon from source
through channel to drain, transistor is ON
Source Gate Drain
Polysilicon
SiO2

1
n+ n+
S D
p bulk Si
21
pMOS Transistor
Similar, but doping and voltages reversed
Body tied to high voltage (VDD)
Gate low: transistor ON
Gate high: transistor OFF
Bubble indicates inverted behavior

Source Gate Drain

Polysilicon
SiO2

p+ p+

n bulk Si
22
Power Supply Voltage
GND = 0 V
In 1980s, VDD = 5V
VDD has decreased in modern processes
High VDD would damage modern tiny transistors
Lower VDD saves power
VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0,

23
Transistors as Switches
We can view MOS transistors as electrically controlled
switches
Voltage at gate controls path from source to drain

g=0 g=1

d d d
nMOS g OFF
ON
s s s

d d d

pMOS g OFF
ON
s s s
24
CMOS Inverter

A Y VDD
0 1
1 0 OFF
ON
0
1
A Y
ON
OFF

A Y
GND
25
CMOS NAND Gate

A B Y
0 0 1 ON
OFF
OFF
ON OFF
ON
0 1 1
1
Y
0
1 0 1 ON
A OFF
1 1 0 0
1
1
0 OFF
ON
B ON
OFF

26
CMOS NOR Gate

A B Y
0 0 1 A
0 1 0
1 0 0 B
1 1 0 Y

27
3-input NAND Gate
Y pulls low if ALL inputs are 1
Y pulls high if ANY input is 0

Y
A
B
C

28
CMOS Fabrication
CMOS transistors are fabricated on silicon wafer
Lithography process similar to printing press
On each step, different materials are deposited or
etched
Easiest to understand by viewing both top and cross-
section of wafer in a simplified manufacturing process

29
Inverter Cross-section
Typically use p-type substrate for nMOS transistors
Requires n-well for body of pMOS transistors

A
GND VDD
Y SiO2

n+ diffusion

p+ diffusion
n+ n+ p+ p+
polysilicon
n well
p substrate
metal1

nMOS transistor pMOS transistor

30
Well and Substrate Taps
Substrate must be tied to GND and n-well to VDD
Metal to lightly-doped semiconductor forms poor
connection called Shottky Diode
Use heavily doped well and substrate contacts / taps

A
GND VDD
Y

p+ n+ n+ p+ p+ n+

n well
p substrate

well
substrate tap
tap

31
Inverter Mask Set
Transistors and wires are defined by masks
Cross-section taken along dashed line

GND VDD

nMOS transistor pMOS transistor

substrate tap well tap

32
Detailed Mask Views
Six masks
n-well
n well

Polysilicon
n+ diffusion
p+ diffusion Polysilicon

Contact n+ Diffusion

Metal
p+ Diffusion

Contact

Metal

33
Fabrication
Chips are built in huge factories called fabs
Contain clean rooms as large as football fields

Courtesy of International
Business Machines Corporation.
Unauthorized use not permitted.

34
Layout
Chips are specified with set of masks
Minimum dimensions of masks determine transistor
size (and hence speed, cost, and power)
Feature size f = distance between source and drain
Set by minimum width of polysilicon
Feature size improves 30% every 3 years or so
Normalize for feature size when describing design
rules
Express rules in terms of = f/2
E.g. = 0.3 m in 0.6 m process

35
Simplified Design Rules
Conservative rules to get you started

36
Inverter Layout
Transistor dimensions specified as Width / Length
Minimum size is 4 / 2, sometimes called 1 unit
In f = 0.6 m process, this is 1.2 m wide, 0.6 m long

37