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SEE 1223

SULIT

UNIVERSITI TEKNOLOGI MALAYSIA

FINAL EXAMINATION SEMESTER 2
SESSION 2010/2011

COURSE CODE : SEE 1223

COURSE : DIGITAL ELECTRONIC

LECTURERS : MR. AMERUDDIN BAHAROM

DR. AZLI YAHYA
DR. EILEEN SU LEE MING
MR.JAMEEL ABDULLA AHMED MUKRED
MR. MUHAMMAD ARIF ABD. RAHIM
DR. SHARIFAH HAFIZAH SYED ARIFFIN

COURSE : SET / SEM / SEE / SEC / SEI / SEP/ SWB

SECTIONS : 01 / 02 / 03 / 04 / 05/ 10

TIME : 2 HOURS

DATE :

INSTRUCTIONS :

ANSWER ALL QUESTIONS IN SECTION A AND THREE QUESTIONS FROM

SECTION B. ALL WORKINGS MUST BE SHOWN CLEARLY IN THE ANSWER
SHEET

THIS QUESTION PAPER CONSISTS OF 11 PAGES ONLY

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SECTION A [40 marks]

1. Convert

(i) (10110)Gray code to BCD.

[4 marks]
(ii) 57428 to hexadecimal.
[4 marks]

2. The pin diagram of 7400 chip (quad 2-input NAND gates) is shown in Figure A(i).
Copy the diagram on your answer script and identify pin 1 and pin 14 as well as the
DC supply VCC and GND pins on the diagram.
[4 marks]

Figure A(i)

3. By using Boolean algebra,

(i) simplify A.B + A.(B + C) + B.(B + C) .

[3 marks]
(ii) prove that A + B = A + A.B .
[3 marks]

4. F(A,B,C,D) = (1, 3, 5, 9, 13, 15) and don't care = D(2, 4, 7, 12, 14).

(i) Obtain the minimized POS expression using the K-map.

[4 marks]
(ii) Implement the minimized function in NOR-NOR configuration.
[3 marks]
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5. A medium scale integrated circuit (MSI circuit) accepts four inputs and produces two
outputs as shown in the Table A(i). X indicates dont care conditions. Give a suitable
name for this circuit.
[3 marks]

Table A(i)
I3 I2 I1 I0 O1 O0
0 0 0 1 0 0
0 0 1 X 0 1
0 1 X X 1 0
1 X X X 1 1

6. Figure A(ii) shows a 4-1 multiplexer with a D flip-flop. Copy the diagram on your
answer script and show how these two devices can be connected to become a J-K flip-
flop. The J and K inputs are connected to the select bits S1 and S0 respectively. You
can't use any additional gates.
[4 marks]

I0 D0 Q0
I1
I2 F
I3 Q0
S1 S0

Figure A(ii)

7. Figure A(iii) is a logic symbol of a 4-bit parallel adder. If X [X3..X0]= 1111 and
Y[Y3..Y0] = 0101, show how this chip can be used as a 4-bit subtractor X - Y. Copy
the diagram on your answer script and label the diagram with the input and output
values. [Hint : 2's complement = 1's complement + 1]
[4 marks]
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X3 X2 X1 X0

A3 A2 A1 A0 B3 B2 B1 B0
Cin
Cout S3 S2 S1 S0

Figure A(iii)

8. A hybrid home theatre system is shown in Figure A(iv). A compact disc (CD) is read
by the CD drive. What is the

(i) type of data stored on the CD?

[1 mark]
(ii) function of the converter?
[1 mark]
(iii) component marked X?
[1 mark]
(iv) advantage of a hybrid system?
[1 mark]

CD drive speaker

Converter X

Figure A(iv)
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SECTION B [60 marks]

Question 1

(a) A student is required to simplify a Karnaugh map. He tries to form groups of 1s as

shown in Figure Q1(a)
CD
AB 00 01 11 10

00 1 0 X 0

01 0 1 1 1

11 0 1 1 1

10 1 0 X 0

Figure Q1(a)

(i) Explain the mistakes done by the student.

[4 marks]
(ii) Obtain the correct Boolean equation from the map.
[3 marks]

(b) The block diagram and the truth-table of a combinational logic circuit are shown in
Figure Q1(b) and Table Q1 respectively.

A1 P8

A0 P4

B1 P2

B0 P1

Figure Q1(b)
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Table Q1
A1 A0 B1 B0 P8 P4 P2 P1
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 0
0 0 1 0 0 0 0 0
0 0 1 1 0 0 0 0
0 1 0 0 0 0 0 0
0 1 0 1 0 0 0 1
0 1 1 0 0 0 1 0
0 1 1 1 0 0 1 1
1 0 0 0 0 0 0 0
1 0 0 1 0 0 1 0
1 0 1 0 0 1 0 0
1 0 1 1 0 1 1 0
1 1 0 0 0 0 0 0
1 1 0 1 0 0 1 1
1 1 1 0 0 1 1 0
1 1 1 1 1 0 0 1

(i) Obtain the minimized SOP expression for output P2 using Karnaugh Map.
[4 marks]
(ii) Implement P2 in NAND-NAND configuration.
[3 marks]
(iii) Implement P1 using one 4-to-1 multiplexer only without any additional gates.
[4 marks]
(iv) Suggest a suitable name for the combinational logic circuit operation.
[2 marks]
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Question 2

(a) A 2-to-4 line decoder (active-HIGH output) and an OR gate can be used to realize the
function F(A, B) = M (1, 3) . By using your inspired creative and innovative minds,
show how this same function can be implemented using a 3-to-8 line decoder (active-
HIGH output) shown in Figure Q2(a) with 2-input OR gates only. A and B should be
connected to the select bits S2 and S1 of the decoder respectively.
[6 marks]

O0
O1
S2 O2
O3
S1
O4
S0
O5
O6
O7

Figure Q2(a)

(b) Consider a circuit shown in Figure Q2(b).

A Q

B Q

Figure Q2(b)

(i) Identify the type of circuit, draw the logic symbol and write down the truth
table for this particular circuit.
[3 marks]
(ii) Using the logic symbol drawn in part (i), construct the simplest positive edge-
triggered J-K flip-flop. You may add additional gates, if necessary. Show also
the positive edge-triggering circuit and draw the logic symbol.
[3 marks]
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(iii) By using the logic symbol of J-K flip-flop in part(ii), show how this flip-flop
can be modified to make a D and a T flip-flops.
[2 marks]

(c) Sketch the output waveforms Q1 and Q2 for four clock pulses for the circuit shown in
Figure Q2(c). Q1 and Q2 are initially 0.
[6 marks]

D Q1

J Q2

K
CLK

Figure Q2(c)
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Question 3

The state transition diagram of a counter is shown in Figure Q3(a)

010 100 110

000 001
111 101 011

Figure Q3(a)

(a) Give two advantages of designing the counter using D flip-flops instead of J-K flip-
flops.
[4 marks]

D0 Q0
Combinational
D1 logic circuit Q1

D2 Q2

D2 Q2

Q2

D1 Q1

Q1

D0 Q0

Q0

CLK

Figure Q3(b)
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(b) The block diagram of the counter for the given state transition diagram is shown in
Figure Q3(b).

(i) What is the purpose of the combinational logic circuit?

[2 marks]
(ii) Design the combinational logic circuit using only 4-to-1 multiplexers.
[12 marks]
(iii) What is the advantage of using multiplexers instead of basic gates for the
combinational logic circuit?
[2 marks]
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Question 4

(a) (i) Show how a NOT function is implemented using each of the following gates;
2-input NOR gate, 3-input NAND gate and 2-input XOR gate.
[6 marks]
(ii) Implement a 3-input OR function using minimum number of 2-input
NAND gates only.
[4 marks]

(b) A ROM circuit to implement various logic operations is shown in Figure Q4.

(i) What is the ROM size?

[2 marks]
(ii) Explain how the ROM can be configured so that it can function as a 2-input
NAND gate and also 2-input XOR gate.
[4 marks]
Address ROM
decoder matrix

O0 1 0 0
O1 0 1 0

SEL S2 O2 0 1 0

A S1 O3 0 0 1
O4 1 1 0
B S0
O5 1 0 1
O6 1 0 1
O7 0 1 1

F2 F1 F0

Figure Q4

(iii) The ROM also stored the data for a 1-bit full-adder. Explain how you can
retrieve the data for the full-adder.
[4 marks]
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APPENDIX

BOOLEAN ALGEBRA

Boolean's Theorem
Theorem 1 A0A A.1 A
Theorem 2 A A 1 A.A 0
Theorem 3 AAA A.A A
Theorem 4 A 1 1 A.0 0
Theorem 5 AA
Theorem 6 A B B A A.B B.A
Theorem 7 A (B C) (A B) C A.(B.C) (A.B).C

Theorem 8 A.(B C) A.B A.C A B.C (A B).(A C)

Theorem 9 A A.B A A.(A+B)=A
Theorem 10 A A.B A B A.(A B) A.B

DeMorgan's Theorem

(i) A.B A B

(ii) A B A.B