6 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO.

1, JANUARY 2010

Design of Parallel Inverters for Smooth Mode

Transfer Microgrid Applications
Chien-Liang Chen, Student Member, IEEE, Yubin Wang, Member, IEEE, Jih-Sheng (Jason) Lai, Fellow, IEEE,
Yuang-Shung Lee, Member, IEEE, and Daniel Martin, Student Member, IEEE

AbstractIn this paper, smooth mode transfers and accurate Gv (s) Outer voltage controller in standalone mode
current sharing are performed in a multi-inverter-based microgrid (islanding mode).
system by the designed system level controls with control area net- Gv i (s) Inverter-side-inductor-current-to-capacitor-
work communication. Controllers of individual inverters within the
microgrid in both grid-tie and islanding modes are also designed voltage transfer function.
to ensure high-quality output waveforms. The mode transfer tests Gv o lo op (s) Open voltage loop gain.
are conducted with an inverter-simulated grid to define the proper Hi Current feedback gain.
transfer procedures. Experimental results show that the invert- Hv Voltage feedback gain.
ers can provide stable outputs in different basic microgrid opera- iacn Inverter-side inductor current for nth dis-
tion modes. With the designed current sharing scheme, the output
current is equally shared among paralleled inverters without no- tributed generation (DG) unit.
ticeable circulating current. Both the simulation and experimental igrid Grid current flowing through the common-
results of mode transfer show that the multi-inverter-based micro- coupling point of the microgrid system.
grid system is able to smoothly switch between the grid-tie and iload Load current for the microgrid system.
islanding modes to guarantee an uninterrupted power supply to ioutn Output current for nth DG unit.
the critical loads within the microgrid.
Rload Critical load of the microgrid system.
Index TermsGrid-tie inverter, islanding, microgrid system, Ti g (s) Compensated current loop gain in grid-tie
mode transfer, parallel inverters. mode.
Ti s (s) Compensated current loop gain in standalone
NOMENCLATURE mode (islanding mode).
vacn Capacitor voltage for nth DG unit.
Fm DSP modulation gain.
vbus Bus voltage for the microgrid system.
Gi c lo op g (s) Closed current loop gain in grid-tie mode.
Vdcn DC-link voltage for nth DG unit.
Gi c lo op s (s) Closed-current-loop gain in standalone mode
vgrid Grid voltage on the common-coupling point
(islanding mode).
of the microgrid system.
Gid (s) Control-to-inverter-side-inductor-current
Vin-n Input voltage for nth DG unit.
transfer function.
Gi o lo op (s) Open current loop gain.
Giv (s) Capacitor-voltage-to-inverter-side-inductor- I. INTRODUCTION
current transfer function. TYPICAL microgrid consists of multiple paralleled dis-
Gi g (s)
Gi s (s)
Current controller in grid-tie mode.
Inner current controller in standalone mode
A tributed generation (DG) units that can be operated in both
grid-tie and islanding modes. The ability of switching between
(islanding mode). grid-tie and islanding modes is the key to guarantee uninter-
Glf (s) Transfer function for hardware low-pass rupted power to critical loads within the mircogrid [1][5]. The
filters. interface between the DG units and the existing grid can be
a rotational machine with relatively large inertia and slow dy-
Manuscript received December 14, 2008; revised March 23, 2009. Current
version published January 29, 2010. This paper was presented in part at the namics, or a power inverter with passive low-pass filters that has
24th IEEE Applied Power Electronics Conference and Exposition, Washington, nearly zero inertia and a cutoff frequency that is much higher
DC, February, 1519, 2009. Recommended for publication by Associate Editor than the fundamental frequency. As compared to the rotational-
T. Shimizu.
C.-L. Chen, J.-S. Lai, and D. Martin are with the Future Energy Electronics machine-based DG units, the inverter-based DG units tend to
Center, Virginia Polytechnic Institute and State University, Blacksburg, VA have faster dynamics, but smaller output impedance; therefore,
24061-0111 USA (e-mail: jlchen99@vt.edu). it can quickly switch between grid-tie and islanding modes.
Y. Wang was with the Future Energy Electronics Center, Virginia Polytechnic
Institute and State University, Blacksburg, VA 24061-0111 USA. He is now with However, it is susceptible to a large switching transient dur-
the School of Electrical Engineering, Shandong University, Shandong 250061, ing transition. Unlike the rotational-machine-based DG units,
China. which normally rely on the droop control method to balance
Y.-S. Lee is with the Future Energy Electronics Center, Virginia Polytechnic
Institute and State University, Blacksburg, VA 24061-0111 USA, and also with the voltage and adjust the current sharing, the inverter allows
the Department of Electronics Engineering, Fu-Jen Catholic University, Taipei operating modes to switch between voltage and current modes;
242, Taiwan. thus, the current sharing control has more DOFs. On the other
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org. hand, the mode changes with a fast dynamics, and a low out-
Digital Object Identifier 10.1109/TPEL.2009.2025864 put impedance tend to produce very large current transients and
0885-8993/$26.00 2010 IEEE

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CHEN et al.: DESIGN OF PARALLEL INVERTERS FOR SMOOTH MODE TRANSFER MICROGRID APPLICATIONS 7

can easily upset or damage the electronics. Therefore, how to

take advantage of fast inverter operation while avoiding large
transients during mode transfer is very important for paralleling
inverter-based DG units in a microgrid system.
The approaches to paralleling multiple inverters can be found
in the design of high-power uninterruptible power systems
(UPSs). Different current-sharing control techniques have been
derived from conventional UPS inverter paralleling methods.
Although some of these techniques can be employed for parallel-
ing DG units, it should be noted that the conventional UPS does
not need to tie to the grid, and thus, the low source impedance and
mode-transition-induced transients do not exist. Another unique
problem found in microgrid systems is how to transmit the com-
mand signals among inverters separated far apart. Therefore,
paralleling microgrid inverters is much more challenging than
paralleling UPS inverters. Major design challenges are found
in: 1) precision power flow control; 2) proper current sharing;
and 3) smooth transition between grid-tie and islanding modes. Fig. 1. Microgrid architecture.
Precision power flow control in the grid-tie mode is nor-
switch, which reduces the disconnect time from grid-tie mode
mally not a problem in a three-phase system because the direct-
to islanding mode. Once the grid recovers, the microgrid should
quadrature (dq) transformation technique can be adopted to ob-
reconnect back to the utility without harming the system. In
tain power components in dc quantities, and the conventional
order to minimize the transients, the phase-locked loop (PLL)
proportionalintegral (PI) controller can be applied to obtain
design and the mode transfer procedure were proposed in [22]
high gains to eliminate the steady-state error. For single-phase
and [23]. An admittance compensation is proposed in [24] to
systems, however, the dq transformation is not straightforward,
reduce the transients during the startup of grid connection. By
and tends to produce large steady-state error and high harmonic
controlling the peak value of the output current with an inner
distortion. The solution is to provide a high loop gain at desired
voltage loop, the indirect current control can achieve smooth
frequencies with proportionalresonant (PR) controllers [6], [7]
mode transfers between the two modes [25].
or to use dq-transformation by adding a quadrature compo-
Past studies on microgrid operation typically focused on a
nent [8], [9].
single inverter with a single power conditioning system for
For proper current sharing in islanding-mode operation, con-
islanding operation or mode transfers between islanding and
ventional solutions for UPS [10][15] can be applied. Large
grid-tie modes. In this paper, the mode transfers are performed
inverter-based microgrid systems with ratings higher than 100
in a multiple inverter-based microgrid system that emulates real
kW utilize the droop control [10][12] to share loads with-
microgrid system operation. The complete system including an
out communication lines. However, the load sharing capabil-
upper level controller that assigns each inverter to run in voltage
ity of droop method may be degraded if the load changes or
or current loop control, a current sharing control, and the mode
the line impedance changes. For small-rating parallel inverters,
transfer algorithm is implemented with the robust CAN com-
current sharing is typically commanded through internal com-
munication. The controller designs for both grid-tie and island-
munication channels or interfaces with different implementation
ing modes for the microgrid system are described in detail. The
schemes including centralized, masterslave, average-load shar-
mode transfer tests are conducted with an inverter-simulated grid
ing, and circular-chain controls to achieve better current sharing
to define the proper transfer procedures. The operation of the
capability [13], [14]. However, the transmission distance for
proposed microgrid system is verified with both simulation and
loadcurrent sharing commands is quite limited with the ac sig-
experimental results. The intent of this paper is to present a prac-
nal transmission. In order to extend the transmission distance,
tical single-phase inverter-based microgrid system that ensures
a load sharing scheme was proposed to transmit the dc quantity
smooth mode transfer between islanding and grid-tie modes,
through a controller area network (CAN) bus among paralleled
while maintaining accurate current sharing and high-quality out-
inverters [15]. This method substantially helps to extend the
put waveforms. The size of the studied system is suitable for a
transmitting distance with sufficiently fast transmission speed.
small community, a building complex, or an industrial park.
For mode transfer between grid-tie and islanding modes, the
first step is to determine when the microgrid should operate in
the grid-tie or islanding mode. Islanding detection can be clas- II. MICROGRID ARCHITECTURE AND OPERATIONS
sified into passive, active, and communication-based detection Fig. 1 shows a paralleled power-conditioning-system-based
schemes [16][19]. When the grid is in an abnormal condition, microgrid architecture consisting of two fuel cell power condi-
the microgrid needs to switch from grid-tie to islanding mode tioning systems, an upper level controller, CAN bus, a static
within the required clearing time [20]. A method is proposed switch, and other DG units. An upper level controller per-
in [21] to have inverters generate a voltage difference on the forms monitoring and power management through the CAN bus.
output inductors to facilitate the turn OFF process of a static According to the load types, critical loads and noncritical loads

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8 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 1, JANUARY 2010

hardware filter and antialiasing filter, respectively. By choosing

a PR controller to reduce the steady-state error [6], [7], the com-
pensated loop gain in grid-tie mode Ti g (s) can be represented
in (2). The PR controller uses proportional gain to adjust the
gain for all-frequency signals, and resonant gain provides the
desirable gain at specific frequency by two complex poles
Ti g (s) = Gi g (s) Gi o lo op (s) (2)
where
2c kr s
Gi g (s) = kp +
s2 + 2c s + 12
Fig. 2. Power conditioning system connected in (a) grid-tie mode and where kp , kr , c , and 1 are the proportional gain, resonant
(b) islanding mode. gain, equivalent bandwidth, and fundamental angular frequency,
respectively. For the system under test, HW F = 301.59
can be separated by a solid-state relay (SSR). If the grid is in nor- 1000 rad/s, ANF = 60.32 1000 rad/s, Vdc = 420 V, rL i =
mal condition, the microgrid system can not only supply power 80 m, and Li = 1 mH. By choosing kp = 0.78, kr = 97.5,
to the loads but also exchange power with the grid through the c = 10 rad/s, and 1 = 377 rad/s in Gi g (s), the Bode plots
SSR. If the grid is abnormal, the microgrid system needs to dis- of Gio lo op (s) and Ti g (s) can be shown in Fig. 3(b).
connect from the grid and keep supporting critical loads through
load distributing schemes. IV. VOLTAGE DUAL-LOOP CONTROLLER
A more detailed view of each power conditioning system run- FOR ISLANDING OPERATION
ning in the grid-tie and islanding modes is shown in Fig. 2(a) and
(b), respectively. Because the grid voltage is known in the grid- As shown in Fig. 4, a dual-loop voltage control is utilized [15]
tie mode, the way to control the power sending to the grid is to to enable current sharing capability among paralleled inverters.
control the inverter output current with current-mode control. On In this dual-loop controller, an inner current loop is used to
the other hand, most loads in islanding mode shown in Fig. 2(b) damp the LC resonance pole while an outer voltage loop is used
require the output voltage to be regulated within a desired volt- to regulate the output voltage.
age range. This can be achieved through voltage-mode control. The current open loop gain Gio lo op (s) is the same as that in (1)
since the inverter hardware is the same. By choosing a low-pass
III. PR CONTROLLER FOR GRID-TIE INVERTER OPERATION filter with a 1.5-kHz cutoff frequency and a 0.5 proportional gain
in the current controller Gi s (s), the compensated current loop
The open current loop gain Gi o lo op (s) is defined in (1), and gain in islanding or standalone mode Ti s (s) is shown in (3). The
the complete control system is shown in Fig. 3(a) Bode plots of Ti s (s) and Gio lo op (s) are shown in Fig. 5(a). The
Gi o lo op (S) = Fm Gid (s) Hi Glf (s) (1) current controller is designed to achieve a crossover frequency
where of about 800 Hz with consideration of the 20-kHz sample-and-
4 fSW 1 hold effect on stability. The low-pass filter in Gi s (s) is selected
Fm = = , to damp the resonance effect of the output LCL filter. The outer
fDSP 1250
open voltage loop gain is expressed in (4) as
Vdc 212
Gid (s) = Hi = = 34.133, Ti s (s) = Gi s (s) Gi o lo op (s) (3)
rL i + sLi |I + M ax | + |IM ax | where
2 f
HW F ANF
Glf (s) = Gi s (s) = 0.5 f = 9.4247 1000 rad/s
(s + HW F )2 (s + ANF ) s + f
where Fm , Gid (s), Hi , and Glf (s) are the DSP modulation gain, Gv o lo op (s) = Gi c lo op s (s) Gv i (s) Hv (s) Glf (s)(4)
the control-to-inverter-side-inductor-current transfer function, where
the current feedback gain, and the hardware low-pass filters
Gi s (s) Fm Gid (s)
transfer function, respectively. Fm1 is the number of pulsewidth Gi c lo op s (s) = ,
1 + Ti s (s)
modulation (PWM) counter steps per quarter switching cycle,
which is determined by the 20-kHz switching frequency (fSW ) Lg (s + z 1 )
Gv i (s) = ,
and the 100-MHz DSP clock frequency (fDSP ). By selecting Lg Cf (s + p 1 ) (s + p 2 )
the voltage at the filtering capacitor (vac ) and the current of the Ro
inverter-side inductor (iac ) as the feedback signals with admit- z 1 = , p1 , p 2
Lg
tance compensation, the control plant model Gid (s) is only a  
2
simple first-order system [24]. Hi is the 12-bit analog-to-digital Ro Ro 4
conversion ratio that maps a 60 A maximum analog value to = 0.5 ,
Lg Lg Lg Cf
a digital value between 0 and 4095. Vdc , Li , rL i , HW F , and
ANF are the dc-link voltage, the inverter-side inductance and 212
Hv = = 5.12
its equivalent resistance, and the angular cutoff frequency of |V+ M ax | + |VM ax |

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CHEN et al.: DESIGN OF PARALLEL INVERTERS FOR SMOOTH MODE TRANSFER MICROGRID APPLICATIONS 9

Fig. 3. (a) Control block diagram in grid-tie mode. (b) Bode plots of T i g (s).

Fig. 4. Control block diagram of a voltage dual-loop controlled inverter for islanding operation.

Fig. 5. Bode plots of voltage controller designs in islanding mode. (a) Current loop results. (b) Voltage loop results.

where Gi c lo op s (s), Gv i (s), and Hv are the closed-loop gain

of the inner current loop, the inverter-side-inductor-current-to-
capacitor-voltage transfer function, and the voltage feedback
gain, respectively. As shown in (5), a PR controller is adopted
to eliminate the steady-state error

2c kr s
Gv (s) = kp + . (5)
s2 + 2c s + 12

Using 20% maximum load as the design point, the control

parameters are selected as kp = 0.02, kr = 12, c = 10 rad/s,
and 1 = 377 rad/s. The resulting Bode plots of the compen- Fig. 6. Hardware configuration of parallel-inverter microgrid system.
sated voltage loop gain Tv (s) =Gv (s)Gv o lo op (s) and the un-
compensated gain Gv o lo op (s) are shown in Fig. 5(b). The PR
controller causes a 38.6 dB loop gain at the fundamental fre- V. MICROGRID OPERATIONS WITH PARALLEL INVERTERS
quency, which should reduce the steady-state error of the output In a microgrid system, there are two basic operation modes:
voltage to about 1.5%. grid-tie mode and islanding mode. Fig. 6 shows the hardware

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10 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 1, JANUARY 2010

Fig. 7. Control block diagrams. (a) Parallel-inverter microgrid system in islanding mode. (b) First inverter when the microgrid system is in grid-tie mode.

configuration of the parallel-inverter microgrid system running Fig. 7(a) shows the control block diagram of the parallel-
in the islanding mode. If the grid is not available, the SSR is inverter microgrid system running in islanding mode. Every in-
disconnected and the system supplies its own power to the criti- dividual inverter has its own DSP controller, and there is an upper
cal load. One of the inverters has to operate in dual-loop control level controller that provides the mode attribute and the mode-
and serve as a voltage source, while the rest of the inverters transfer command generation for the inverters in the system.
operate in single current-loop control to share the current as When the microgrid system in Fig. 7(a) switches from islanding
required. When the grid recovers, the SSR is reconnected and mode to grid-tie mode, the control of the first inverter changes
all the inverters in the system run in a single current mode to from voltage-control mode to current-control mode, as shown in
supply energy to the critical load and to exchange energy with Fig. 7(b), while the control of the other inverters stays the same.
the grid. At least one inverter is operating in voltage dual-loop control in

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CHEN et al.: DESIGN OF PARALLEL INVERTERS FOR SMOOTH MODE TRANSFER MICROGRID APPLICATIONS 11

islanding mode. Conversely, all inverters are running in current
single-loop control in grid-tie mode. The selection of the in-
verter running in voltage-mode or current-mode control is also
determined by the upper level controller through the CAN bus.
With the hot-swap CAN bus, the communication channel
will still survive even when one single node is disconnected. In
addition, when the original dual-loop unit fails, the microgrid
system can still function because the upper level controller will
assign another inverter as the dual-loop control and keep the
whole system running. However, the CAN bus or upper level
controller may fail. In this case, it is necessary to adopt other
backup control methods such as droop control [10][12] or
circular-chain control [13], [14] to improve reliability. These
added backup control methods may increase the hardware cost
due to increased communication ports or the software burden
due to additional computation requirement.
In order to minimize the thermal stress of the system, the
microgrid system should perform current sharing among the
paralleled inverters. As shown in Fig. 7, the microgrid can share
the currents among parallel inverters by peak value calcula-
tion (PC), the automatic reference generation (ARG), and PLL
blocks through the CAN bus. Once the PC and the PLL detect the
magnitude and phase information, the ARG adjusts the current
reference iref2 , as shown in (6), so that the current peak dif-
ference and phase difference are minimized, where the ipk band
and i band are the magnitude and phase bands for the inequality
condition. The ipk step and i step are the magnitude and phase
step sizes used to modify the magnitude offset ipk offset and the
phase offset i offset , respectively. In this system, only the digi-
tally formatted ac signal magnitude and phase information need
to be transmitted. The frequency information does not need to
be transmitted because it will be automatically tracked by the
PLL. Without transmitting the actual 50- or 60-Hz ac signal,
the transmitting bandwidth can be lowered and the transmission
distance can be largely extended. The signal transmission can be
very reliable even in a noisy environment with the differential
transmission and the CAN bus error checking protocol
where (iref 2 pk )
page.
VI. MODE TRANSFER CONSIDERATIONS
As shown in Fig. 6, the parallel-inverter microgrid system
should either supply the critical load Rload and exchange the
power with the grid when the grid is available, or keep supply-
ing the Rload when the grid is not available. In order to keep
supplying power to Rload , the microgrid system is required to
switch between grid-tie and islanding modes without drastic
electrical stresses. If the system does not have the proper mode
transfer procedure, severe transient voltages or currents will
occur that may damage the entire system. Since the whole mi-
crogrid is controlled like a current source in the grid-tie mode
and a voltage-controlled output in islanding mode, the key to a
smooth transfer is to comply with the basic circuit laws: 1) do
not interrupt a large magnitude of current on the switch and 2) do
not connect two voltage sources directly without well-matched
and synchronized magnitude, frequency, and phase.
With the control block diagram shown in Fig. 7, the pro-
posed procedure to change from grid-tie to islanding mode is
summarized as follows.
1) The upper level controller detects the fault on the grid
vgrid and extracts the current information igrid .
2) Through the CAN bus, the upper level controller provides
igrid information and commands all the current-controlled
inverters to change their outputs, so that the current on
the SSR igrid can be minimized to avoid mode transfer
transient.
3) The upper level controller provides the turn OFF signal
for the SSR after a certain waiting time, for example, five
cycles.
4) Through the CAN bus, the upper level controller com-
mands a selected inverter (inverter 1) to change from
current-controlled mode to voltage-controlled mode at the
next zero crossing.
5) Inverter 1 regulates the bus voltage to a desired level and
provides the output current information to inverter 2, so
that they can share the total current in the islanding mode.
Since the inverter-based microgrid tends to have small over-
current capability, the five-cycle waiting is chosen to ensure
smooth current transfer while considering the ten-cycle clearing
time under the worse-case abnormal grid voltage and frequency
conditions [20]. However, this waiting time can be set to an-
other value to accommodate equipment electrical ratings and a
desirable clearing time in different fault conditions
On the other hand, the procedure to change from islanding to
grid-tie mode is summarized as follows.
iref 2 = iref 2 pk iref 2 (6) 1) The upper level controller detects if the grid voltage vgrid
recovers, and keeps detecting the grid voltage magnitude
and (iref 2 ), as shown at the bottom of this
vgrid pk and phase vgrid information.
2) Through the CAN bus, the upper level controller provides
the grid voltage information and commands the inverter 1
to adjust vbus to track vgrid in both magnitude and phase.
3) The upper level controller keeps monitoring vbus and vgrid .
It turns on the SSR once the two voltages are synchronized
in phase and magnitude.
4) Through the CAN bus, the upper level controller com-
mands the inverter 1 to change its controller from voltage-
controlled mode to current-controlled mode at the next


ipk offset = ipk offset , if |iac1 pk iac2 pk | < ipk band
iref 2 pk = iac1 pk + ipk offset ,
ipk offset = ipk offset ipk step , if |iac1 pk iac2 pk | > ipk band

i offset = i offset , if |vac2 e iac e| < i band
iref 2 = vac2 e + i offset ,
i offset = i offset i step , if |vac2 e iac e| > i band .

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12 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 1, JANUARY 2010

Fig. 8. Photograph of the proposed microgrid system.

zero crossing. It assigns the current references so that zero

current goes through the SSR during transfer transient.
5) The current controlled inverters change the current refer-
ence to a desired level.

VII. RESULTS OF IMPLEMENTATION

Fig. 8 shows the hardware setup of tested microgrid system,
which consists of two identical power conditioning systems,
an upper level controller, an SSR, and the CAN bus connection.
Each power conditioning system consists of a dcdc converter to
boost the low-voltage input from 48 to 420 V and a dcac inverter
that produces 208 V ac output for the grid connection. The
source of the dcdc converter can be a fuel cell or a photovoltaic,
but for this testing, a 60-V, 20-kW fuel cell simulator was used to
serve as the source. Each power conditioning system is packaged
in a standard 19 rack-mount case with a power connection on Fig. 9. Inverter test results. (a) Grid-tie test at 4.85 kW power output.
the back panel and the DSP controller on the front panel. The (b) Islanding test at 7.6 kW power output with two inverters in parallel.
upper level controller communicates with power conditioning
systems by the CAN bus to provide a stable communication. An
SSR is used to connect the grid at the point of common coupling grid-tie mode so that the bus voltage vbus is the same as the grid
(PCC) to perform the mode transfers. voltage vgrid . Note that the igrid and vgrid are 180 out of phase,
Fig. 9(a) shows the experimental results of one single inverter which means that the grid also supplies power to the critical load
in grid-tie mode under 32 A peak current connecting to the Rload before the mode transfer. Once the grid voltage vgrid is
utility grid. Waveforms indicate that the output current follows higher than a preset limit (135 Vrm s ), the upper level controller
the command well, which indicates successful elimination of the starts to command all the current controllers to change their
steady-state error by the use of a PR controller along with the output currents iout1 and iout2 to minimize the current in igrid .
admittance compensation in the current loop. Fig. 9(b) shows the As can be seen from the waveforms, the igrid starts to decay
experimental results of the parallel-inverter microgrid system to near zero about five cycles ahead of changing the state of
running in islanding mode at 7.6 kW output. The experimental the SSR control signal Vssr ctl . Five cycles later, the upper level
results indicate that output currents are in phase between the two controller changes the level of the SSR control signal Vssr ctl ,
inverters, and both parallel inverters share current evenly. This which turns off the SSR at the next zero crossing. Note that the
suggests that the CAN communication along with the autotuning time when Vssr ctl changes state in the simulation is the real time
reference works well. when the SSR starts to act, which happens at the zero crossing.
Fig. 10 shows the simulation and experimental results of mode The PWM signal switches from current controller to voltage
transfer from grid-tie mode to islanding mode for the parallel- controller at the same zero crossing.
inverter microgrid system. For the mode transfer tests, the grid The voltage controller in inverter 1 regulates the bus voltage
voltage is simulated by an additional voltage-controlled inverter vbus and keeps supplying the load in islanding mode. At the
so that the simulated grid voltage can be regulated to trigger the same time, the current sharing mechanism by the CAN bus and
mode transfer. For the safety considerations, the mode transfers the autotuning reference start to work to minimize the thermal
are conducted with the following resistors to limit the transient stress of the system. Both the simulation and test results show
currents: a 2.5- resistor in series with the simulated grid, a no severe transients in bus voltage vbus and load current iload ,
1.6- resistor in series with the inverter 1 output, and a 1- which suggests that the parallel-inverter microgrid system can
resistor in series with the output of inverter 2. Before the mode smoothly transfer from grid-tie to islanding mode. In order to
transfer, all the inverters in the microgrid system operate in clearly show the voltage level difference before and after the

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CHEN et al.: DESIGN OF PARALLEL INVERTERS FOR SMOOTH MODE TRANSFER MICROGRID APPLICATIONS 13

Fig. 11. Islanding mode to grid-tie mode transfer results for (a) simulation
Fig. 10. Grid-tie mode to islanding mode transfer results for (a) simulation and (b) experiment.
and (b) experiment.

mode transfer during an abnormal voltage condition, the bus actual systems, these abnormal voltage levels can be different
voltage is intentionally set at a higher level before and at a lower levels, as specified in [20].
level after the mode transfer. The test waveform shows that Fig. 11 shows the simulation and experimental results of the
when the bus voltage is 15% higher than the nominal voltage, it paralleled-inverter microgrid system transferring from islanding
is transferred to islanding mode. After the mode transfer, the bus to grid-tie mode. Once the grid voltage recovers to a preset value
voltage is intentionally 10% lower than the nominal voltage. In (90 Vrm s ), commanded by the upper level controller through

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14 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 1, JANUARY 2010

CAN bus, the inverter 1 starts to synchronize the magnitude and [2] L. Yunwei, D. M. Vilathgamuwa, and C. L. Poh, Design, analysis,
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CHEN et al.: DESIGN OF PARALLEL INVERTERS FOR SMOOTH MODE TRANSFER MICROGRID APPLICATIONS 15

Chien-Liang Chen (S06) received B.S. degree from Yuang-Shung Lee (M91) received the M.S. and
the National Taiwan University of Science and Tech- Ph.D. degrees in electrical engineering from the Na-
nology, Taipei, Taiwan, in 2002, and the M.S. degree tional Taiwan Institute of Technology, Taipei, Taiwan,
from the National Tsing-Hua University, Hsinchu, in 1983 and 1993, respectively.
Taiwan, in 2004, both in electrical engineering. He is During 1986, he was a faculty member at Fu-Jen
currently working toward the Ph.D. degree at Virginia Catholic University (FJCU), Taipei, where he was
Polytechnic Institute and State University (Virginia the Chair of the Department of Electronic Engineer-
Tech), Blacksburg. ing from 1997 to 2000 and the Dean of the Office
Since 2006, he has been a Research Assistant at the of Research and Development from February 2007
Future Energy Electronics Center (FEEC), Virginia to January 2009, and is currently a Full Professor in
Tech. His current research interests include grid- the Graduate Institute of Applied Science and Engi-
tie inverters, parallel inverters, mircogrid applications, and soft-switching neering, and the Department of Electronic Engineering. He is also a Visiting
techniques. Research Scholar at the Future Energy Electronic Center, Virginia Polytech-
nic Institute and State University, Blacksburg. His current research interests
include dynamic control of power systems and distributed generation systems,
cell voltage equalization and protection of series connected lithium-ion batter-
ies, intelligent battery management systems, design of soft-switching bidirec-
tional dcdc converters, electromagnetic interference (EMI) measurement and
countermeasures for switching mode power supply, applications of power line
Yubin Wang (M07) was born in Yantai, China, communication, and power IC design.
in 1967. He received the B.S., M.S., and Ph.D. Prof. Lee is a member of the IEEE Industrial Electronics Society, the IEEE
degrees from Shandong University of Technology, Power Electronics Society, and the Institute of Electronics, Information and
Jinan, China, in 1989, 1993, and 2007, respectively, Communication Engineers (IEICE) Communication Society.
all in electrical engineering.
From 2007 to 2008, he was a Postdoctoral Re-
search Scholar with the Future Energy Electronics
Center (FEEC), Virginia Polytechnic Institute and
State University, Blacksburg. He is currently an As-
sociate Professor at Shandong University of Technol-
ogy. His current research interests include modeling
and design of power electronic converters, flexible ac transmission systems Daniel Martin (S09) received the Bachelors degree
(FACTS), and microgrid applications. in electrical engineering from Michigan State Univer-
sity, East Lansing, in 2008. He is currently working
toward the Ph.D. degree at Virginia Polytechnic In-
stitute and State University, Blacksburg.
He is currently with in the Future Energy Elec-
tronics Center. His current research interests include
power systems and parallel inverters for alternative
Jih-Sheng (Jason) Lai (S84M87SM93F07) energy applications.
received the M.S. and Ph.D. degrees in electrical engi-
neering from the University of Tennessee, Knoxville,
in 1985 and 1989, respectively.
From 1980 to 1983, he was the Head of the Elec-
trical Engineering Department, Ming-Chi Institute
of Technology, Taipei, Taiwan, where he initiated a
power electronics program and received a grant from
his college, and a fellowship from the National Sci-
ence Council to study abroad. In 1986, he became a
Staff Member at the University of Tennessee, where
he taught control systems and energy conversion courses. In 1989, he joined
the Electric Power Research Institute (EPRI) Power Electronics Applications
Center (PEAC), where he was engaged in the EPRI-sponsored power electronics
research projects. During 1993, he was a Power Electronics Lead Scientist at
Oak Ridge National Laboratory, where he initiated a high-power electronics pro-
gram and developed several novel high-power converters including multilevel
converters and soft-switching inverters. In 1996, he joined Virginia Polytechnic
Institute and State University, Blacksburg, where he is currently a Professor and
the Director of the Future Energy Electronics Center. His current research in-
cludes high-efficiency power electronics conversions for high-power and energy
applications. He has authored or coauthored more than 200 technical papers and
two books, and holds 18 U.S. patents.
Dr. Lai was the Chair for the 2000 IEEE Workshop on Computers in Power
Electronics (COMPEL 2000), the 2001 IEEE/Department of Energy (DOE)
Future Energy Challenge, and the 2005 IEEE Applied Power Electronics Con-
ference and Exposition (APEC 2005). He received several distinctive awards
including the Technical Achievement Award in Lockheed Martin Award Night,
two IEEE Industry Applications Society (IAS) Conference Paper Awards, the
Best Paper Awards from the IEEE Industrial Electronics Society (IECON 1997),
the International Power Electronics Conference (IPEC 2005), and the Power
Conversion Conference (PCC 2007).

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