12/08/17

Introduc)on
Memory is one of the most important func8onal units of a computer.
Used to store both instruc8ons and data.
Stores as bits (0s and 1s), usually organized in terms of bytes.
How are the data stored in memory accessed?
Lecture 1: EVOLUTION OF COMPUTER SYSTEM
Lecture 23:1:PROCESSOR
Lecture EVOLUTION MEMORY INTERACTION
OF COMPUTER SYSTEM Every memory loca8on has a unique address.
A memory is said to be byte addressable if every byte of data has a unique
address.
DR. KAMALIKA DATTA Some memory systems are word addressable also (every addressed loca8ons
DR. DR. KAMALIKA DATTA
KAMALIKA DATTA
DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING, NIT MEGHALAYA consists of mul8ple bytes, say, 32 bits or 4 bytes).
DEPARTMENT OFOF
DEPARTMENT COMPUTER SCIENCE
COMPUTER AND
SCIENCE ANDENGINEERING,
ENGINEERING,NIT
NITMEGHALAYA
MEGHALAYA

2 2 2

Connec)on between Processor and Memory An Example Memory Module

n address lines :: The maximum
n-bit m-bit
address bus
Address bus provides the number of memory loca8ons MEMORY data bus

address of the memory that can be accessed is 2n. (2n addressable

loca8on to be accessed. M Address m data lines :: The number of memory loca8ons)
A bits stored in every addressable
Data bus transfers the
R loca8on is m.
data read from memory, PRIMARY The RD/WR control line selects
or data to be wriPen into PROCESSOR MEMORY the memory for reading or
M Data
memory. RD/WR CS
D wri8ng (1: read, 0: write).
Bidirec8onal.
R The chip select line (CS) when
Control bus provides ac8ve (=0) will enable the chip; The memory size is specied as
various signals like READ, otherwise, the data bus is in the
WRITE, etc. Control 2n x m
high impedance state.

3 2 4 2

Classica)on of Memory Systems b) Random-access versus Direct/Sequen)al access:

A memory is said to be random-access when the read/write 8me is
a) Vola)le versus Non-vola)le: independent of the memory loca8on being accessed.
A vola.le memory system is one where the stored data is lost when the Examples: CMOS memory (RAM and ROM).
power is switched o. A memory is said to be sequen.al access when the stored data can
Examples: CMOS sta8c memory, CMOS dynamic memory. only be accessed sequen8ally in a par8cular order.
Dynamic memory in addi8on requires periodic refreshing. Examples: Magne8c tape, Punched paper tape.
A non-vola.le memory system is one where the stored data is retained A memory is said to be direct or semi-random access when part of the
even when the power is switched o. access is sequen8al and part is random.
Examples: Read-only memory, Magne8c disk, CDROM/DVD, Flash memory, Example: Magne8c disk.
Resis8ve memory. We can directly go to a track acer which access will be sequen8al.

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c) Read-only versus Random-access: Access Time, Latency and Bandwidth

Read-only Memory (ROM) is one where data once stored in permanent
or semi-permanent. Terminologies used to measure speed of the memory system.
Data wriPen (programmed) during manufacture or in the laboratory.
a) Memory Access Time: Time between ini8a8on of an opera8on (Read or
Examples: ROM, PROM, EPROM, EEPROM. Write) and comple8on of that opera8on.
Random Access Memory (RAM) is one where data access 8me is the b) Latency: Ini8al delay from the ini8a8on of an opera8on to the 8me the
same independent of the loca8on (address). rst data is available.
Used in main / cache memory systems.
c) Bandwidth: Maximum speed of data transfer in bytes per second.
Example: Sta8c RAM (SRAM) data once wriPen are retained as long as
power is on. In modern memory organiza8ons, every read request reads a block of words
Example: Dynamic RAM (DRAM) requires periodic refreshing even when into some high-speed registers (LATENCY), from where data are supplied to
power is on (data stored as charge on 8ny capacitors). the processor one by one (ACCESS TIME).

7 2 8 2

Design Issue of Memory System

The most important issue is to Some important ques8ons?
bridge the processor-memory How to make the memory system work faster?
gap that has been widening
How to increase the data transfer rate between CPU and memory?
with every passing year.
Advancements in memory
How to address the ever increasing storage needs of applica8ons?
technology are unable to cope Some possible solu8ons:
with faster advancements in
Cache Memory: to increase the eec8ve speed of the memory system.
processor technology.
Virtual Memory: to increase the eec8ve size of the memory system.

9 2 10 2

What is Cache Memory? What is Virtual Memory?

A fast memory (possibly organized Technique used by the opera8ng
in several levels) that sits between system to provide an illusion of very
processor and main memory. large memory to the processor.
Faster than main memory and Level-1 Level-2 Main Program and data are actually Main
CPU CPU
Cache Cache stored on secondary memory that is Secondary
rela8vely small. Memory Memory
much larger. Memory
Frequently accessed data and
instruc8ons are stored here. Transfer parts of program and data
from secondary memory to main
Cache memory makes use of the
memory only when needed.
fast SRAM technology.

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How a Memory Chip Looks Like? Organiza)on of Cells in an 8x4 Memory Chip
W0 b3 b3 b2 b2 b1 b1 b0 b0
Memory cells are organized in
W1
the form of an array.
W2
Every memory cell holds one
bit of data. Address
W3
Memory Cells
Present-day VLSI technology A0 Decoder W4
A1 3 X 8
allows one to pack billions of W5
A2
bits per chip. W6
A memory module used in
W7
computers typically contains
R/W
several such chips. Sense/Write
circuit
Sense/Write
circuit
Sense/Write
circuit
Sense/Write
circuit
CS

13 2 14 2

A 32-bit memory chip organized as 8 x 4 is shown. External Connec)on Requirements

Every row of the cell array cons8tutes a memory word.
A 3 x 8 decoder is required to access any one of the 8 rows.
The 8 x 4 memory requires the following external connec8ons:
The rows of the cells are connected to the word lines.
Address decoder of size: 3 x 8
Individual cells are connected to two bit lines.
Bit b and its complement b. 3 external connec8ons for address.
Required for reading and wri8ng. Data output : 4-bit
Cells in each column are connected to a sense/write circuit by the two bit 4 external connec8ons for data.
lines. 2 external connec8ons for R/W and CS.
Other than address and data lines, there are two control lines: R/W and
2 external connec8ons for power supply and ground.
CS (Chip Select).
CS is required to select one single chip in a mul8-chip memory system. Total of 3 + 4 + 2 + 2 = 11.

15 2 16 2

What About a 256 X 16 Memory?

Here the total number of external connec8ons are es8mated
as follows.
Address decoder size: 8 x 256 END OF LECTURE 23
8 external connec8ons for address.
Data output : 16-bit
16 external connec8ons for data.
2 external connec8ons for R/W and CS.
2 external connec8ons for power supply and ground.
Total of 8 + 16 + 2 + 2 = 28.

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Introduc)on
Broadly two types of semiconductor memory systems:
a) Sta8c Random Access Memory (SRAM)
b) Dynamic Random Access Memory (DRAM)
Lecture 1: EVOLUTION OF COMPUTER SYSTEM i. Asynchronous DRAM
Lecture
Lecture 1:24: STATIC AND
EVOLUTION DYNAMICSYSTEM
OF COMPUTER RAM ii. Synchronous DRAM
Vary in terms of speed, density, vola8lity proper8es, and cost.
DR. KAMALIKA DATTA
DR. KAMALIKA DATTA Present-day main memory systems are built using DRAM.
DEPARTMENT OF DR. KAMALIKA DATTA
DEPARTMENT OFCOMPUTER
COMPUTERSCIENCE AND ENGINEERING,
SCIENCE AND ENGINEERING, NIT
NIT MEGHALAYA
MEGHALAYA Cache memory systems are built using SRAM.
DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING, NIT MEGHALAYA

2 20 2

Sta)c Random Access Memory (SRAM)

SRAM technology:
SRAM consists of circuits which can store the data as long as Can be built using 4 or 6 MOS transistors.
power is applied. Modern SRAM chips in the market uses 6-transistor implementa8ons
It is a type of semiconductor memory that uses bistable latching for CMOS compatability.
circuitry (ip-op) to store each bit. Widely used in small-scale systems like microcontrollers and
SRAM memory arrays can be arranged in rows and columns of embedded systems.
memory cells. Also used to implement cache memories in computer systems.
To be discussed later.
Called word line and bit line.

21 2 22 2

A 1-bit SRAM Cell READ Opera)on in SRAM

Two inverters are cross connected to form Bit lines Bit lines
a latch. To read the content of the cell, the word
line is ac8vated (= 1) to make the
The latch is connected to two bit lines with
transistors T1 and T2 on.
transistors T1 and T2.
T1 A B
T2 The value stored in latch is available on T1 A B
T2
Transistors behave like switches that can
bit line b and its complement on b.
be opened (OFF) or closed (ON) under the
control of the word line. Sense/write circuits connected to the bit
lines monitor the states of b and b.
To retain the state of the latch, the word
Word line Word line
line can be grounded which makes the b b b b
transistors o.

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WRITE Opera)on in SRAM 6-Transistor Sta)c Memory cell

Bit lines
To write 1: The bit line b is set with 1 and bit Bit lines 1-bit SRAM cell with 6-transistors
line b is set with 0. Then the word line is are used in modern-day SRAM
ac8vated and the data is wriPen to the latch. implementa8ons. T3 T4
To write 0: The bit line b is set with 0 and bit Transistors (T3 &T5) and (T4 &T6)
line b is set with 1. Then the word line is T1 A B
T2
form the CMOS inverters in the T1 T2
ac8vated and the data is wriPen to the latch. latch. X Y
The required signals (either 1 or 0) are The data can be read or wriPen in T5 T6
generated by the sense/write circuit. the same way as explained.
Word line
b b
b Word line b

25 2 26 2

In State 0 In State 1
Bit lines Bit lines
In state 0 the voltage at X is low and In state 1 the voltage at X is high and
the voltage at Y is high. the voltage at Y is low.
When the voltage at X is low, T3 T4 When the voltage at X is high, T3 T4
transistors (T4 & T5) are on while transistors (T3 & T6) are on while
(T3 & T6) are o. T1 T2 (T4 & T5) are o. T1 T2
X Y X Y
When word line is ac8vated, T1 and When word line is ac8vated, T1 and
T2 are turned on and the bit lines b T5 T6 T2 are turned on and the bit lines b T5 T6
will have 0 and b will have 1. will have 1 and b will have 0.

b Word line b b Word line b

27 2 28 2

Features of SRAM Dynamic Random Access Memory (DRAM)

Moderate / High power consump8on.
Current ows in the cells only when the cell is accessed. Dynamic RAM do not retain its state even Bit line
Because of latch opera8on, power consump8on is higher than DRAM. if power supply is on. Word line
Data stored in the form of charge stored
Simplicity refresh circuitry is not needed. on a capacitor.
Vola8le :: con8nuous power supply is required.
Requires periodic refresh. T
Fast opera8on. The charge stored cannot be retained C
Access 8me is very fast; fast memories (cache) are built using SRAM. over long 8me (due to leakage).
High cost. Sense/Write
Less expensive that SRAM. Circuit
6 transistors per cell. Requires less hardware (one transistor
Limited capacity. and one capacitor per cell).
Not economical to manufacture high-capacity SRAM chips. Address lines are mul8plexed. 1-transistor DRAM Cell

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READ Opera)on in DRAM WRITE Opera)on in DRAM

The transistor of the par8cular cell is Bit line The transistor of the par8cular cell is Bit line
turned on by ac8va8ng the word line. Word line turned on by ac8va8ng the word line. Word line
A sense amplier connected to bit line Depending on the value to be wriPen (0
senses the charge stored in the capacitor. or 1), an appropriate voltage is applied
T T
C to the bit line. C
If the charge is above threshold, the bit
line is maintained at high voltage, which The capacitor gets charged to the
Sense/Write required voltage state. Sense/Write
represents logic 1. Circuit Circuit
Refreshing of the capacitor requires
If the charge is below threshold, the bit periodic READ-WRITE cycles (every few
line is grounded, which represent logic 0. msec).

31 2 32 2

Types of DRAM
a) Asynchronous DRAM (ADRAM) b) Synchronous DRAM (SDRAM)
Timing of the memory device is Memory opera8ons are synchronized by a
handled asynchronously. clock.
A special memory controller
circuit generates the signals
Concept of SDRAM came in the 1970s. END OF LECTURE 24
Commercially made available only in 1993
asynchronously. by Samsung.
DRAM chips produced between By 2000 SDRAM replaced almost all types
the early 1970s to mid-1990s of DRAMs in the market.
used asynchronous DRAM. Performance of SDRAM is much higher
compared to all other exis8ng DRAM.

33 2 34 2

Asynchronous DRAM
The 8ming of the memory device is controlled asynchronously.
The device connected to this memory is responsible for the
delay.
Lecture 1: EVOLUTION OF COMPUTER SYSTEM Address lines are divided into two parts and mul8plexed.
Lecture
Lecture 25: ASYNCHRONOUS
1: EVOLUTION DRAM
OF COMPUTER SYSTEM Upper half of address:
Loaded into Row Address Latch using Row Address Strobe (RAS).
DR. KAMALIKA DATTA Lower half of address:
DR.
DR.KAMALIKA
KAMALIKA DATTA
DATTA
DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING, NIT MEGHALAYA
DEPARTMENT OFOF
DEPARTMENT COMPUTER SCIENCE
COMPUTER AND
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AND ENGINEERING,NIT
NITMEGHALAYA
MEGHALAYA
Loaded into Column Address Latch using Column Address Strobe (CAS).

2 36 2

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Internal Organiza)on of a DRAM Chip

Cells are RAS
organized in the x Row x Memory Suppose that the memory cell array is organized as r x c.
form of an array, Address Row . . Cell r rows and c columns.
in rows and Latch Decoder . Array An x-bit address is required to select a row r, where x = log2r.
columns.
Cells of each row ... An y-bit address is required to select a column c, where y = log2c.
CS
are divided into An-1 A0 Sense/Write Total address bits: n = x (high order) + y (low order)
xed number of
y y
... R / W
Column
columns, m bits Address Column
each. Latch Decoder
m is 8, 16, 32 or
CAS Dm-1 D0
64.

37 38
2 2

READ or WRITE Opera)on For a READ opera8on, the output values Each row of the cell array must be
of the selected circuits are transferred to periodically refreshed to prevent data
For a read opera8on, the x-bit row Acer loading of row address, the column data lines Dm-1 to D0. loss.
address is applied rst. address is selected. For a WRITE opera8on, the data available Cost is low but access 8me is high
It is loaded into Row Address In response to CAS the column address is on the data lines Dm-1 to D0 is compared to SRAM.
Latch in response to the signal loaded into Column Address Latch. transferred to the selected circuits. Very high packing density (few billion
RAS. Then the column decoder selects a This informa8on is stored in the cells per chip).
The read opera8on is performed par8cular column from c columns and an selected cell. Widely used in the main memory of
in which all the cells of the appropriate group of m sense/write Both RAS and CAS are ac8ve low signals. modern computer systems.
selected row are read and circuits are selected.
refreshed. That is they cause latching the addresses
when they move from high to low.

39 40
2 2

An Example: 1 Gbit ADRAM Chip RAS

32768 x (1024 x 32)
15 x 32768
We assume that the 1 Gbit memory cells are organized as 32768 (215) x = 15 Row x Memory
rows and 32768 (215) columns. Address Row . . Cell
A24 A10
Latch Decoder . Array
Let us assume that data bus is 32-bit long.
So, the memory can be organized as (215) x (210 x 25). ...
CS
Total number of address lines is 25 bits. A24 A0 Sense/Write
y = 10 ... R / W
High order 15 bits of the address is used to select a row. Column y
Address Column
Requires a 15 x 32768 row-address decoder. Decoder
A9 A0 Latch
Low order 10 bits of the address is used to select a column. CAS D31 D0
32 data lines
Requires a 10 x 1024 column decoder.

41
2
42
2

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Fast Page Mode c

RAS
r
Opera8on:
Row
15-bit row address is selected (i.e., x = 15). Address Row . . :. ...
With the help of RAS control signal the row address is latched. The 15 x 32768 Latch Decoder .
Row Decoder selects a par8cular row.
...
Then the 10-bit column address is applied and with the help of CAS the CS
address is latched. The 10 x 1024 column decoder selects a par8cular column. An-1 A0 Sense/Write
R/W
A group of 32 bits are selected as the 32-bit word to be accessed.

Column
...
Address
Latch Column Decoder Latch
Dm-1 D0
CAS

43 44
2 2

Opera8on:
When the DRAM cell is accessed only an m-bit word (data bus width) is transferred.
But when we select a row, we can select not only the data of a single column but
mul8ple columns as well.
A latch can be connected at the output of the sense amplier in each column. END OF LECTURE 25
Once we apply a row address, the row get selected.
Dierent column addresses are required to place dierent bytes on the data lines.
Hence consecu8ve bytes can be transferred by applying consecu8ve column
addresses under the control of successive CAS signals.
This also helps in faster transfer of blocks of data.
This block transfer capability is termed as Fast Page Mode access.

45 46
2 2

Synchronous DRAM
SDRAM is the commonly used name for various kinds of
dynamic RAM that are synchronized with clock.
The structure of this memory is same as asynchronous DRAM.
Lecture 1: EVOLUTION OF COMPUTER SYSTEM The concept of SDRAM were known from 70s but it is rst
Lecture
Lecture 26: SYNCHRONOUS
1: EVOLUTION DRAM
OF COMPUTER SYSTEM developed by Samsung in the year 1993 (KM48SL2000).
By 2000 all kinds of DRAM were replaced by SDRAM.
DR.
DR.
KAMALIKA
DR.KAMALIKA
KAMALIKA
DATTA
DATTA
DATTA
DEPARTMENT
DEPARTMENTOF
OFCOMPUTER
DEPARTMENT COMPUTER
OF SCIENCE
SCIENCE
COMPUTER AND
AND
SCIENCE ENGINEERING,
ENGINEERING,
AND NIT
ENGINEERING,NIT
NIT MEGHALAYA
MEGHALAYA
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48
2 2

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Internal Organiza)on of a SDRAM Chip

Refresh
Counter
In SDRAM address and data connec8ons are buered by registers.
Row
address
Row ... Cell array The output of individual sense amplier is connected to a latch.
Row/ latch Decoder
Column Mode register is present which can be set to operate the memory chip in
address
Column
address
Column ... Read/Write
circuits and dierent modes.
counter Decoder latches
To select successive columns it is not required to provide externally
clock generated pulses on CAS line.
RAS Mode register Data input Data output
A column counter is used internally to generate the required signals.
CAS and Timing register register
R / W control
CS

49 50
2 2

READ and WRITE Opera)ons Burst mode transfer

For READ opera8on, the row address is applied rst, and in response to As in fast page mode, acer the column address is applied the
the column address, the data present in the latches for the selected data from successive column addresses are read out or wriPen
columns are transferred to the data output register.
into.
Then the data is available on the data bus.
For WRITE opera8on, the row address is applied rst, and in response to
In same way burst opera8on of dierent lengths can be specied.
the column address, the data present in the data bus is made available to This uses the same block transfer capability of fast page mode.
the latches through data input register.
The data is then wriPen to the par8cular cell.

51 52
2 2

Standardiza)on
Here the control signals required are provided internally by column SDRAM families are standardized by Joint Electron Device
counter and clock signals. Engineering Council (JEDEC).
New set of data are available in the data lines acer every clock cycle. Various DDRx standards have been formulated and published by
All the opera8ons are triggered at the rising edge of the clock. JEDEC.
It has built-in refresh circuitry, and refresh counter is part of it. Board manufacturers comply by the standards.

53 54
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Types of SDRAM DDR2

Single data rate SDRAM (called SDR) can accept one command and transfer The internal bus
one word of data per clock cycle. width also
grows with
Data transferred typically on the rising edge of the clock.
newer
Double data rate SDRAM (called DDR) transfers data on both the rising and genera8ons of
falling edges of the clock. DDR SDRAM.

DDR SDRAM was launched

in 2000. Internal clock: 133 MHz
DDR2 (2003), DDR3 Bus clock: 266 MHz
(2007), DDR4 (2014). Transfer rate: 4.26 GB/s

55 56
2 2

DDR3 DDR4
Internal clock: 133 MHz Internal clock: 133 MHz
Bus clock: 533 MHz Bus clock: 1067 MHz
Transfer rate: 8.53 GB/s Transfer rate: 17.06 GB/s

57 58
2 2

Name Internal Clock Bus Clock Transfer Rate A dual in-line memory module (DIMM)
DDR2-400 100 MHz 200 MHz 3.20 GB/s consists of a number of DRAM ICs.
Genera)ons of
DDR2-400 133 MHz 266 MHz 4.26 GB/s These modules are mounted on a
DDRx SDRAM DDR2-667 166 MHz 333 MHz 5.33 GB/s printed-circuit board and designed for
DDR2-800 200 MHz 400 MHz 6.40 GB/s use in PCs, worksta8ons and servers.
Three SRDAM DIMM slots on a PC motherboard
DDR3-800 100 MHz 400 MHz 6.40 GB/s DIMMs have separate electrical
DDR3-1066 133 MHz 533 MHz 8.53 GB/s contacts on each side of the module,
and has a 64-bit data path.
DDR3-1333 166 MHz 667 MHz 10.67 GB/s
DDR3-1600 200 MHz 800 MHz 12.80 GB/s
DDR4-1600 100 MHz 800 MHz 12.80 GB/s
DDR4-2133 133 MHz 1066 MHz 17.06 GB/s
DDR4-3200 200 MHz 1600 MHz 25.60 GB/s Two 8 GB DDR4-2133 ECC 1.2V modules

59 60
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DDR Genera)ons: To Summarize

The DDR memory SDR SDRAMs can transfer one word of data per clock cycle.
modules across
DDR (or DDR1) SDRAMs can transfer two words per clock cycle.
genera8ons may not be
compa8ble. DDR2 SDRAM doubles the minimum read or write unit again, to 4
They may have notches consecu8ve words per clock cycle.
in dierent posi8ons. DDR3 con8nues the trend, doubling the minimum read or write unit to 8
consecu8ve words per clock cycle.
DDR4 extends the trend again to 16 consecu8ve words per clock cycle.
In March 2017, a DDR5 standard under development has been announced.

61 62
2 2

Speed of DDR Memories Across Genera)ons

Year Chip size Type Slowest Fastest CAS Cycle
DRAM DRAM transfer )me
)me
2000 256 Mb DDR1 65 ns 45 ns 7 ns 90 ns END OF LECTURE 26
2002 512 Mb DDR1 60 ns 40 ns 5 ns 80 ns
2004 1 Gb DDR2 55 ns 35 ns 5 ns 70 ns
2006 2 Gb DDR2 50 ns 30 ns 2.5 ns 60 ns
2010 4 Gb DDR3 36 ns 28 ns 1 ns 37 ns
2012 8 Gb DDR3 30 ns 24 ns 0.5 ns 31 ns

63 64
2 2

Memory Interfacing
Basic problem:
Interfacing one of more memory modules to the processor.
We assume a single level memory at present (i.e. no cache memory).
Ques8ons to be answered:
Lecture 1: EVOLUTION OF COMPUTER SYSTEM
Lecture 27: MEMORY INTERFACING AND ADDRESSING How the processor address and data lines are connected to memory modules?
Lecture 1: EVOLUTION OF COMPUTER SYSTEM
How are the addresses decoded?
How are the memory addresses distributed among the memory modules?
DR. KAMALIKA DATTA
DR. KAMALIKA DATTA
DR. KAMALIKA DATTA How to speed up data transfer rate between processor and memory?
DEPARTMENT
DEPARTMENTOF
OFCOMPUTER SCIENCEAND
COMPUTER SCIENCE ANDENGINEERING,
ENGINEERING,NITNIT MEGHALAYA
MEGHALAYA
DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING, NIT MEGHALAYA

2 66 2

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M Address A Note About the Memory Interface Signals

A
R PRIMARY The processors The data signals of a memory module (RAM) are typically bidirec8onal.
PROCESSOR MEMORY view of memory Some memory chips may have separate data in and data out lines.
M Data
D For memory READ opera8on:
R
Address of memory loca8on is applied to address lines.
Control RD/WR control signal is set to 1, and CS is set to 0.
MEMORY Data is read out through the data lines acer memory access 8me delay.
Typical interface of a (2n x m memory
memory module. n-bit module) m-bit For memory WRITE opera8on:
address bus data bus Address of memory loca8on is applied to address lines, and the data to be
Real chip may contain more
wriPen to data lines.
signal lines (e.g. DRAM).
RD/WR CS RD/WR control signal is set to 0, and CS is set to 0.

67 2 68 2

Why is CS signal required? SELECTED

An Example Memory Interfacing Problem
To handle mul8ple memory
MEMORY
modules interfacing problem.
Address (2n x m) Consider a MIPS32 like processor with a 32-bit address.
We typically select only one out of
several memory modules at a 8me. Maximum memory that can be connected is 232 = 4 Gbytes.
What happens when CS = 1? RD/WR CS = 0
Assume that the processor data lines are 8 bits.
When a memory module is not Assume that memory chips (RAM) are available with size 1 Gbyte.
selected, the data lines are set to the
MEMORY 30 address lines and 8 data lines.
high impedance state (i.e. (2n x m)
electrically disconnected). Address m-bit Low-order 30 address lines (A29-A0) are connected to the memory modules.
data bus
An example scenario is shown. We want to interface 4 such chips to the processor.
RD/WR CS = 1 Total memory of 4 Gbytes.

69 2 70 2

High order address lines (A31 and A30) select one of the memory modules.
MEMORY M0 CS0 When is M0 selected?
A31 CS0 (1G x 8) RD/WR Address is: 0 0 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
2 x 4 CS1 Range of addresses is: 0x00000000 to 0x3FFFFFFF
A30 Decoder CS2
MEMORY M1 CS1 When is M1 selected?
CS3
(1G x 8) RD/WR Address is: 0 1 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
PROCESSOR A29 A0 Range of addresses is: 0x40000000 to 0x7FFFFFFF
MEMORY M2 CS2 When is M2 selected?
(1G x 8) RD/WR Address is: 1 0 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
D7 D0
Range of addresses is: 0x80000000 to 0xBFFFFFFF
MEMORY M3 CS2 When is M3 selected?
(1G x 8) RD/WR Address is: 1 1 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
Range of addresses is: 0xC0000000 to 0xFFFFFFFF

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Improved Memory Interface for MIPS32

An observa8on:
Consecu8ve block of bytes are mapped to the same memory module. We make small changes in the organiza8on so that 32-bits of
For MIPS32, we have to access 32 bits (4 bytes) of data in parallel, data can be fetched in a single memory access cycle.
which requires four sequen8al memory accesses here.
Exploit the concept of memory interleaving.
We shall look at an alternate memory organiza8on later that would
make this possible. The main changes:
Called memory interleaving. High order 30 address lines (A31-A2) are connected to memory modules.
Low order two address lines (A1 and A0) are used to select one of the
modules.

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How are the addresses mapped to memory modules?

Module M0: 0, 4, 8, 12, 16, 20, 24,
Mo8va8on for word alignment in MIPS32 data words.
32-bit words start from a memory address that is divisible by 4.
Module M1: 1, 5, 9, 13, 17, 21, 25,
Corresponding byte addresses are (0, 1, 2, 3), (4, 5, 6, 7), (8, 9, 10, 11),
Module M2: 2, 6, 10, 14, 18, 22, 26, (12, 13, 14, 15), etc.
Module M3: 3, 7, 11, 15, 19, 23, 27, Possible to transfer all the four bytes in a single memory cycle.
Memory addresses are interleaved across memory modules. What happens if a word is not aligned?
What we can gain from this mapping? Say: (1, 2, 3, 4) or (2, 3, 4, 5) or (3, 4, 5, 6).
Two of the bytes will be mapped to the same memory module.
Consecu8ve addresses are mapped to consecu8ve modules.
Hence the word cannot be transferred in a single memory cycle.
Possible to access four consecu8ve words in the same cycle, if all four
modules are enabled simultaneously. 2 memory cycles required

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MEMORY M0 CS0 MEMORY M0 0

(1G x 8) RD/WR (1G x 8) RD/WR
A31 A2 A31 A2
MEMORY M1 CS1 MEMORY M1 0
A1 CS0 (1G x 8) RD/WR A1 CS0 (1G x 8) RD/WR
MIPS32 MIPS32
PROCESSOR 2 x 4 CS1 PROCESSOR 2 x 4 CS1
Decoder CS2 Decoder CS2
A0 MEMORY M2 CS2 A0 MEMORY M2 0
CS3 CS3
(1G x 8) RD/WR (1G x 8) RD/WR
D7 D0 D31 D0
MEMORY M3 CS2 MEMORY M3 0
(1G x 8) RD/WR (1G x 8) RD/WR
S)ll one module is selected at a Enable all the four modules together.
)me :: 8 bits data transfer per cycle. 32-bit parallel data transfer.

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Memory Latency and Bandwidth Example 1:

Consider a memory system that takes 20 ns to service the access of a
Memory Latency: single 32-bit word.
The delay from the issue of a memory read request to the rst byte of data Latency L = 20 ns per 32-bit word.
becoming available. Bandwidth BW = 32 / (20 x 10-9) = 200 Mbits per second.
Memory Bandwidth:
The maximum number of bytes that can be transferred between the Example 2:
processor and the memory system per unit 8me. The memory system is modied to accept a new (s8ll 20ns) request for
a 32-bit word every 5 ns by overlapping requests.
Latency L = 20 ns per 32-bit word (no change).
Bandwidth BW = 32 / (5 x 10-9) = 800 Mbits per second.

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END OF LECTURE 27

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