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2012 International Conference on Computing, Electronics and Electrical Technologies [ICCEET]



G.Preethi, J. Gayathri Monika, v.Jamuna,

PG Scholar, Research scholar, Professor,
Department of Electrical and Department of Electrical and Department of Electrical and
Electronics Engineering Electronics Engineering Electronics Engineering
Jerusalem College of Jerusalem College of Jerusalem College of
Engineering, Engineering, Engineering,
Chennai, India Chennai, India Chennai, India

Abstract - This paper presents a design of a Multi inverter, and the cascaded H-bridge inverter. All the
Carrier Pulse Width Modulation (MCPWM) Strategy for an topologies have the same property of reducing the
eleven level inverter. The emergence of multilevel inverters harmonics [5].The flying capacitor inverter topology is
(MLI) has increased since the last decade. They are suitable tedious to realize, because every capacitor voltage is
for high voltage and high power applications, due to their
different from the other ,therefore charging becomes
ability to synthesize waveforms with a better harmonic
difficult [3 ]. The clamped inverter which is
spectrum. Numerous topologies have been introduced and
widely studied, for utility and drive applications. Multilevel
commonly known as a neutral clamped converter is not
inverters are commonly modulated, by using multicarrier preferred because it has the problem of DC link voltage
pulse width modulation techniques, such as phase-shifted unbalancing [3 ].
multicarrier modulation, and level-shifted multicarrier
modulation. Amongst these, the level-shifted multicarrier The cascaded inverter has the disadvantage of
modulation technique produces the best harmonic separate DC source but circuit layout is compact and the
performance. This work studies a multilevel inverter with voltage sharing problem is absent .Hence it is easy to
equal DC sources, using the level shifting MCPWM
expand. It is applicable in high power motor drive and
technique. By applying this concept, harmonics can be
HVDC [1][5].
eliminated, and in the output voltage, the Total Harmonic
Distortion (THD) can be improved. A procedure to achieve
the appropriate level shifting is presented in this paper. This paper presents a control technique to the multi
level cascaded inverter so that its harmonic content is
Keywords- Multi-Carrier Pulse Width Modulation reduced and hence voltage is effectively used. Level
(MCPWM), Total Harmonic Distortion (THD), Multi-Level shifting is a well-established emerging modulation and
Inverters (MLI). control technique that has been designed and discussed.


The multilevel voltage source inverter mainly
finds its application in industries such as AC power The cascaded inverter with individual single DC
supplies. The most important advantages of a multilevel sources (SDCS) is preferred. The cascaded topology is
inverter is the harmonic reduction in the output waveform, similar to other two topologies. Every SDCS consist of
by keeping the switching frequency stable or decreasing single-phase full-bridge inverter. Each inverter can give
the inverter power output [2]. The output voltage three different voltage outputs, + Vdc. - Vdc and zero.
waveform of a multilevel inverter is composed of a
number of levels of voltages, Thus the multilevel starts The AC output of each of the different levels of full
from three level. As the number of levels reaches bridge inverters is connected in a series, such that the
increases, the output THD reduces to zero [10]. synthesized voltage waveform is the sum of the inverter
outputs. The number of output phase voltage levels is
The multi-level inverters are basically classified defined by
in to three topologies, which is already studied, they are as
follows, the flying capacitor inverter, the diode clamped M = 2S+ l (1)

978-1-4 673-0210-4112/$31.00 20l2 IEEE 509

2012 International Conference on Computing, Electronics and Electrical Technologies [ICCEET]

based modulation schemes are mainly divided into two

Where S is the number of DC sources categories: level-shifted (LSPWM) and phase-shifted
M is the number of levels. The eleven level (PSPWM) methods. Both of these have several variations,
MLI output will be obtained as given in Figure 2. which differ by the allocation of module carriers with
respect to each other [4].



S., In all level-shifted PWM methods, the carriers of

V, the modules have a frequency of f car =lITsw where the
, frequency of the carrier signal is inversely proportional to
the switching period of the device (The range of the fear
is selected between 10K to lOOK Hz ). The reference
Vdc(S -I ) voltage, on the other hand, can have values between
-MVde and MVde. To cover the whole voltage range, the
carriers are shifted vertically, so that the carrier of the first
module covers the range from zero to Vdc, while the
second covers the range from Vde to 2Vde. The last module
covers the voltage from (M-l)Vde to MVde.
Figure 1: Single-phase structure of a multilevel cascaded inverter.

There are three alternative level shifted

modulation techniques, namely;
Phase Opposition Disposition
Alternative Phase Opposition Disposition
Phase Disposition

In the phase opposition disposition (POD) the
--= :S:::='-
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 carriers above the reference point, are out of phase with
Figure 2: An eleven level multilevel inverter output.
those below zero, by 180.


Pulse Width Modulation refers to a method of

carrying information on a train of pulses, the information
is encoded in the width of the each pulse. This technique
helps in maintaining a constant voltage. The working
principle is comparatively difficult but due to its efficiency
it is preferred [9,6]
Figure 4: Carrier arrangements for POD

A modulation strategy for multilevel inverters is given in

In the alternative phase opposition disposition
Figure 3 .
(APOD), the carriers of adjacent bands are phase shifted
by 180.

Figure 3 : Modulation strategies for multilevel inverters. Figure 5: Carrier arrangements for APOD.

In the carrier-based multilevel modulation, each In the phase disposition (PD), all the carriers are
level in a phase requires a carrier of its own. For the in phase across all the bands. This gives rise to the lowest
SCRBI, this means that every module has its own carrier, harmonic in the higher modulation indices, when
which is compared with the reference voltage. Carrier- compared to the other disposition method.

2012 International Conference on Computing, Electronics and Electrical Technologies [ICCEET]

The switching strategy for the eleven level

inverter is given in Table 1.The above system is connected
for an R load. The switching patterns for the switches in
the upper leg are mentioned, and that for the lower
switches would be the complement of the upper ones. The
waveform obtained for the MLI is given in Figure 8.The
Fast Fourier Transforms analysis is done for the eleven
level inverter for the R load and is given in Figure 9.For
the load of 500hms the THD obtained was 18.87%.
Figure 6: Carrier arrangements for PD.

The level shifted multicarrier modulation offers Table 1 Switching strategy for eleven level
better harmonic attenuation, but also offers an unequal
device condition.
IV SIMULATION RESULTS 1 2 3 4 5 6 7 8 9 10

5 Vdc 1 0 1 0 1 0 1 0 1 0
The feasibility of the proposed PWM strategy has
been investigated and verified through computer 1 0 1 0 I 0 1 0 0 0
simulation results, for both multilevel inverter and multi 1 0 0 0 1 0 1 0 I 0
carrier PWM inverter, for an eleven level cascaded H 1 0 1 0 1 0 0 0 0 0
Bridge inverter. 3Vdc
1 0 0 0 I 0 1 0 0 0
1 0 1 0 0 0 0 0 0 0
2Vdc 1 0 0 0 1 0 0 0 0 0

The cascaded H-bridge inverter is one of the Vdc 1 0 0 0 0 0 0 0 0 0

popular converter topologies for an eleven level inverter; 1 0 1 0 0 1 0 1 1 0
the number of DC sources used is five cells, i.e. , referred 0 0 0 0 0 0 0 0 0 0 0
from equation 1. We use five cells, each cell consisting of
-Vdc 0 I 0 0 0 0 0 0 0 0
a half bridge or full bridge combination of switches with
1 0 0 1 I 0 0 1 0 I
IGBT as switches. The simulink model of the eleven level
-2Vdc 0 1 0 0 I 0 0 I 0 0
MLI is given in Figure 7.
0 I 0 1 0 1 1 0 0 I
-3Vdc 0 I 0 1 0 1 0 0 0 0
0 1 0 1 0 1 0 1 0 0
-4Vdc 0 I 0 1 0 0 0 I 0 I
-5 Vdc 0 1 0 1 0 1 0 I 0 I


0 ,,;-
, --co

;- o.;;-"
8: Eleven level output for R load.

FFT analysis

Fundamental (50Hz) = 275.4 THD= 18.87%

_.1 400



Frequency (Hz)

Figure 7: Simulink model representation for eleven level

Figure 9: FFT analysis of eleven level multi-level inverter .

2012 International Conference on Computing, Electronics and Electrical Technologies [ICCEET]



This is the logical extension of the sine triangle PWM

multilevel inverter, in which n-l carriers are needed for an
n-Ievel inverter. The preferred type is Phase disposition.
The carriers are arranged in vertical shifts in continuous
bands defined by the levels of the inverter. Each carrier
has the same frequency and amplitude. The simulink
model of eleven level MCPWM is given in Figure 10.

A single voltage reference is compared to the

carrier arrangement, and the level associated with the
carrier immediately below the reference, will be generated
by the converter. The subsystem which includes a
sinusoidal and triangular subsystem, briefs the comparison
of the sine wave which is the modulated signal, and is
compared with the carrier signal. When the reference
signal is greater than or equal to the carrier signal, then the
output waveform is above the reference; and otherwise, it
will be below the reference. The subsystem is displayed in , ..
Figures 11 and I2.The output for the II-Level Inverter is
given in Figure 13 and its FFT analysis is shown in Figure
I4.For a load of 50 ohms ,the THD obtained was 4.2%..
The main subsystem model and sinusoidal subsystem for
the eleven level is shown in Figures 11 and 12.



--- ..


:"" -t


-- -

- , -
Figure 11: Subsystem representation of MCPWM

-B i!1 80f-----+i Trigonom Etric
- Constant
. ___ t "-I--

L Figure 12: Sinusoidal subsystem representation of MCPWM

-[ -

Figure 10: Simulink model of eleven level MCPWM

2012 International Conference on Computing, Electronics and Electrical Technologies [ICCEET]

implementing the multicarrier strategy is studied. The

results of both the techniques are then compared against
the values of the THD. It is proved from the comparison
that the THD obtained from the MCPWM inverter is
comparatively lesser than that from the MLI.


I. Czarkowski, Liu, and Pillay, "Multilevel

selectiveharmonic elimination PWM technique in
Figure 13: Output waveform for ll-Level MCPWM series-connected voltageinverters," in Proc. Industry
Applications Annu. Meeting, Oct. 1998,PP. 1454-


2. Carrara, Gardella, Marchesoni" and G. Sciutto,"A

new multilevel PWMmethod: A theoretical analysis,"
IEEE Trans.Power Electron., vol. 7, no. 3, pp. 497-
505, Jul. 1992.

3. Du, L. Tolbert, and 1. Chiasson, "Active harmonic

elimination for multilevel converters," IEEE Trans.
Power Electron., vol. 21, no. 2, pp.459--469, Mar.
Harmo nic order 2006

Figure 14: FFT analysis for MCPWM for R load. 4. Grath and Holmes, "Multicarrier PWM strategies for
multilevel inverters," IEEE Trans. Ind. Electron., vol.
49, no. 4, pp. 858-867, Aug. 2002

20.00% 5. Loh, Holmes, and Lipo, "Implementation and control

of distributed PWM cascaded multilevel inverters with
10.00% minimal harmonic distortion and common-mode
voltage," IEEE Trans. Power Electron., vol. 20, no. I,
0.00% pp. 90-99, Jan. 2005.
MLI for R-LoadMCPWM for R
6. Marchesoni, Mazzucchelli, and S. Tenconi, "A non
conventional power converter for plasma
stabilization," in Proc. Power Electronics Specialist
Conf., 1988, pp. 122-129.
FigurelS: Comparison between MLI and MCPWM.

7. Meynard and H. Foch, "Multi-level choppers for high

The values inferred during simulation for both voltage applications
MLI and MCPWM for an R load, is compared and given Eur. Power Electron. J., vol. 2, no. 1, pp. 45-50, March
in Figure 15 .Based on the values obtained, the graphs are 1992.

represented in Figure 15.From the comparison, the main

8. Rodriguez, B. Wu, S. Bernet, J. Pontt, and S. Kouro,
achievement is harmonic reduction. By increasing the
"Multilevel voltage-source-converter topologies for
number of steps, the waveform reaches the desired
industrial medium-voltage drives," IEEE Trans. Ind.
sinusoidal shape. Electron., vol. 54, no. 6, pp. 2930-2945, Dec. 2007.

9. Sakly, Delarue, and Bausiere, "Rejection of
undesirable effectsof input
DC-voltage ripple in
It is easy to conclude that the multi-level inverter h
single-phasePWM inverters," in Proc. 5t Eur. Conf.
research and development activities are experiencing an on Power Electronics and Applications, Sep. 13-16,
explosive rate of growth. A trend of having more and more 1993,vol. 4, pp. 65-70.
multi-level inverters is obvious. Detailed circuit simulation
was conducted to verify the inverter operation. The 10. Thoegersen .Blaabjerg, and Pedersen, "Improved
research and development is extended to areas such as modulation techniques for PWM- drives," IEEE
high voltage high power semiconductor devices, sensors, Trans. Ind. Electron., vol. 44,no. 1, pp. 87-95,

and high speed DSPs. Also, the behavior of the eleven Feb. 1997.

level cascaded H-bridge inverter, with and without

2012 International Conference on Computing, Electronics and Electrical Technologies [ICCEET]

G.Preethi is currently pursuing

her M.E (Power Electronics And
Drives) in Jerusalem college of
Engineering, Anna university,
Chennai. She received her B.E
degree in Electrical and
Electronics Engineering in the
year 2008 from Golden Valley
Institute of Technology, K.G.F, Karnataka. She is a
student member of IEEE.. Her research interest area
includes multi-level inverters and motor drives.

J.Gayathri Monicka is currently

pursuing her Ph.D Electrical
&Electronics Engineering. in
Jerusalem college of engineering,
Anna university of Technology,
Chennai. She received her B.E.
degree in Electrical & Electronics
Engineering from Annai Teresa Engineering College,
Madras University, India in 2002, M.E. degree in
Power Electronics and Drives from Bharath
University, Chennai, India in 2007. She has 8 years
of teaching experience. Her research interests include
motor drives.
.V.Jamuna is Professor in
Electrical and Electronics
Engineering Department,
Jerusalem College of Engineering,
Chennai, India. She received her
B.E. degree in Electrical &
Electronics Engineering from
St.Peter's Engineering College, Madras University,
Chennai, India in 1999, M.E. degree in Power Electronics
and Drives from Anna University, Chennai, India in 2005,
Ph.D from Anna university in 2010. She has secured fifth
university rank in her P.G degree. She has 12 years of
teaching experience. She has published over 20 technical
papers in national and international conferences
proceedings / journals. She is life member of Indian
Society for Technical Education, Ilnstitution of Electrical
and Electronics Engineers. Her research interests include
Induction Motor Drives and Neural Network.