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In the above gure, A, B 4-bit input, C0 is Carry in and S 4-bit output , C4 is Carry out. The
remaining C1, C2, C3 are intermediate Carry. They are called signals in VHDL Code.
To implement 4 bit Ripple Carry Adder VHDL Code, First implement VHDL Code for full adder
.We Already implemented VHDL Code for Full Adder . Now declare full adder entity as
component in 4-bit Ripple Carry Adder VHDL Code and do Port Map operation.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Ripple_Adder is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
Cin : in STD_LOGIC;
S : out STD_LOGIC_VECTOR (3 downto 0);
Cout : out STD_LOGIC);
end Ripple_Adder;
begin
end Behavioral;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY Tb_Ripple_Adder IS
END Tb_Ripple_Adder;
COMPONENT Ripple_Adder
PORT(
A : IN std_logic_vector(3 downto 0);
B : IN std_logic_vector(3 downto 0);
Cin : IN std_logic;
S : OUT std_logic_vector(3 downto 0);
Cout : OUT std_logic
);
END COMPONENT;
--Inputs
--Outputs
signal S : std_logic_vector(3 downto 0);
signal Cout : std_logic;
BEGIN
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
A <= "0110";
B <= "1100";
wait;
end process;
END;