M ISMATCH IS THE process that causes timeinde matical treatmerit of classes of mismatch behavior which
pendent random variations in physical quantities of covers all known arearelated physical causes. Then the
identically designed devices. Mismatching is a limiting measurements are used to verify the theory and to derive
factor in generalpurpose analog signal processing, but the unknown constants in the theory. The origins of mis
especially in multiplexed analog systems [l], digitaltoana match in several MOS parameters have been studied by
log converters [2], reference sources, etc. In digital circuits means of additional experiments. The applicability of the
matching can also be important, e.g., in the read and write results is demonstrated on several basic circuits.
circuits of digital memories and even in the voltage mar
gins of static RAM cells. The impact of (mis)matching
MOS transistors becomes more important because the /
11. ANALYSIS
dimensions of the devices are reduced and the available
Mismatch that can be observed between the parameters
signal swing decreases.
of a group of equally designed devices (MOS transistors in
Despite the widely recognized importance of matching,
this paper) is the result of several random processes which
there are only a limited number of specialized open litera
occur during every fabrication phase of the devices. This
ture contributions in this field. Shyu et al. [3], [4] has
definition excludes batchtobatch or wafertowafer varia
analyzed the variation in capacitors and current sources in
tions of the absolute value of parameters and unwanted
terms of local and global variations. Local variations are
offsets caused by electrical, lithographic, or timing differ
characterized by a short correlation distance: the concept
ences.
of local variations is also part of the analysis of this paper.
In general the value of a parameter P is composed of a
The effect of the global variations is a constant term in
fixed part and a randomly varying part, resulting in differ
Shyus mismatch description. In the following sections a
ing values of P at different coordinate pairs ( x , y ) on the
more detailed description will be used, thereby introducing
wafer. If the variations are small, the average value of the
spacing dependence. The analysis of current mismatch in
parameter over any area is given by the integral of P ( x , y )
[4] is based on four physical causes: edge effects, implanta
over this area. The actual mismatch in parameter P be
tion and surfacestate charges, oxide effects, and mobility
tween two identical areas at coordinates ( x ~yl) , and
effects. The resulting measurements confirm the global
( X Z , Y d is
trend in current matching, but matching is not further
specified in parameter terms.
Lakshmikumar et al. [ 5 ] described MOStransistor
matching by means of thresholdvoltage and currentfactor
standard deviations. The starting points were again the
possible physical causes. Their analysis of the contribu
tions to the current factor mismatch is not supported by
This integral can be interpreted as the convolution of
Manuscript received December 5 , 1988; revised May 5, 1989. double box functions formed by the integral boundaries
The authors are with the Philips Research Laboratories, 5600 .TA, with the mismatch source function P ( x , U). By means
Eindhoven, The Netherlands.
IEEE Log Number 8930108. of a twodimensional Fourier transformation the geome
(3)
For convenience it has been assumed that both areas are at
a spacing 0, along the x axis. Fig. 1 shows the absolute
value of the geometry functions for three types of transis
tor pairs. The geometry functions have a zero value for The variance of parameter A P between two rectangular
ax,Y = 0, thereby eliminating the absolute value of the
devices is then found by substitution of (3) and the above
parameter from the calculations. The geometry functions described models for the long and short correlation dis
for other geometries are found in the same way, e.g., a tance variations in (4):
crosscoupled group of four transistors has a geometry
function where the last term in brackets in (3) is replaced
by (~0~(c~~D,/2)~0~(~,0,)/2}.
After t h s analysis of the geometry dependence, the
Here A , is the area proportionality constant for parameter
specification of the random contribution to P ( x , y ) or
P, while S, describes the variation of parameter P with the
P ( u x ,a,) has to be formulated. Two classes of distinct
spacing. The proportionality constants can be measured
physical mismatch causes are specified in this paper. Every
and used to predict the mismatch variance of a circuit. For
mismatchgenerating physical process which fulfils the
a group of four crosscoupled transistors is found in a
mathematical properties of these classes results in a similar
similar way:
behavior at the level of mismatchng transistor parameters.
The first class of the mismatchgenerating process on a
parameter P is spatial white noise or shortdistance
variations, with the following features:
the total mismatch of parameter P is composed of The effect of the doubled gate area and of the cancellation
many single events of the mismatchgenerating pro of the linear components in the gradient is obvious.
cess; In the experiments reported in the following sections
the effects on the parameter are so small that the mostly rectangular devices have been used, so ( 5 ) describes
contributions to the parameter can be summed; the variance of the parameters. Secondly the constants in
the events have a correlation distance much smaller (5) are used in t h s paper for tracing the causes of parame
than the transistor dimensions. ter mismatch.
PELGROM et d.: MATCHING PROPERTIES OF MOS TRANSISTORS 1435
begin
111. MATCHING
OF MOS TRANSISTORS I

calculated by applying this theory to the parameters of the for 6 trans for 130 dies
per die per wafer
longchannel MOS model in the linear region: calculate
V, 0, K E
I
differences
AVrAAAKAE
calculate
leads to u2(L ) 0:1/W and a2(W )CC 1/L: position and a complete wafer test cycle is performed: so
the same die is measured about 100 times. The resulting
parameter standard deviations indicate the obtainable ac
curacy of the measurement setup: a(V,) = 0.15 mV and
a( p)/p = 1.5 X lo?
A major problem in wafer measurements is the varying
resistance in the measurement chain, e.g. prober contact to
the bond pad, the aluminum wiring, and relay resistances.
. where A , , A,, A,, Acox, and Sp are processrelated Especially at large W / L ratios and gate drive voltages of
constants. The relative mismatch in the current factor can around 1 V, the equivalent resistance of the MOS transis
. be approximated by the inversearea description as seen in tor in the linear region can be less than 1 k 0 , requiring
the last part of (10) if W and L are large enough. The standard deviations of the series resistances of less than
.
values of W and L for which the inversearea proportion 0.1 !J. This problem was circumvented by including the
ality still holds must be determined from the measure series resistance in the parameter extraction. The major
ments. effect of series resistance is observed in the mobility degra
1436 IEEE JOURNAL OF SOLIDSTATE CIRCUITS, VOL 24, NO 5 , OCTOBER 1989
IO 10. ~7 8%
U (0)

P
6% 3% 1 /
.L %
2%
Fig 4. Standard deviation of (a) the current factor 8 , versus the inverse
tranhtor area for an NMOS transistor p a r and (b) a companson of
the standard deviation of ,8 for parallel and rotated placement.
Fig 3 Standard deviation of (a) the threshold V, and (b) the substrate
factor K versus the inverse transistor area for an NMOS transistor pair
10
t.6% 4 mV .4 %
2
2mV .2%
'30 250
(a)
500
D
750pm 30
(b)
250 500
+D
750pm
mls2Llm
(a)
 ilm 20k2+0
(b)
 I/H
AVTO I .
50mVpm
,theoretical
40mVpm V = 5v

1 
1 2 3 CV
vGS
3%pm
Fig 8 Standard deviahon of the current in an NMOS transistor p a r
connected to 5V drain potential Dots are measurement points, the
2 % pm
. . : n solid curve has been calculated from extracted mismatch data

25nm 35nm50nm65nm
nominal gafe oxide
deviation can be calculated using the mismatch data and
1.300, I
VIII. CONCLUSIONS
I
The variance of the threshold voltage, the current factor,
1.285 and the substrate factor are inversely proportional to the
1.2807 I transistor area. The mismatch in threshold voltage domi
1.275
 nates the transistor performance for normal gatesource
1.210b
potentials. Charge components are believed to contribute
to the mismatch in threshold voltage and mobility varia
1.260
tions influence the currentfactor variance. The spacing
1.255
between transistors can be ignored for transistor areas less
1.250
than 100 pm2. It is shown that thinner gate oxides decrease
t
1.245
1.240
1.235
 I
the threshold and substratefactor mismatch while the rela
tive currentfactor mismatch remains almost constant.
Comparing data of several production facilities indicates
1.230
that matching is not strongly varying for these facilities.
1.225
Several examples show that mismatch data can predict
1.220
the performance of circuits.
1.215
1.210
1.205
ACKNOWLEDGMENT
1.195
1 190
20 30 40 50 60 7b 80 90 ld0 The authors would like to thank the IC processing staff
temp of the Philips Research Laboratory as well as the factories,
Fig. 9. Typical output curves of 70 bandgap circuits measured on one the test and statistics group, and many colleagues for their
wafer for a temperature range of 2O10O0C. assistance and helpful discussions.
Aad C. J. Duinmaijer was born in Uitgeest, The Anton P. G. Welbers was born in Eindhoven,
Netherlands, on March 2, 1959. In 1982 he re The Netherlands, on December 10, 1960 He
ceived the Ing. degree in electrical engineering received the Ing degree from H T S , Eind
from the Polytechmcal School, Haarlem, The hoven, The Netherlands, in 1984
Netherlands In 1986 he joined Phlips Research Laborato
In the same year he joined Phdips Research ries, Eindhoven, The Netherlands, where he 1s
Laboratories, Eindhoven, The Netherlands, involved in the development ol analog tesl and
where he has been workmg in the field of analog measurement procedures E s current interest is
IC design, in both bipolar and CMOS processes in hghfrequency testing methods
In 1988 he transferred to the Consumer Electron
ics Department of Phihps in Eindhoven, where
he is working on analog CMOS dcsign
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