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3, MARCH 2013
(1a) cillator has a single differential tank while the resonator of the single-differential
pair Class-C oscillator in [14] is made of two single-ended tanks. The amplitude
(1b) calculated in [14] is for one of the two tanks.
726 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 48, NO. 3, MARCH 2013
(6a)
(8)
(6b)
(9)
Interestingly, if nMOS and pMOS transistors have different An analysis of the circuit if the pMOS transistors enter the triode
gains (i.e., ), the peak values of the tank voltages region is much more involved, and does not lead to simple
expressed by (6) are different. For symmetry, the analysis of closed-form equations. The intuitive view discussed above is
the circuit in the second half of the oscillation period, i.e., for nevertheless still useful to explain the behavior in this case. The
, when and are active, as depicted in results of a simulation with 0.25 V are shown with
Fig. 2(b), leads to tank voltages with opposite magnitude as the dotted lines in Fig. 3. The gain of the pMOS transistors is
now much lower, since they operate in triode for most of the
time, but the drain current shape must still match the drain cur-
rent of the opposite nMOS transistors. As a result, the ampli-
tude of the tank voltage driving the nMOS transistors (i.e.,
and in the first and second half of the period respectively)
(7)
drops significantly. As shown by the bottom plots in Fig. 3,
the conduction angle of the devices increases and the drain cur-
rent pulses are widened, losing the high dc-to-RF conversion
The above analysis has been checked by means of circuit sim-
efficiency of the narrow pulses. To gain further insight, Fig. 4
ulations reported in Fig. 3. The continuous lines represent the
plots the simulated magnitude of the fundamental component of
tank voltages (top plot) and the MOS currents (bottom plot) for a
the drain current normalized to the bias current (i.e., )
design where 0.9 V, 1.2 mA, and .
versus for different gain factors of the transistors. For
The supply voltage is adjusted for a steady-state common-mode
, the pMOS transistors do not leave the saturation
tank voltage 1 V, and the threshold of the pMOS tran-
region, while for they enter gradually into the
sistors has been artificially increased to 1 V by means of a dc
triode region; the lower , the larger the fraction of the
voltage source in series with the pMOS gates to avoid triode
oscillation period with pMOS transistors in triode. The current
operation. The simulated tank voltages are in very good agree-
conduction angle increases with decreasing , gradu-
ment with (6) and (7) and the difference between positive and
ally losing the high dc-to-RF conversion efficiency. In the limit
negative peaks, due to the different gains of pMOS and nMOS
case of , the conduction angle is approximately
transistors, is clearly evident. The origin of this asymmetry finds
and , which is the same as in the standard
also a very intuitive explanation. Since the circuit forces the
complementary CMOS oscillator.
same current in opposite nMOS and pMOS transistors, different
voltage amplitudes are required to compensate for the different
transistor gains. Focusing for example on the first half of the os- III. PHASE NOISE
cillation period, since the nMOS has more gain than the pMOS Following the linear time-variant (LTV) analysis approach
transistor ( ), the voltage driving the nMOS proposed by Hajimiry and Lee, the phase noise of a generic
MAZZANTI AND ANDREANI: PUSHPULL CLASS-C CMOS VCO 727
harmonic oscillator at an offset frequency from the carrier that is twice the amplitude that would be available with a single
can be expressed as [8], [29], [30] differential pair, yielding .
The effective noise contributed by each active pair is there-
fore
(10) (14)
TABLE I
SIMULATED OSCILLATION AMPLITUDE, NOISE CONTRIBUTIONS, AND PHASE
NOISE OF THE PUSHPULL CLASS-C OSCILLATOR FOR DIFFERENT VALUES
OF
is worth noticing the proportional increase of both nMOS and Fig. 5. Pushpull Class-C oscillator modified to accommodate a large voltage
pMOS contributions, even if the former never leave the satura- swing.
tion region. The primary mechanism behind the increased con-
tribution of transistors effective noise is the larger current con-
duction angle, when pMOS transistors enter the triode region, as waveforms depicted in Fig. 5. During the first half of the os-
previously shown in Fig. 3. As a result, both nMOS and pMOS cillation cycle, transistors and are pushed toward the
transistors inject thermal noise into the tank over a wider frac- triode region. The boundary condition for saturation of ,
tion of the oscillation period, leading to a larger integral noise , can be written as
expressed by (11). , where and are the peak voltage
We have focused our attention on the transistors of the pMOS magnitudes at the two tank nodes in the first half of the oscilla-
pair, but the same discussion, with similar qualitative results, is tion cycle, as shown in Fig. 5. Given the differential oscillation
also valid for the transistors of the nMOS pair. For an optimal amplitude , the minimum required to
phase-noise performance, it is therefore very important to avoid keep in saturation is
any transistors entering the deep triode region.
(17)
IV. PUSHPULL CLASS-C OSCILLATOR FOR
Looking now at , the saturation condition
LARGE VOLTAGE SWING
requires . Assuming the
To avoid excessive phase noise penalty, the zero-peak differ- external bias voltage for the nMOS pair is selected at the min-
ential voltage swing across the resonator must be comparable imum possible value, i.e., ,
or lower than a pMOS threshold voltage. While this limitation where is the minimum voltage to keep the tail current
can be acceptable in ultrascaled technologies having a supply source in saturation), the upper bound for the tank voltage swing
voltage of 1 V with 0.50.6-V high- transistor options, it is:
represents a significant penalty for realizations in less scaled
technology nodes. A modified pushpull Class-C oscillator ac- (18)
commodating a larger voltage swing is presented in Fig. 5. An
additional RC network is introduced to provide a dc bias voltage The tank steady-state dc common-mode voltage is set by the
for the gates of the pMOS pair ( ) higher than the tank pMOS pair and the level shifter
common-mode voltage, allowing a larger resonator swing be-
(19)
fore the pMOS pair is pushed into the triode region. This is the
same technique adopted to bias the nMOS pair, with the differ- Assuming is selected at the optimal value given by (17),
ence that is not applied externally, but is generated by and replacing (19) in (18), the constraint on the maximum tank
offsetting upward the tank common-mode voltage, , by voltage swing to ensure transistors do not enter the triode region
, with transistor working as level shifter. This is nec- is
essary to preserve a low common-mode tank impedance and a
well-defined common-mode voltage. The power required to bias
the level shifter is negligible, compared with the overall dissi-
pation in the oscillator. (20)
By selecting a moderately high time constant for the RC bi-
asing networks, the noise impressed on and the noise The absolute value of and is introduced in the last
generated by the level shifter providing are low-pass fil- expression to highlight that the steady-state overdrive voltage of
tered and do not deteriorate the oscillator phase noise. nMOS (pMOS) transistors working in Class-C is negative (pos-
itive). For practical transistor sizes, the magnitude of the over-
A. Maximum Oscillation Amplitude drives is in the range of 50100 mV. The tail current source
To estimate the optimal design value for and the max- transistor in the Class-C oscillator can be sized very large, since
imum allowed oscillation amplitude, we refer to the voltage its drain parasitic capacitance is absorbed in . The required
MAZZANTI AND ANDREANI: PUSHPULL CLASS-C CMOS VCO 729
minimum drain voltage for saturation ( ) is therefore of the robustness against single-ended tank capacitance, lead to
the order of 100 mV or even less, leading to a maximum tank a significant improvement of the spectral purity for a given
voltage swing, from (20), which is roughly half of the supply power dissipation in favor of the Class-C oscillator. This will
voltage.3 This is nevertheless quite a pessimistic estimate. In be also evident from the comparison of experimental results
fact, in deep-submicron technologies, the velocity saturation of against the performances of recently reported complementary
the charge carriers prevails on the channel pinch-off to deter- LC-tank oscillators, presented in Section V.
mine saturation of the drain current, and a magnitude of
lower than what has been assumed in the above derivation is
therefore sufficient to keep the transistors in the active region. V. EXPERIMENTAL RESULTS
A VCO based on the large-swing Class-C topology of Fig. 5
B. Comparison With the Standard Complementary has been designed in 0.18- m CMOS. To keep a low VCO
Differential-Pairs CMOS Oscillator gain, the tank capacitance is made of a small varactor for fine
The maximum theoretical oscillation amplitude for the stan- tuning and a bank of four digitally switched and binary-sized
dard LC-tank oscillator with complementary differential pairs metal-fringe capacitors for coarse tuning. The 1-nH inductor is
is - [27]. Thus, this oscillator theoretically allows a two-turn coil, and the estimated tank is 10. From (20), the
a larger maximum amplitude than the pushpull Class-C os- optimal oscillation amplitude is approximately half of the
cillator of Fig. 5. However, it should be noticed that, unlike supply voltage. Given a nominal supply of 1.8 V, the biasing
in the Class-C oscillator, cannot be selected below current is set to 1.2 mA, leading to a simulated of
a few hundred millivolts, because the tail-current-source tran- 900 mV. The aspect ratio of the nMOS ( - ) and pMOS
sistor must be designed with a relatively small aspect ratio and a ( - ) core transistors is, respectively, 42 m/0.18 m and
correspondingly large overdrive voltage to yield a low transcon- 60 m/0.18 m. Transistor is 15 m/0.2 m and is biased
ductance, since its high-frequency thermal noise (proportional close to the threshold voltage with a 10- A current, providing
to its transconductance) is not filtered out, impacting the os- a voltage shift of 470 mV. The VCO drives directly a pair
cillator phase noise [28]. Furthermore, the noise from the of open-drain buffers, supplied off-chip with bias-tees, to drive
tail-current-source transistor is an issue as well [12]. the 50- impedance of the measurement setup.
The phase noise of the standard complementary oscillator is The tail current source is realized with a transistor
also severely impaired by capacitors connected single-ended having an aspect ratio of 500 m/0.8 m. A nonminimum
to the resonator, i.e., capacitors connected between the differ- channel length is selected to limit the generation of
ential outputs and ground [15], [27]. Assuming a tail-biased noise, which would be (at least partially) translated into
standard complementary oscillator topology, at large oscilla- phase noise. At the same time, the very large width leads
tion amplitude the on-resistance of the pMOS transistors, en- to a minimum drain voltage for saturation, of only
tering the triode region, appears in parallel to the single ended 80 mV. The total tail capacitance , comprising the parasitic
tank capacitors, thus degrading the loaded tank and there- drain junction capacitance of the tail transistor and an explicit
fore phase noise. In a typical design, this mechanism leads to a metal-fringe capacitance, is 1.1 pF. This value is sufficiently
significant phase noise penalty if the single-ended capacitance large to keep an almost constant steady-state tail voltage, the
is a non-negligible fraction of the total tank capacitance [27] fundamental condition for Class-C operation of the core tran-
(and up to 10-dB penalty in the case of 100% single-ended sistors. On the other hand, similar to the single-differential-pair
tank capacitance [15]). This issue leads to a severe tradeoff be- Class-C oscillator, too large a tail capacitance would lead to an
tween frequency tuning range and phase noise, since the com- instability of the oscillation amplitude, a phenomenon referred
ponents mostly responsible for introducing single-ended tank to as squegging [14]. Simulations indicate that squegging
capacitances are the varactors in the case of continuous fre- appears for 1.7 pF, indicating a sufficiently safe sta-
quency tuning, and, if a switched-capacitor bank is used for dis- bility margin with 1.1 pF. No squegging is observed
crete tuning, the parasitic capacitances of the switches [7]. How- in measurements.
ever, since the core transistors of a correctly designed pushpull Fig. 6 shows the chip photograph. The die area, including
Class-C oscillator never leave the saturation region, its pMOS pads, is 650 m 430 m. Fig. 7 shows the tuning curves. The
transistors cannot discharge the single-ended parasitic capaci- VCO is tunable from 6.09 to 7.50 GHz in 16 widely overlapping
tances, allowing a large frequency tuning range without a sig- bands. The maximum gain, at the center of the tuning curves,
nificant phase-noise penalty. ranges from 110 to 164 MHz/V.
In summary, even if the maximum oscillation amplitude Phase-noise measurements are carried out with 1.8 V
for the standard complementary differential-pair oscillator is and a current consumption of 1.2 mA, corresponding to a power
theoretically larger than for the Class-C oscillator, the higher dissipation of 2.16 mW. Fig. 8 shows a typical phase-noise plot.
dc-to-RF current conversion efficiency, the use of a large The bias voltage for the nMOS pair , provided off-chip,
explicit capacitance at the common-source node, allowing a is set to a nominal value of 0.65 V. This value, which is slightly
very low and filtering-out the bias current noise, and higher than the optimal minimum value calculated in the pre-
vious section, sets a small-signal device transconductance suffi-
3The maximum tank voltage swing of the pushpull Class-C oscillator is half
ciently large to ensure a robust oscillator start-up. On the other
that of the originally reported Class-C oscillator based on a single differential
pair [14]. Following the same analysis reported in [27], the two oscillators have hand, as it has been discussed in [14] for the single-differential-
the same maximum phase noise FoM. pair Class-C oscillator, the sensitivity of phase noise to
730 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 48, NO. 3, MARCH 2013
TABLE II
PERFORMANCE SUMMARY AND COMPARISON WITH RECENTLY REPORTED CMOS VCOS EMPLOYING COMPLEMENTARY DIFFERENTIAL PAIRS
[32] J. Bank, A Harmonic-Oscillator Design Methodology based on De- over 50 technical papers. His main research interests cover device modeling
scribing Functions, Ph.D. dissertation, Dept. Signals and Syst., Sch. and IC design for high-speed communications and millimeter-wave systems.
Electr. Eng., Chalmers Univ. Technol., Gteborg, Sweden, 2006. Dr. Mazzanti has been a member of the Technical Program Committee of the
[33] T. Tokairin, M. Okada, M. Kitsunezuka, T. Maedaand, and M. IEEE Custom Integrated Circuit Conference (CICC) and the IEEE International
Fukaishi, A 2.1-to-2.8-GHz low-phase-noise all-digital frequency Conference on IC Design and Technology (ICICDT) since 2008. He is currently
synthesizer with a time-windowed time-to-digital converter, IEEE J. serving as an associate editor for the IEEE TRANSACTIONS ON CIRCUITS AND
Solid State Circuits, vol. 45, no. 12, pp. 25822590, Dec. 2010. SYSTEMSI: REGULAR PAPERS.
[34] J. Shin and H. Shin, A 1.93.8 GHz fractional- PLL frequency syn-
thesizer with fast auto-calibration of loop bandwidth and VCO fre-
quency, IEEE J. Solid State Circuits, vol. 47, no. 3, pp. 665675, Mar.
2012. Pietro Andreani (SM07) received the M.S.E.E. de-
[35] S. Levantino, M. Zanuso, C. Samori, and A. Lacaita, Suppression of gree from the University of Pisa, Pisa, Italy, in 1988,
flicker noise upconversion in a 65 nm CMOS VCO in the 3.0-to-3.6 and the Ph.D. degree from Lund University, Lund,
GHz band, in IEEE Int. Solid State Circuits Conf. Dig. of Tech. Papers, Sweden, in 1999.
Feb. 2010, pp. 5051. Between 2001 and 2007, he was Chair Professor
[36] D. Ponton, G. Knoblinger, A. Roithmeierl, M. Tiebout, M. Fulde, and with the Center for Physical Electronics, Tech-
P. Palestri, Assessment of the impact of technology scaling on the nical University of Denmark. Since 2007, he has
performance of LC-VCOs, in Proc. Eur. Solid State Circuits Conf., been an Associate Professor with the Department
Sep. 2009, pp. 364367. of Electrical and Information Technology, Lund
University, Lund, Sweden, where he is involved
Andrea Mazzanti (M09) received the Laurea and with analog/mixed-mode/RF IC design. He is also a
Ph.D. degrees in electrical engineering from the Uni- part-time IC Designer with ST-Ericsson, Lund.
versit di Modena and Reggio Emilia, Modena, Italy, Prof. Andreani has been a TPC member of ISSCC (20072012) and is a TPC
in 2001 and 2005, respectively. member of ESSCIRC.
During the summer of 2003, he was with Agere
Systems, Allentown, PA as an Intern. From 2006
to 2009, he was an Assistant Professor with the
Universit di Modena and Reggio Emilia, Modena,
Italy, where he taught a course on advanced analog
IC design. In January 2010, he joined the Universit
di Pavia, Pavia, Italy. He has authored or coauthored