Dell Inspiron

1 2 3 4 5 6 7 8
Corsica\Gilligan - DISCRETE
M08 M/B PCB
A VER : X02 A
POWER
POWER CLOCK
SYSTEM Merom CK505M+LP
RESET CIRCUIT PG 38 (478 Micro-FCPGA) REGULATOR PG 43 CPU VR PG 45
+1.5V_RUN/+1.05V_VCCP
PG 3,4
BATT REGULATOR PG 17
PG 40 PG 44 PG 42 DC/DC
AC/BATT CHARGER
(Symbol Rev.09) +1.25V/+1.8V_SUS/+0.9V_DDR_VTT +3.3V_ALW/+5V_ALW/+15V_ALW
CONNECTOR
RUN POWER SW PG 39
PG 41 +3.3V_SUS/+5V_SUS/+3.3V_M
+5V/+3.3V/+1.8V/+1.25_RUN 667/800 MHz FSB
LVDS
VGA CONN. Panel Connector
Crestline PCI EXPRESS GFX TVOUT S-Video

PCIEx16
B
DDR2-SODIMM1 533/667 MHZ DDR II PG 19 B
1299 uFCBGA
PG 15,16
VGA CRT CONN.
PG 5,6,7,8,9,10 PG 18
PG 19
533/667 MHZ DDR II
DDR2-SODIMM2
(Symbol Rev.09)
PG 15,16
USB2.0 (P5) Camera
PG 33
IDE LAN
DMI interface
CD-ROM BCM4401 (B0)
PG 23 +3.3V_LAN RJ45/Magnetics
33MHz PCI
PG 35
PG 36
SATA - HDD SATA0 ICH8-M (Symbol Rev.09)
33MHz PCI
PG 23
PCIEx1
676 BGA
USB2.0 (P6) CARDBUS/1394
SATA - HDD SATA1
PG 11,12,13,14 PCIEx1 R5C833
C PG 23 C
IHDA USB2.0 (P9) PG 20,21,22
PCIEx2
(Symbol Rev.09) USB2.0 (P7) EXPRESS-CARD
AUDIO/AMP MDC CONN
R5538
PG 32 PG 26
SPI LPC
MINI-CARD x1
PG 26
WWAN
D-Micro Audio Tip PG 25
Jacks Ring SIO SIO MINI-CARD x2
PG 33 PG 33 MEC5025 ECE5011
WLAN
128KB Flash BC Expander
BC TMKBC USB 2.0 Hub(4) PG 24
Dash BD USB2.0 (P0,P2) (EXT SIDE)
TP/KB External USB
PS/2 128 Pins VTQFP 128 Pins VTQFP USB2.0 (P3,P8) (EXT BACK)
& PG 27
PG 28 PG 29
D
KB Media/Dash BD D
SPI
Conn QUANTA
Touchpad FAN & THERMAL
PG 31 FLASH CIR
EMC4001 Title
COMPUTER
PG 31 Schematic Block Diagram1
PG 30 PG 34
Media BD Size Document Number Rev
C G M-08 0.1
31FM5MB0011 31GM2MB0004
41FM5SS0017 41GM2SS0000 Date: Tuesday, March 06, 2007 Sheet 1 of 51
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
INDEX Power & Ground

Pg# Description DNI LIST Label Pg# Description Control Signal
1 Schematic Block Diagram DC_IN+ AC ADAPTER (19V)
2 Front Page PBATT+ MAIN BATTERY + (10~17V)
3-4 Merom PBATT+ SECOND BATTERY + (10~17V)

A A
5-10 Crestline PWR_SRC MAIN POWER (10~19V)
11-14 ICH8M RTC_PWR3_3V RTC & +3.3V_RTC_LDO(3.3V)
15-16 DDRII SO-DIMM(200P) +VCC_CORE CPU CORE POWER (1.5V) RUNPWROK
17 Clock Generator +15V_ALW LARGE POWER (15V) SUS_ON
18-21 VGA +3.3V_RUN SLP_S3# CTRLD POWER RUN_ON
22 LCD Conn. & SSP +3.3V_SUS SLP_S5# CTRLD POWER SUS_ENABLE
23 CRT Conn +3.3V_ALW 8051 POWER (3.3V) ALWON/THERM_STP#
24 SATA & IDE Conn +5V_RUN SLP_S3# CTRLD POWER RUN_ON
25 PCCARD/Conn & 1394 +5V_SUS SLP_S5# CTRLD POWER SUS_ON
26 Express Card & Smart Card +5V_HDD HDD POWER (5V) +5V_RUN
B B
27 Mini Card +5V_MOD MODULE POWER (5V) HDDC_EN
28 MDC Conn. +5V_ALW LCD/CHARGE POWER (5V)
29 SIO (MEC5004) +VDDA AUDIO ANALOG POWER (5V) AUDIO_AVDD_ON
30 SIO (MEC5018) +1.5V_RUN CALISTOGA/ICH7 POWER RUN_ON
31 SERIAL PORT & USB +1.05V_VCCP CPU/CALISTOGA/ICH7 POWER RUN_ON
32 Flash ROM +1_8V_SUS SODIMM POWER SUSPWROK_5V
33 TP,BT & FIR +1.8V_RUN SDVO POWER RUN_ON
34 Switch,Keyboard & LED +0.9V_DDR_VTT SODIMM POWER RUN_ON
35 FAN & Thermal +3.3V_LAN LAN POWER AUX_EN
C 36-37 Audio CODEC(STAC9200)/Phone Jack C
38-39 LOM (BCM5752)/Switch

40-41 Docking Conn/Q-Switch GND ALL PAGES DIGITAL GROUND
42 System Reset Circuit AGND_ISL6260 CPU GND
43-44 Battery Selector & Charger DC/DC POWER GND
45 DDR2_1.8VSUS, 0.9V AGND1 VTT POWER GND
46 1.5VSUS,1.05V(VTT) AGND2 VTT POWER GND
47 1.25V,1.05VM 8731AGND CHARGER GND
48 CPU_MAX8786(3phase)
49 D/D Power
D 50 RUN Power Switch D
51 VGA DC/DC QUANTA

52 DCIN/Batt Conn.
Title
COMPUTER
53 Index, DNI, Power & Ground
PAD& SCREW
Size Document Number Rev
54 M-08 0.1
EMI CAP
Date: Monday, March 05, 2007 Sheet 2 of 51
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
H_A#[3..16] U15A H_D#[0..63] U15B H_D#[0..63]

<5> H_A#[3..16] <5> H_D#[0..63] H_D#[0..63] <5>
H_A#3 J4 H1 H_D#0 E22 Y22 H_D#32
A[3]# ADS# H_ADS# <5> D[0]# D[32]#
H_A#4 L5 E2 H_D#1 F24 AB24 H_D#33
A[4]# BNR# H_BNR# <5> D[1]# D[33]#
H_A#5 L4 G5 H_D#2 E26 V24 H_D#34
A[5]# BPRI# H_BPRI# <5> D[2]# D[34]#
H_A#6 K5 H_D#3 G22 V26 H_D#35
H_A#7 A[6]# H_D#4 D[3]# D[35]# H_D#36
M3 A[7]# DEFER# H5 H_DEFER# <5> F23 D[4]# D[36]# V23
H_A#8 N2 F21 H_D#5 G25 T22 H_D#37
A[8]# DRDY# H_DRDY# <5> D[5]# D[37]#
H_A#9 J1 E1 H_D#6 E25 U25 H_D#38
A[9]# DBSY# H_DBSY# <5> D[6]# D[38]#
H_A#10 N3 H_D#7 E23 U23 H_D#39
A A[10]# H_BR0# <5> D[7]# D[39]# A
ADDR GROUP 0
DATA GRP 0
DATA GRP 2
H_A#11 P5 F1 H_D#8 K24 Y25 H_D#40
H_A#12 A[11]# BR0# R346 56 H_D#9 D[8]# D[40]# H_D#41
P2 A[12]# G24 D[9]# D[41]# W22
H_A#13 L2 D20 H_IERR# 1 2 H_D#10 J24 Y23 H_D#42
CONTROL
A[13]# IERR# +1.05V_VCCP D[10]# D[42]#
H_A#14 P4 B3 H_D#11 J23 W24 H_D#43
A[14]# INIT# H_INIT# <11> D[11]# D[43]#
H_A#15 P1 H_D#12 H22 W25 H_D#44
H_A#16 A[15]# H_D#13 D[12]# D[44]# H_D#45
R1 A[16]# LOCK# H4 H_LOCK# <5> F26 D[13]# D[45]# AA23
M1 H_D#14 K22 AA24 H_D#46
<5> H_ADSTB#0 H_REQ#[0..4] ADSTB[0]# D[14]# D[46]#
C1 H_RESET# H_D#15 H23 AB25 H_D#47
<5> H_REQ#[0..4] RESET# H_RESET# <5> D[15]# D[47]#
H_REQ#0 K3 F3 J26 Y26
REQ[0]# RS[0]# H_RS#0 <5> <5> H_DSTBN#0 DSTBN[0]# DSTBN[2]# H_DSTBN#2 <5>
H_REQ#1 H2 F4 H26 AA26
REQ[1]# RS[1]# H_RS#1 <5> <5> H_DSTBP#0 DSTBP[0]# DSTBP[2]# H_DSTBP#2 <5>
H_REQ#2 K2 G3 H25 U22
REQ[2]# RS[2]# H_RS#2 <5> <5> H_DINV#0 DINV[0]# DINV[2]# H_DINV#2 <5>
H_REQ#3 J3 G2
REQ[3]# TRDY# H_TRDY# <5> H_D#[0..63] H_D#[0..63]
H_REQ#4 L1
H_A#[17..35] REQ[4]# <5> H_D#[0..63] H_D#[0..63] <5>
G6 H_D#16 N22 AE24 H_D#48
<5> H_A#[17..35] HIT# H_HIT# <5> D[16]# D[48]#
H_A#17 Y2 E4 H_D#17 K25 AD24 H_D#49
A[17]# HITM# H_HITM# <5> D[17]# D[49]#
H_A#18 U5 H_D#18 P26 AA21 H_D#50
H_A#19 A[18]# ITP_BPM#0 H_D#19 D[18]# D[50]# H_D#51
R3 A[19]# BPM[0]# AD4 R23 D[19]# D[51]# AB22
H_A#20 W6 AD3 ITP_BPM#1 Layout Note: H_D#20 L23 AB21 H_D#52
A[20]# BPM[1]# D[20]# D[52]#
ADDR GROUP 1
H_A#21 U4 AD1 ITP_BPM#2 H_D#21 M24 AC26 H_D#53
XDP/ITP SIGNALS
H_A#22 A[21]# BPM[2]# ITP_BPM#3
Place voltage H_D#22 D[21]# D[53]# H_D#54
Y5 A[22]# BPM[3]# AC4 L22 D[22]# D[54]# AD20
divider within
DATA GRP 1
DATA GRP 3
H_A#23 U1 AC2 ITP_BPM#4 H_D#23 M23 AE22 H_D#55
H_A#24 A[23]# PRDY# ITP_BPM#5 0.5" of GTLREF H_D#24 D[23]# D[55]# H_D#56
R4 A[24]# PREQ# AC1 P25 D[24]# D[56]# AF23
H_A#25 T5 AC5 ITP_TCK pin H_D#25 P23 AC25 H_D#57
H_A#26 A[25]# TCK ITP_TDI H_D#26 D[25]# D[57]# H_D#58
T3 A[26]# TDI AA6 P22 D[26]# D[58]# AE21
H_A#27 W2 AB3 ITP_TDO H_D#27 T24 AD21 H_D#59
H_A#28 A[27]# TDO ITP_TMS +1.05V_VCCP H_D#28 D[27]# D[59]# H_D#60
W5 A[28]# TMS AB5 R24 D[28]# D[60]# AC22
H_A#29 Y4 AB6 ITP_TRST# H_D#29 L25 AD23 H_D#61
H_A#30 A[29]# TRST# ITP_DBRESET# H_D#30 D[29]# D[61]# H_D#62
U2 A[30]# DBR# C20 ITP_DBRESET# <13,29> T25 D[30]# D[62]# AF22
2
H_A#31 V4 H_D#31 N25 AC23 H_D#63
H_A#32 A[31]# R344 56 R402 D[31]# D[63]#
B W3 A[32]# <5> H_DSTBN#1 L26 DSTBN[1]# DSTBN[3]# AE25 H_DSTBN#3 <5> B
H_A#33 AA4 THERMAL 2 1 +1.05V_VCCP 1K/F M26 AF24
A[33]# <5> H_DSTBP#1 DSTBP[1]# DSTBP[3]# H_DSTBP#3 <5>
H_A#34 AB2 R340 0_NC N24 AC20
A[34]# <5> H_DINV#1 DINV[1]# DINV[3]# H_DINV#3 <5>
H_A#35 AA3 D21 CPU_PROCHOT# 1 2 EC_CPU_PROCHOT# <28>
1
A[35]# PROCHOT# H_THERMDA V_CPU_GTLREF AD26 COMP0
<5> H_ADSTB#1 V1 ADSTB[1]# THERMDA A24 H_THERMDA <34> GTLREF COMP[0] R26 Note:
B25 H_THERMDC CPU_TEST1 C23 MISC COMP[1] U26 COMP1 H_DPRTSTP need to daisy chain
THERMDC H_THERMDC <34> TEST1
2
A6 CPU_TEST2 D25 AA1 COMP2
<11> H_A20M# A20M# TEST2 COMP[2] from ICH8 to IMVP6 to CPU.
A5 C7 H_THERMTRIP# CPU_TEST3 C24 Y1 COMP3
<11> H_FERR# FERR# THERMTRIP# H_THERMTRIP# <34> TEST3 COMP[3]
ICH
C4 R330 56 R404 CPU_TEST4 AF26

<11> H_IGNNE# IGNNE# TEST4
1 2 +1.05V_VCCP 2K/F CPU_TEST5 AF1 E5
TEST5 DPRSTP# H_DPRSTP# <6,11,45>
D5 H CLK CPU_TEST6 A26 B5
<11> H_STPCLK# H_DPSLP# <11>
1
STPCLK# TEST6 DPSLP#
<11> H_INTR C6 LINT0 DPWR# D24 H_DPWR# <5>
<11> H_NMI B4 LINT1 BCLK[0] A22 CLK_CPU_BCLK <17> <6,17> CPU_MCH_BSEL0 B22 BSEL[0] PWRGOOD D6 H_PWRGOOD <11>
<11> H_SMI# A3 SMI# BCLK[1] A21 CLK_CPU_BCLK# <17> <6,17> CPU_MCH_BSEL1 B23 BSEL[1] SLP# D7 H_CPUSLP# <5>
<6,17> CPU_MCH_BSEL2 C21 BSEL[2] PSI# AE6 H_PSI# <45>
M4 RSVD[01]
N5 Merom Ball-out Rev 1a
RSVD[02] C163
T2 RSVD[03]
V3 H_THERMDA 1 2 H_THERMDC
RSVD[04]
RESERVED
B2 RSVD[05]
C3 2200P/50V_NC R331 1K/F_NC PAD T17 CPU_TEST3
RSVD[06] CPU_TEST1 CPU_TEST5
D2 RSVD[07] 1 2 PAD T97
D22 R106 1K/F_NC
RSVD[08] CPU_TEST2
D3 RSVD[09] 1 2 For the purpose of testability, route these signals
F6 C520 0.1U/10V_NC through a ground referenced Z0 = 55ohm trace that
RSVD[10] CPU_TEST4
2 1
R332 0_NC ends in a via that is near a GND via and is
1 2 CPU_TEST6 accessible through an oscilloscope connection.
Merom Ball-out Rev 1a
C C
For Support XDP: Place C close to the
1. ITP_BPM#5 need PU 51ohms to +1.05V_VCCP. CPU_TEST4 pin. Make sure
FSB BCLK BSEL2 BSEL1 BSEL0 COMP0
Populate ITP700Flex for bringup 2. Change R4 & R361 to 51 ohms. CPU_TEST4 routing is COMP1
3. Changed R6 & R346 to 51 ohms. reference to GND and away COMP2
533 133 0 0 1
+1.05V_VCCP 4. Depopulate R2 and changed R8 to 1K/F. from other noisy signal. COMP3
667 166 0 1 1
Layout Note:
2
Place couple 0.1uF Decoupling 800 200 0 1 0
R398 R400 R392 R388
caps with in 0.1" ITP connector.
1
54.9/F 27.4/F 54.9/F 27.4/F

R352 R354 R408 R409
51/F 51 39/F 150 +1.05V_VCCP +3.3V_ALW +3.3V_SUS
1
ITP700 layout guidelines
JITP1 C476 0.1U/10V
2
2 1 Signal Resistor Value Connect To Resistor Placement Comp0,2 connect with Zo=27.4ohm,Comp1,3
0_NCR414
R414
ITP_TDI 1 27 connect with Zo=55ohm, make those traces

TDI VTT0
2
ITP_TMS 2 28 C472 0.1U/10V TDI 150 ohm 5% VCCP Place the pull-up near CPU
TMS VTT1 length shorter than 0.5".Trace should be
0R416
0_NC
ITP_TCK 5 26 2 1
ITP_TDO R3531 TCK VTAP at least 25 mils away from any other
2 0 7 TDO TMS 39 ohm 1% VCCP Within 200ps of ITP connector
ITP_TRST# 3 toggling signal.
TRST#
500 to 680
1
R351 22.6/F R412 150 TRST# ohm 5% GND Place the pull-down near CPU
H_RESET# 1 2 12 25 ITP_DBRESET# 2 1
RESET# DBR#
Layout Note: DBA# 24 Connect to TCK pin of CPU and then
ITP_TCK
Place R8 close ITP. connect it to FBO pin of ITP connector
11 FBO
TCK 27 ohm 1% GND in daisy chain. Place the pull-down
<17> CLK_CPU_ITP# 8 BCLKN
near TCK0 pin of ITP connector
D 9 23 ITP_BPM#0 D
<17> CLK_CPU_ITP BCLKP BPM0#
21 ITP_BPM#1 +1.05V_VCCP TDO 51 ohm 5% VCCP Place the pull-up near ITP
BPM1# ITP_BPM#2
BPM2# 19
10 17 ITP_BPM#3 Connect to CPURST# pin of GMCH through
GND0 BPM3# ITP_BPM#4
14 15 22.6 ohm 1%
R350 27/F
ITP_TCK
16
GND1
GND2
BPM4#
BPM5# 13 ITP_BPM#51
R403
2
51_NC
series resistor
the series resistor placed within
200ps of ITP connector. Place the
DELL CONFIDENTIAL/PROPRIETARY
2 1 18 GND3 NC0 4 RESET# and pullup 51 VCCP
20 GND4 NC1 6 Reserved for support pull-up after the series resistor from
R406 649/F 22 GND5 GND_0 29 XDP debug. ohm 1%. ITP connector. Title
2 1 ITP_TRST# 30 Merom Processor (HOST BUS)
GND_1
ITP700Flex_NC Size Document Number Rev
M-08 0.1

1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
+VCC_CORE +VCC_CORE
U15C U15D
A7 VCC[001] VCC[068] AB20 A4 VSS[001] VSS[082] P6
A9 VCC[002] VCC[069] AB7 A8 VSS[002] VSS[083] P21
+VCC_CORE All use 10U 4V(+-20%,X6S,0805)Pb-Free. A10 AC7 A11 P24
VCC[003] VCC[070] VSS[003] VSS[084]
A12 VCC[004] VCC[071] AC9 A14 VSS[004] VSS[085] R2
1
C492 C203 C204 C205 C206 A18 AC17 AF2 T1
10U/4V 10U/4V 10U/4V 10U/4V 10U/4V VCC[008] VCC[075] VSS[008] VSS[089]
A20 AC18 B6 T4
2
2
A VCC[009] VCC[076] VSS[009] VSS[090] A
B7 VCC[010] VCC[077] AD7 B8 VSS[010] VSS[091] T23
B9 VCC[011] VCC[078] AD9 B11 VSS[011] VSS[092] T26
B10 VCC[012] VCC[079] AD10 B13 VSS[012] VSS[093] U3
+VCC_CORE B14 AD14 B19 U21
VCC[014] VCC[081] VSS[014] VSS[095]
B17 VCC[016] VCC[083] AD17 B24 VSS[016] VSS[097] V2
B18 VCC[017] VCC[084] AD18 C5 VSS[017] VSS[098] V5
1
1
B20 VCC[018] VCC[085] AE9 C8 VSS[018] VSS[099] V22
C508 C507 C207 C208 C462 C9 AE10 C11 V25
10U/4V 10U/4V 10U/4V 10U/4V 10U/4V VCC[019] VCC[086] VSS[019] VSS[100]
C10 AE12 C14 W1
2
2
VCC[020] VCC[087] VSS[020] VSS[101]
C12 VCC[021] VCC[088] AE13 C16 VSS[021] VSS[102] W4
8 inside cavity, north side, secondary layer. C17 VCC[024] VCC[091] AE18 C22 VSS[024] VSS[105] Y3
C18 VCC[025] VCC[092] AE20 C25 VSS[025] VSS[106] Y6
D9 VCC[026] VCC[093] AF9 D1 VSS[026] VSS[107] Y21
+VCC_CORE D10 AF10 D4 Y24
VCC[027] VCC[094] VSS[027] VSS[108]
D12 VCC[028] VCC[095] AF12 D8 VSS[028] VSS[109] AA2
1
1
C503 C502 C506 C505 C504 D18 AF18 D19 AA14
10U/4V 10U/4V 10U/4V 10U/4V 10U/4V VCC[032] VCC[099] +1.05V_VCCP VSS[032] VSS[113]
E7 AF20 D23 AA16
2
2
VCC[033] VCC[100] VSS[033] VSS[114]
E9 VCC[034] D26 VSS[034] VSS[115] AA19
E10 VCC[035] VCCP[01] G21 E3 VSS[035] VSS[116] AA22
E12 VCC[036] VCCP[02] V6 E6 VSS[036] VSS[117] AA25
1
E13 VCC[037] VCCP[03] J6 E8 VSS[037] VSS[118] AB1
+VCC_CORE E15 K6 + C487 E11 AB4
VCC[038] VCCP[04] 220U/4V VSS[038] VSS[119]
B E17 VCC[039] VCCP[05] M6 E14 VSS[039] VSS[120] AB8 B
E18 J21 E16 AB11
2
VCC[040] VCCP[06] VSS[040] VSS[121]
E20 VCC[041] VCCP[07] K21 E19 VSS[041] VSS[122] AB13
1
1
F7 VCC[042] VCCP[08] M21 E21 VSS[042] VSS[123] AB16
C448 C447 C501 C442 C449 F9 N21 E24 AB19
10U/4V 10U/4V 10U/4V 10U/4V 10U/4V VCC[043] VCCP[09] VSS[043] VSS[124]
F10 N6 F5 AB23
2
2
VCC[044] VCCP[10] VSS[044] VSS[125]
F12 VCC[045] VCCP[11] R21 F8 VSS[045] VSS[126] AB26
F14 R6 +1.5V_RUN F11 AC3
VCC[046] VCCP[12] VSS[046] VSS[127]
F15 VCC[047] VCCP[13] T21 F13 VSS[047] VSS[128] AC6
8 inside cavity, south side, secondary layer. F17 VCC[048] VCCP[14] T6 F16 VSS[048] VSS[129] AC8
F18 VCC[049] VCCP[15] V21 F19 VSS[049] VSS[130] AC11
F20 VCC[050] VCCP[16] W21 F2 VSS[050] VSS[131] AC14
AA7 VCC[051] F22 VSS[051] VSS[132] AC16
+VCC_CORE AA9 B26 F25 AC19
VCC[052] VCCA[01] VSS[052] VSS[133]
AA10 VCC[053] VCCA[02] C26 G4 VSS[053] VSS[134] AC21
AA12 VCC[054] G1 VSS[054] VSS[135] AC24
1
AA13 AD6 C430 C440 G23 AD2
VCC[055] VID[0] VID0 <45> VSS[055] VSS[136]
1
AA15 AF5 0.01U/25V 10U/4V G26 AD5

VCC[056] VID[1] VID1 <45> VSS[056] VSS[137]
C491 C458 C443 C444 C445 C446 AA17 AE5 H3 AD8
VID2 <45>
2
10U/4V 10U/4V 10U/4V 10U/4V 10U/4V 10U/4V VCC[057] VID[2] VSS[057] VSS[138]
AA18 AF4 VID3 <45> H6 AD11
2
VCC[058] VID[3] VSS[058] VSS[139]

AA20 VCC[059] VID[4] AE3 VID4 <45> H21 VSS[059] VSS[140] AD13
AB9 VCC[060] VID[5] AF3 VID5 <45> H24 VSS[060] VSS[141] AD16
AC10 VCC[061] VID[6] AE2 VID6 <45> J2 VSS[061] VSS[142] AD19
6 inside cavity, north side, primary layer. AB10 VCC[062] J5 VSS[062] VSS[143] AD22
AB12 VCC[063] Layout Note: J22 VSS[063] VSS[144] AD25
AB14 AF7 VCCSENSE Place C105 near PIN J25 AE1
VCC[064] VCCSENSE VCCSENSE <45> VSS[064] VSS[145]
+VCC_CORE AB15 K1 AE4
VCC[065] B26. VSS[065] VSS[146]
AB17 VCC[066] K4 VSS[066] VSS[147] AE8
AB18 AE7 VSSSENSE K23 AE11
VCC[067] VSSSENSE VSSSENSE <45> VSS[067] VSS[148]
K26 VSS[068] VSS[149] AE14
1
C C
Merom Ball-out Rev 1a L3 AE16
C184 C185 C186 C187 C188 C189 VSS[069] VSS[150]
. L6 VSS[070] VSS[151] AE19
10U/4V 10U/4V 10U/4V 10U/4V 10U/4V 10U/4V L21 AE23
2
+VCC_CORE VSS[071] VSS[152]

L24 VSS[072] VSS[153] AE26
M2 VSS[073] VSS[154] A2
1
M5 VSS[074] VSS[155] AF6
6 inside cavity, south side, primary layer. R413 M22 AF8
100/F VSS[075] VSS[156]
M25 VSS[076] VSS[157] AF11
N1 VSS[077] VSS[158] AF13
N4 AF16
2
VSS[078] VSS[159]
N23 VSS[079] VSS[160] AF19
VCCSENSE N26 AF21
VSSSENSE VSS[080] VSS[161]
P3 VSS[081] VSS[162] A25
+PWR_SRC 60 AF25
VSS[163]
1
+1.05V_VCCP
R410 Merom Ball-out Rev 1a
1
1
100/F .
+ C250 + C53 + C98 + C249
1
100U/25V 100U/25V 100U/25V_NC 100U/25V
2
C490 C461 C489 C460 C488 C459
2
0.1U/10V 0.1U/10V 0.1U/10V 0.1U/10V 0.1U/10V 0.1U/10V

2
Route VCCSENSE and VSSSENSE

Layout Note: traces at 27.4ohms and
Layout out: Need to add 100uF cap on PWR_SRC for cap singing. length matched to within 25
Place these inside socket cavity on North side secondary. Place on PWR_SRC near +VCC_CORE. mil. Place PU and PD within
2 inch of CPU.
D D
Title
Merom Processor (POWER)

M-08 0.1

1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
U19A H_A#[3..35]
H_D#[0..63] H_A#[3..35] <3>
J13 H_A#3
<3> H_D#[0..63] H_A#_3
H_D#0 E2 B11 H_A#4
H_D#1 H_D#_0 H_A#_4 H_A#5
A
G2 H_D#_1 H_A#_5 C11 A
H_D#2 G7 M11 H_A#6
H_D#3 H_D#_2 H_A#_6 H_A#7
M6 H_D#_3 H_A#_7 C15
H_D#4 H7 F16 H_A#8
H_D#5 H_D#_4 H_A#_8 H_A#9
H3 H_D#_5 H_A#_9 L13
H_D#6 G4 G17 H_A#10
H_D#7 H_D#_6 H_A#_10 H_A#11
F3 H_D#_7 H_A#_11 C14
H_D#8 N8 K16 H_A#12
H_D#9 H_D#_8 H_A#_12 H_A#13
H2 H_D#_9 H_A#_13 B13
H_D#10 M10 L16 H_A#14
H_D#11 H_D#_10 H_A#_14 H_A#15
N12 H_D#_11 H_A#_15 J17
H_D#12 N9 B14 H_A#16
+1.05V_VCCP H_D#13 H_D#_12 H_A#_16 H_A#17
H5 H_D#_13 H_A#_17 K19
H_D#14 P13 P15 H_A#18
H_D#15 H_D#_14 H_A#_18 H_A#19
K9 H_D#_15 H_A#_19 R17
H_D#16 M2 B16 H_A#20
H_D#_16 H_A#_20
1
H_D#17 W10 H20 H_A#21

R360 H_D#18 H_D#_17 H_A#_21 H_A#22
Y8 H_D#_18 H_A#_22 L19
221/F H_D#19 V4 D17 H_A#23
H_D#20 H_D#_19 H_A#_23 H_A#24
M3 H_D#_20 H_A#_24 M17
H_D#21 J1 N16 H_A#25
2
H_SWING H_D#22 H_D#_21 H_A#_25 H_A#26

N5 H_D#_22 H_A#_26 J19
H_D#23 N3 B18 H_A#27
H_D#_23 H_A#_27
1
H_D#24 W6 E19 H_A#28

H_D#_24 H_A#_28
2
R368 H_D#25 W9 B17 H_A#29

100/F C465 H_D#26 H_D#_25 H_A#_29 H_A#30
N2 H_D#_26 H_A#_30 B15
0.1U/10V H_D#27 Y7 E17 H_A#31
1
H_D#28 H_D#_27 H_A#_31 H_A#32

Y9 C18
2
H_D#29 H_D#_28 H_A#_32 H_A#33

P4 H_D#_29 H_A#_33 A19
H_D#30 W3 B19 H_A#34
H_D#31 H_D#_30 H_A#_34 H_A#35
B N1 H_D#_31 H_A#_35 N19 B
H_D#32 AD12
H_D#33 H_D#_32
AE3 H_D#_33 H_ADS# G12 H_ADS# <3>
H_D#34 AD9 H17
H_D#_34 H_ADSTB#_0 H_ADSTB#0 <3>
H_D#35 AC9 G20
H_D#_35 H_ADSTB#_1 H_ADSTB#1 <3>
HOST
H_D#36 AC7 C8
H_D#_36 H_BNR# H_BNR# <3>
+1.05V_VCCP H_D#37 AC14 E8
H_D#_37 H_BPRI# H_BPRI# <3>
H_D#38 AD11 F12
H_D#_38 H_BREQ# H_BR0# <3>
H_D#39 AC11 D6
H_D#_39 H_DEFER# H_DEFER# <3>
H_D#40 AB2 C10
H_D#_40 H_DBSY# H_DBSY# <3>
H_D#41 AD7 AM5
H_D#_41 HPLL_CLK CLK_MCH_BCLK <17>
1
H_D#42 AB1 AM7

H_D#_42 HPLL_CLK# CLK_MCH_BCLK# <17>
R401 R399 H_D#43 Y3 H8
H_D#_43 H_DPWR# H_DPWR# <3>
54.9/F 54.9/F H_D#44 AC6 K7
H_D#_44 H_DRDY# H_DRDY# <3>
H_D#45 AE2 E4
H_D#_45 H_HIT# H_HIT# <3>
H_D#46 AC5 C6 H_HITM# <3>
2
H_SCOMP H_D#47 H_D#_46 H_HITM#

AG3 H_D#_47 H_LOCK# G10 H_LOCK# <3>
H_SCOMP# H_D#48 AJ9 B7
H_D#_48 H_TRDY# H_TRDY# <3>
H_D#49 AH8
H_RCOMP H_D#50 H_D#_49
AJ14 H_D#_50
H_D#51 AE9 H_D#_51
1
H_D#52 AE11
R361 H_D#53 H_D#_52
AH12 H_D#_53 H_DINV#_0 K5 H_DINV#0 <3>
24.9/F H_D#54 AJ5 L2
H_D#_54 H_DINV#_1 H_DINV#1 <3>
H_D#55 AH5 AD13
H_D#_55 H_DINV#_2 H_DINV#2 <3>
Layout Note: H_D#56 AJ6 AE13 H_DINV#3 <3>
2
H_D#57 H_D#_56 H_DINV#_3

H_RCOMP trace should be AE7 H_D#_57
H_D#58 AJ7 M7
10-mil wide with 20-mil H_D#_58 H_DSTBN#_0 H_DSTBN#0 <3>
H_D#59 AJ2 K3
H_D#_59 H_DSTBN#_1 H_DSTBN#1 <3>
C
spacing. H_D#60 AE5 H_D#_60 H_DSTBN#_2 AD2 H_DSTBN#2 <3> C
H_D#61 AJ3 AH11
H_D#_61 H_DSTBN#_3 H_DSTBN#3 <3>
H_D#62 AH2
H_D#63 H_D#_62
AH13 H_D#_63 H_DSTBP#_0 L7 H_DSTBP#0 <3>
H_DSTBP#_1 K2 H_DSTBP#1 <3>
H_DSTBP#_2 AC2 H_DSTBP#2 <3>
H_SWING B3 AJ10
+1.05V_VCCP H_SWING H_DSTBP#_3 H_DSTBP#3 <3>
H_RCOMP C2 H_RCOMP
H_REQ#_0 M14 H_REQ#0 <3>
H_SCOMP W1 E13
H_SCOMP H_REQ#_1 H_REQ#1 <3>
2
H_SCOMP# W2 A11
H_SCOMP# H_REQ#_2 H_REQ#2 <3>
R357 H13
H_REQ#_3 H_REQ#3 <3>
1K/F B6 B12
<3> H_RESET# H_CPURST# H_REQ#_4 H_REQ#4 <3>
<3> H_CPUSLP# E5 H_CPUSLP#
E12 H_RS#0 <3>
1
H_RS#_0
H_RS#_1 D7 H_RS#1 <3>
H_RS#_2 D8 H_RS#2 <3>
H_REF B9 H_AVREF
A9 H_DVREF
1
CRESTLINE_1p0 AJ0QP210T00
1
R362 C456
2K/F 0.1U/10V
2
2
Layout Note:
Place the 0.1 uF
D decoupling capacitor D
within 100 mils from
GMCH pins.
Title
Crestline (HOST)

M-08 0.1
Date: Tuesday, March 06, 2007 Sheet 5 of 51

1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
U19B U19C +VCC_PEG

+1.8V_SUS
P36 J40 R389 24.9/F
RSVD1 L_BKLT_CTRL
1
P37 AV29 H39 N43 VCC3G_PCIE_R 1 2
RSVD2 SM_CK_0 M_CLK_DDR0 <15> L_BKLT_EN PEG_COMPI
R35 BB23 +1.8V_SUS E39 M43
RSVD3 SM_CK_1 M_CLK_DDR1 <15> L_CTRL_CLK PEG_COMPO
R421 N35 BA25 E40
RSVD4 SM_CK_3 M_CLK_DDR2 <15> L_CTRL_DATA
1K/F AR12 AV23 C37
RSVD5 SM_CK_4 M_CLK_DDR3 <15> L_DDC_CLK PCIE_MRX_GTX_N[0..15] <18>
1
AR13 D35 J51 PCIE_MRX_GTX_N0
2
SM_RCOMP_VOH RSVD6 L_DDC_DATA PEG_RX#_0 PCIE_MRX_GTX_N1
AM12 RSVD7 SM_CK#_0 AW30 M_CLK_DDR#0 <15> K40 L_VDD_EN PEG_RX#_1 L51
AN13 BA23 R424 N47 PCIE_MRX_GTX_N2
RSVD8 SM_CK#_1 M_CLK_DDR#1 <15> PEG_RX#_2
1
1
C564 C559 J12 AW25 20/F L41 T45 PCIE_MRX_GTX_N3
RSVD9 SM_CK#_3 M_CLK_DDR#2 <15> LVDS_IBG PEG_RX#_3
0.01U/25V 2.2U/10V AR37 AW23 L43 T50 PCIE_MRX_GTX_N4
M_CLK_DDR#3 <15>
2
R425 RSVD10 SM_CK#_4 SMRCOMPP LVDS_VBG PEG_RX#_4 PCIE_MRX_GTX_N5
AM36 N41 U40
2
A
3.01K/F RSVD11 SMRCOMPN LVDS_VREFH PEG_RX#_5 PCIE_MRX_GTX_N6 A
AL36 RSVD12 SM_CKE_0 BE29 DDR_CKE0_DIMMA <15,16> N40 LVDS_VREFL PEG_RX#_6 Y44
AM37 AY32 D46 Y40 PCIE_MRX_GTX_N7
DDR_CKE1_DIMMA <15,16>
2
RSVD13 SM_CKE_1 LVDSA_CLK# PEG_RX#_7
1
D20 BD39 C45 AB51 PCIE_MRX_GTX_N8
DDR_CKE2_DIMMB <15,16>
MUXING
SM_RCOMP_VOL RSVD14 SM_CKE_3 LVDSA_CLK PEG_RX#_8 PCIE_MRX_GTX_N9
SM_CKE_4 BG37 DDR_CKE3_DIMMB <15,16> D44 LVDSB_CLK# PEG_RX#_9 W49
R422 E42 AD44 PCIE_MRX_GTX_N10
LVDSB_CLK PEG_RX#_10
1
LVDS
C563 C560 BG20 20/F AD40 PCIE_MRX_GTX_N11
SM_CS#_0 DDR_CS0_DIMMA# <15,16> PEG_RX#_11
0.01U/25V 2.2U/10V BK16 G51 AG46 PCIE_MRX_GTX_N12
DDR_CS1_DIMMA# <15,16>
2
R426 SM_CS#_1 LVDSA_DATA#_0 PEG_RX#_12 PCIE_MRX_GTX_N13
BG16 DDR_CS2_DIMMB# <15,16> E51 AH49
2
1K/F SM_CS#_2 LVDSA_DATA#_1 PEG_RX#_13 PCIE_MRX_GTX_N14

H10 RSVD20 SM_CS#_3 BE13 DDR_CS3_DIMMB# <15,16> F49 LVDSA_DATA#_2 PEG_RX#_14 AG45
B51 AG41 PCIE_MRX_GTX_N15
2
RSVD21 PEG_RX#_15
BJ20 RSVD22 SM_ODT_0 BH18 M_ODT0 <15,16> PCIE_MRX_GTX_P[0..15] <18>
RSVD
PCIE_MRX_GTX_P0
GRAPHICS
BK22 RSVD23 SM_ODT_1 BJ15 M_ODT1 <15,16> G50 LVDSA_DATA_0 PEG_RX_0 J50
+1.25V_RUN PCIE_MRX_GTX_P1
BF19 RSVD24 SM_ODT_2 BJ14 M_ODT2 <15,16> Non-iAMT E50 LVDSA_DATA_1 PEG_RX_1 L50
DDR
BH20 BE16 F48 M47 PCIE_MRX_GTX_P2
RSVD25 SM_ODT_3 M_ODT3 <15,16> LVDSA_DATA_2 PEG_RX_2
Santa Rosa Platform MOW WW15 BK18 U44 PCIE_MRX_GTX_P3
RSVD26 PEG_RX_3
1
For 4Gb DRAM support, BJ18 BL15 SMRCOMPP T49 PCIE_MRX_GTX_P4
RSVD27 SM_RCOMP SMRCOMPN R405 PEG_RX_4 PCIE_MRX_GTX_P5
BF23 RSVD28 SM_RCOMP# BK14 G44 LVDSB_DATA#_0 PEG_RX_5 T41
change Pin-BJ29 to DDR_A_MA14, BG23 1K/F B47 W45 PCIE_MRX_GTX_P6
change Pin-BE24 to DDR_B_MA14. RSVD29 SM_RCOMP_VOH LVDSB_DATA#_1 PEG_RX_6 PCIE_MRX_GTX_P7
BC23 RSVD30 SM_RCOMP_VOH BK31 B45 LVDSB_DATA#_2 PEG_RX_7 W41
BD24 BL31 SM_RCOMP_VOL AB50 PCIE_MRX_GTX_P8
2
DDR_A_MA14 RSVD31 SM_RCOMP_VOL MCH_CLVREF PEG_RX_8 PCIE_MRX_GTX_P9
<15,16> DDR_A_MA14 BJ29 RSVD32 PEG_RX_9 Y48
DDR_B_MA14 BE24 AR49 V_DDR_MCH_REF E44 AC45 PCIE_MRX_GTX_P10
<15,16> DDR_B_MA14 RSVD33 SM_VREF_0 LVDSB_DATA_0 PEG_RX_10
1
BH39 AW4 A47 AC41 PCIE_MRX_GTX_P11
RSVD34 SM_VREF_1 LVDSB_DATA_1 PEG_RX_11
2
AW20 C522 R407 A45 AH47 PCIE_MRX_GTX_P12
+3.3V_RUN RSVD35 0.1U/10V 392/F LVDSB_DATA_2 PEG_RX_12 PCIE_MRX_GTX_P13
BK20 RSVD36 PEG_RX_13 AG49
C48 AH45 PCIE_MRX_GTX_P14
PCI-EXPRESS
1
R375 1 PM_EXTTS#0 RSVD37 PEG_RX_14 PCIE_MRX_GTX_P15
2 10K D47 B42 AG42 PCIE_MTX_GRX_N[0..15] <18>
2
R383 1 RSVD38 DPLL_REF_CLK PEG_RX_15
2 10K PM_EXTTS#1 B44 RSVD39 DPLL_REF_CLK# C42
C44 H48 E27 N45 PCIE_MTX_GRX_N0
RSVD40 DPLL_REF_SSCLK TVA_DAC PEG_TX#_0 PCIE_MTX_GRX_N1
B A35 H47 G27 U39 B
CLK
RSVD41 DPLL_REF_SSCLK# TVB_DAC PEG_TX#_1 PCIE_MTX_GRX_N2
B37 RSVD42 K27 TVC_DAC PEG_TX#_2 U47
+1.05V_VCCP B36 K44 N51 PCIE_MTX_GRX_N3
RSVD43 PEG_CLK CLK_MCH_3GPLL <17> PEG_TX#_3
TV
R395 56 B34 K45 F27 R50 PCIE_MTX_GRX_N4
RSVD44 PEG_CLK# CLK_MCH_3GPLL# <17> TVA_RTN PEG_TX#_4
1 2 THERMTRIP_MCH# C34 J27 T42 PCIE_MTX_GRX_N5
RSVD45 TVB_RTN PEG_TX#_5 PCIE_MTX_GRX_N6
L27 TVC_RTN PEG_TX#_6 Y43
W46 PCIE_MTX_GRX_N7
PEG_TX#_7 PCIE_MTX_GRX_N8
Layout Note: DMI_RXN_0 AN47 DMI_MRX_ITX_N0 <12> M35 TV_DCONSEL_0 PEG_TX#_8 W38
Location of all MCH_CFG strap AJ38 P33 AD39 PCIE_MTX_GRX_N9
DMI_RXN_1 DMI_MRX_ITX_N1 <12> TV_DCONSEL_1 PEG_TX#_9
AN42 AC46 PCIE_MTX_GRX_N10
resistors needs to be close to DMI_RXN_2 DMI_MRX_ITX_N2 <12> PEG_TX#_10
AN46 AC49 PCIE_MTX_GRX_N11
DMI_RXN_3 DMI_MRX_ITX_N3 <12> PEG_TX#_11
minmize stub. PEG_TX#_12 AC42 PCIE_MTX_GRX_N12
AM47 AH39 PCIE_MTX_GRX_N13
DMI_RXP_0 DMI_MRX_ITX_P0 <12> PEG_TX#_13
P27 AJ39 AE49 PCIE_MTX_GRX_N14
<3,17> CPU_MCH_BSEL0 CFG_0 DMI_RXP_1 DMI_MRX_ITX_P1 <12> PEG_TX#_14
N27 AN41 AH44 PCIE_MTX_GRX_N15
<3,17> CPU_MCH_BSEL1 CFG_1 DMI_RXP_2 DMI_MRX_ITX_P2 <12> PEG_TX#_15 PCIE_MTX_GRX_P[0..15] <18>
<3,17> CPU_MCH_BSEL2 N24 CFG_2 DMI_RXP_3 AN45 DMI_MRX_ITX_P3 <12>
PAD T80 CFG3 C21 H32 M45 PCIE_MTX_GRX_P0
CFG4 CFG_3 CRT_BLUE PEG_TX_0 PCIE_MTX_GRX_P1
C23 AJ46 G32 T38
DMI
PAD T26 CFG_4 DMI_TXN_0 DMI_MTX_IRX_N0 <12> CRT_BLUE# PEG_TX_1

R377 2 1 4.02K/F_NC CFG5 F23 AJ41 K29 T46 PCIE_MTX_GRX_P2
CFG_5 DMI_TXN_1 DMI_MTX_IRX_N1 <12> CRT_GREEN PEG_TX_2
PAD T94 CFG6 N23 AM40 J29 N50 PCIE_MTX_GRX_P3
CFG_6 DMI_TXN_2 DMI_MTX_IRX_N2 <12> CRT_GREEN# PEG_TX_3
PAD T84 CFG7 G23 AM44 F29 R51 PCIE_MTX_GRX_P4
CFG_7 DMI_TXN_3 DMI_MTX_IRX_N3 <12> CRT_RED PEG_TX_4
VGA
PAD T85 CFG8 J20 E29 U43 PCIE_MTX_GRX_P5
CFG_8 CRT_RED# PEG_TX_5
CFG
R366 2 1 4.02K/F_NC CFG9 C20 AJ47 W42 PCIE_MTX_GRX_P6

CFG_9 DMI_TXP_0 DMI_MTX_IRX_P0 <12> PEG_TX_6
PAD T95 CFG10 R24 AJ42 Y47 PCIE_MTX_GRX_P7
CFG_10 DMI_TXP_1 DMI_MTX_IRX_P1 <12> PEG_TX_7
PAD T89 CFG11 L23 AM39 K33 Y39 PCIE_MTX_GRX_P8
CFG_11 DMI_TXP_2 DMI_MTX_IRX_P2 <12> CRT_DDC_CLK PEG_TX_8
PAD T90 CFG12 J23 AM43 G35 AC38 PCIE_MTX_GRX_P9
CFG_12 DMI_TXP_3 DMI_MTX_IRX_P3 <12> CRT_DDC_DATA PEG_TX_9
PAD T79 CFG13 E23 F33 AD47 PCIE_MTX_GRX_P10
CFG14 CFG_13 CRT_HSYNC PEG_TX_10 PCIE_MTX_GRX_P11
PAD T82 E20 CFG_14 C32 CRT_TVO_IREF PEG_TX_11 AC50
PAD T88 CFG15 K23 E33 AD43 PCIE_MTX_GRX_P12
R391 2 CFG16 CFG_15 CRT_VSYNC PEG_TX_12 PCIE_MTX_GRX_P13
C
1 4.02K/F_NC M20 CFG_16 PEG_TX_13 AG39 C
+3.3V_RUN
GRAPHICS VID
PAD T92 CFG17 M24 AE50 PCIE_MTX_GRX_P14

CFG18 CFG_17 PEG_TX_14 PCIE_MTX_GRX_P15
PAD T91 L32 CFG_18 PEG_TX_15 AH43
R381 2 1 4.02K/F_NC CFG19 N33
R382 2 CFG_19
1 4.02K/F_NC CFG20 L35 CFG_20 CRESTLINE_1p0
GFX_VID_0 E35 T83 PAD Low=DMIx2

<13> PM_BMBUSY# G41 PM_BM_BUSY# GFX_VID_1 A39 T19 PAD CFG5 DMI X2 Select High=DMIx4(Default)
<3,11,45> H_DPRSTP# L39 PM_DPRSTP# GFX_VID_2 C38 T20 PAD
PM_EXTTS#0 L36 B39 T22 PAD PCI Express Low= Reveise Lane
<15> PM_EXTTS#0 PM_EXT_TS#_0 GFX_VID_3
PM
PM_EXTTS#1 J36 E36 T21 PAD CFG9 Graphic Lane High=Normal operation
<15> PM_EXTTS#1 PM_EXT_TS#_1 GFX_VR_EN
<13,38> ICH_PWRGD AW49 PWROK
PLTRST#_R AV20 FSB Dynamic Low=Dynamic ODT Disable
THERMTRIP_MCH# N20 RSTIN#
<34> THERMTRIP_MCH# THERMTRIP#
CFG16 ODT High=Dynamic ODT Enable(default).
<13,45> DPRSLPVR 1 2 G36 DPRSLPVR
DMI Lane Low=Normal(default).
R363 0 AM49 CFG19 Reversal High=Lane Reversed
CL_CLK CL_CLK0 <13>
CL_DATA AK50 CL_DATA0 <13>
PAD T37 TP_NC1 BJ51 AT43 Low=Only SDVO or PCIEx1 is
ICH_CL_PWROK <13,28>
ME
TP_NC2 NC_1 CL_PWROK

PAD T38 BK51 NC_2 CL_RST# AN49 ICH_CL_RST0# <13> SDVO/PCIE operational (defaults)
PAD T42 TP_NC3 BK50 AM50 CFG20 Concurrent
TP_NC4 NC_3 CL_VREF MCH_CLVREF High=SDVO and PCIEx1 are operating
PAD T44 BL50 NC_4
T43 TP_NC5 BL49
Operation simultaneously via PEG port
PAD NC_5
PAD T41 TP_NC6 BL3
TP_NC7 NC_6
PAD T40 BL2 NC_7 Low=No SDVO Device Present
NC
PAD T36 TP_NC8 BK1 (default)

TP_NC9 NC_8
PAD T35 BJ1 NC_9 SDVO_CTRL_CLK H35 SDVO_CRTL_DATA SDVO Present. High=SDVO Device Present
PAD T30 TP_NC10 E1 K36
NC_10
MISC
TP_NC11 SDVO_CTRL_DATA
PAD T25 A5 NC_11 CLK_REQ# G39 CLK_3GPLLREQ# <17>
D PAD T29 TP_NC12 C51 G40 D
NC_12 ICH_SYNC# MCH_ICH_SYNC# <13>
PAD T27 TP_NC13 B50
TP_NC14 NC_13
PAD T24 A50 NC_14
PAD T23 TP_NC15 A49 A37
TP_NC16 NC_15 TEST_1
BK2 R32
PAD T39 NC_16 TEST_2 DELL CONFIDENTIAL/PROPRIETARY
2
CRESTLINE_1p0
R396 R356 R160 0_0402
20K 0 100 1 2 Title
R415 PLTRST# <12,28> Crestline (VGA,DMI)
R161 0_0402_NC
1
PLTRST#_R 2 1 1 2 Size Document Number Rev

SB_NB_PCIE_RST# <12> M-08 0.1

1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
<15> DDR_A_D[0..63] <15> DDR_B_D[0..63]

U19D U19E
DDR_A_D0 AR43 BB19 DDR_A_BS0 DDR_B_D0 AP49 AY17 DDR_B_BS0
SA_DQ_0 SA_BS_0 DDR_A_BS0 <15,16> SB_DQ_0 SB_BS_0 DDR_B_BS0 <15,16>
DDR_A_D1AW44 BK19 DDR_A_BS1 DDR_B_D1 AR51 BG18 DDR_B_BS1
A SA_DQ_1 SA_BS_1 DDR_A_BS1 <15,16> SB_DQ_1 SB_BS_1 DDR_B_BS1 <15,16> A
DDR_A_D2 BA45 BF29 DDR_A_BS2 DDR_B_D2 AW50 BG36 DDR_B_BS2
SA_DQ_2 SA_BS_2 DDR_A_BS2 <15,16> SB_DQ_2 SB_BS_2 DDR_B_BS2 <15,16>
DDR_A_D3 AY46 DDR_B_D3 AW51
DDR_A_D4 AR41 SA_DQ_3 DDR_A_CAS# DDR_B_D4 SB_DQ_3 DDR_B_CAS#
SA_DQ_4 SA_CAS# BL17 DDR_A_CAS# <15,16> AN51 SB_DQ_4 SB_CAS# BE17 DDR_B_CAS# <15,16>
DDR_A_D5 AR45 DDR_B_D5 AN50
SA_DQ_5 DDR_A_DM[0..7] <15> SB_DQ_5 DDR_B_DM[0..7] <15>
DDR_A_D6 AT42 AT45 DDR_A_DM0 DDR_B_D6 AV50 AR50 DDR_B_DM0
DDR_A_D7AW47 SA_DQ_6 SA_DM_0 DDR_A_DM1 DDR_B_D7 SB_DQ_6 SB_DM_0 DDR_B_DM1
SA_DQ_7 SA_DM_1 BD44 AV49 SB_DQ_7 SB_DM_1 BD49
DDR_A_D8 BB45 BD42 DDR_A_DM2 DDR_B_D8 BA50 BK45 DDR_B_DM2
DDR_A_D9 BF48 SA_DQ_8 SA_DM_2 DDR_A_DM3 DDR_B_D9 SB_DQ_8 SB_DM_2 DDR_B_DM3
SA_DQ_9 SA_DM_3 AW38 BB50 SB_DQ_9 SB_DM_3 BL39
DDR_A_D10BG47 AW13 DDR_A_DM4 DDR_B_D10 BA49 BH12 DDR_B_DM4
DDR_A_D11BJ45 SA_DQ_10 SA_DM_4 DDR_A_DM5 DDR_B_D11 SB_DQ_10 SB_DM_4 DDR_B_DM5
SA_DQ_11 SA_DM_5 BG8 BE50 SB_DQ_11 SB_DM_5 BJ7
DDR_A_D12BB47 AY5 DDR_A_DM6 DDR_B_D12 BA51 BF3 DDR_B_DM6
DDR_A_D13BG50 SA_DQ_12 SA_DM_6 DDR_A_DM7 DDR_B_D13 SB_DQ_12 SB_DM_6 DDR_B_DM7
SA_DQ_13 SA_DM_7 AN6 AY49 SB_DQ_13 SB_DM_7 AW2
DDR_A_D14BH49 DDR_B_D14 BF50
SA_DQ_14 DDR_A_DQS[0..7] <15> SB_DQ_14 DDR_B_DQS[0..7] <15>
DDR_A_D15BE45 AT46 DDR_A_DQS0 DDR_B_D15 BF49 AT50 DDR_B_DQS0
SA_DQ_15 SA_DQS_0 SB_DQ_15 SB_DQS_0
A
DDR_A_D16
AW43 BE48 DDR_A_DQS1 DDR_B_D16 BJ50 BD50 DDR_B_DQS1
SA_DQ_16 SA_DQS_1 SB_DQ_16 SB_DQS_1
B
DDR_A_D17BE44 BB43 DDR_A_DQS2 DDR_B_D17 BJ44 BK46 DDR_B_DQS2
DDR_A_D18BG42 SA_DQ_17 SA_DQS_2 DDR_A_DQS3 DDR_B_D18 SB_DQ_17 SB_DQS_2 DDR_B_DQS3
SA_DQ_18 SA_DQS_3 BC37 BJ43 SB_DQ_18 SB_DQS_3 BK39
DDR_A_D19BE40 BB16 DDR_A_DQS4 DDR_B_D19 BL43 BJ12 DDR_B_DQS4
DDR_A_D20BF44 SA_DQ_19 SA_DQS_4 DDR_A_DQS5 DDR_B_D20 SB_DQ_19 SB_DQS_4 DDR_B_DQS5
BH6 BK47 BL7
MEMORY
DDR_A_D21BH45 SA_DQ_20 SA_DQS_5 DDR_A_DQS6 DDR_B_D21 SB_DQ_20 SB_DQS_5 DDR_B_DQS6
BB2 BK49 BE2
MEMORY
DDR_A_D22BG40 SA_DQ_21 SA_DQS_6 DDR_A_DQS7 DDR_B_D22 SB_DQ_21 SB_DQS_6 DDR_B_DQS7
SA_DQ_22 SA_DQS_7 AP3 DDR_A_DQS#[0..7] <15> BK43 SB_DQ_22 SB_DQS_7 AV2 DDR_B_DQS#[0..7] <15>
DDR_A_D23BF40 AT47 DDR_A_DQS#0 DDR_B_D23 BK42 AU50 DDR_B_DQS#0
DDR_A_D24AR40 SA_DQ_23 SA_DQS#_0 DDR_A_DQS#1 DDR_B_D24 SB_DQ_23 SB_DQS#_0 DDR_B_DQS#1
SA_DQ_24 SA_DQS#_1 BD47 BJ41 SB_DQ_24 SB_DQS#_1 BC50
DDR_A_D25
AW40 BC41 DDR_A_DQS#2 DDR_B_D25 BL41 BL45 DDR_B_DQS#2
DDR_A_D26AT39 SA_DQ_25 SA_DQS#_2 DDR_A_DQS#3 DDR_B_D26 SB_DQ_25 SB_DQS#_2 DDR_B_DQS#3
SA_DQ_26 SA_DQS#_3 BA37 BJ37 SB_DQ_26 SB_DQS#_3 BK38
DDR_A_D27
AW36 BA16 DDR_A_DQS#4 DDR_B_D27 BJ36 BK12 DDR_B_DQS#4
DDR_A_D28 SA_DQ_27 SA_DQS#_4 DDR_A_DQS#5 DDR_B_D28 SB_DQ_27 SB_DQS#_4 DDR_B_DQS#5
AW41 SA_DQ_28 SA_DQS#_5 BH7 BK41 SB_DQ_28 SB_DQS#_5 BK7
DDR_A_D29AY41 BC1 DDR_A_DQS#6 DDR_B_D29 BJ40 BF2 DDR_B_DQS#6
DDR_A_D30AV38 SA_DQ_29 SA_DQS#_6 DDR_A_DQS#7 DDR_B_D30 SB_DQ_29 SB_DQS#_6 DDR_B_DQS#7
SA_DQ_30 SA_DQS#_7 AP2 BL35 SB_DQ_30 SB_DQS#_7 AV3
B DDR_A_D31AT38 DDR_B_D31 BK37 B
SA_DQ_31 DDR_A_MA[0..13] <15,16> SB_DQ_31 DDR_B_MA[0..13] <15,16>
DDR_A_D32AV13 BJ19 DDR_A_MA0 DDR_B_D32 BK13 BC18 DDR_B_MA0
DDR_A_D33AT13 SA_DQ_32 SA_MA_0 DDR_A_MA1 DDR_B_D33 SB_DQ_32 SB_MA_0 DDR_B_MA1
BD20 BE11 BG28
SYSTEM
DDR_A_D34 SA_DQ_33 SA_MA_1 DDR_A_MA2 DDR_B_D34 SB_DQ_33 SB_MA_1 DDR_B_MA2

AW11 BK27 BK11 BG25
SYSTEM
DDR_A_D35AV11 SA_DQ_34 SA_MA_2 DDR_A_MA3 DDR_B_D35 SB_DQ_34 SB_MA_2 DDR_B_MA3
SA_DQ_35 SA_MA_3 BH28 BC11 SB_DQ_35 SB_MA_3 AW17
DDR_A_D36AU15 BL24 DDR_A_MA4 DDR_B_D36 BC13 BF25 DDR_B_MA4
DDR_A_D37AT11 SA_DQ_36 SA_MA_4 DDR_A_MA5 DDR_B_D37 SB_DQ_36 SB_MA_4 DDR_B_MA5
SA_DQ_37 SA_MA_5 BK28 BE12 SB_DQ_37 SB_MA_5 BE25
DDR_A_D38BA13 BJ27 DDR_A_MA6 DDR_B_D38 BC12 BA29 DDR_B_MA6
DDR_A_D39BA11 SA_DQ_38 SA_MA_6 DDR_A_MA7 DDR_B_D39 SB_DQ_38 SB_MA_6 DDR_B_MA7
SA_DQ_39 SA_MA_7 BJ25 BG12 SB_DQ_39 SB_MA_7 BC28
DDR_A_D40BE10 BL28 DDR_A_MA8 DDR_B_D40 BJ10 AY28 DDR_B_MA8
DDR_A_D41BD10 SA_DQ_40 SA_MA_8 DDR_A_MA9 DDR_B_D41 SB_DQ_40 SB_MA_8 DDR_B_MA9
SA_DQ_41 SA_MA_9 BA28 BL9 SB_DQ_41 SB_MA_9 BD37
DDR_A_D42 BD8 BC19 DDR_A_MA10 DDR_B_D42 BK5 BG17 DDR_B_MA10
DDR_A_D43 AY9 SA_DQ_42 SA_MA_10 DDR_A_MA11 DDR_B_D43 SB_DQ_42 SB_MA_10 DDR_B_MA11
SA_DQ_43 SA_MA_11 BE28 BL5 SB_DQ_43 SB_MA_11 BE37
DDR_A_D44BG10 BG30 DDR_A_MA12 DDR_B_D44 BK9 BA39 DDR_B_MA12
DDR_A_D45AW9 SA_DQ_44 SA_MA_12 DDR_A_MA13 DDR_B_D45 SB_DQ_44 SB_MA_12 DDR_B_MA13
SA_DQ_45 SA_MA_13 BJ16 BK10 SB_DQ_45 SB_MA_13 BG13
DDR_A_D46 BD7 DDR_B_D46 BJ8
DDR
DDR_A_D47 BB9 SA_DQ_46 DDR_B_D47 SB_DQ_46 DDR_B_RAS#

BJ6 AV16
DDR
SA_DQ_47 SB_DQ_47 SB_RAS# DDR_B_RAS# <15,16>
DDR_A_D48 BB5 BE18 DDR_A_RAS# DDR_B_D48 BF4 AY18 T103 PAD
SA_DQ_48 SA_RAS# DDR_A_RAS# <15,16> SB_DQ_48 SB_RCVEN#
DDR_A_D49 AY7 AY20 T102 PAD DDR_B_D49 BH5
DDR_A_D50 AT5 SA_DQ_49 SA_RCVEN# DDR_B_D50 SB_DQ_49 DDR_B_WE#
SA_DQ_50 BG1 SB_DQ_50 SB_WE# BC17 DDR_B_WE# <15,16>
DDR_A_D51 AT7 BA19 DDR_A_WE# DDR_B_D51 BC2
SA_DQ_51 SA_WE# DDR_A_WE# <15,16> SB_DQ_51
DDR_A_D52 AY6 DDR_B_D52 BK3
DDR_A_D53 BB7 SA_DQ_52 DDR_B_D53 SB_DQ_52
SA_DQ_53 BE4 SB_DQ_53
DDR_A_D54 AR5 DDR_B_D54 BD3
DDR_A_D55 AR8 SA_DQ_54 DDR_B_D55 SB_DQ_54
SA_DQ_55 BJ2 SB_DQ_55
DDR_A_D56 AR9 DDR_B_D56 BA3
DDR_A_D57 AN3 SA_DQ_56 DDR_B_D57 SB_DQ_56
SA_DQ_57 BB3 SB_DQ_57
DDR_A_D58 AM8 DDR_B_D58 AR1
DDR_A_D59AN10 SA_DQ_58 DDR_B_D59 SB_DQ_58
SA_DQ_59 AT3 SB_DQ_59
DDR_A_D60 AT9 DDR_B_D60 AY2
C
DDR_A_D61 AN9 SA_DQ_60 DDR_B_D61 SB_DQ_60 C
SA_DQ_61 AY3 SB_DQ_61
DDR_A_D62 AM9 DDR_B_D62 AU2
DDR_A_D63AN11 SA_DQ_62 DDR_B_D63 SB_DQ_62
SA_DQ_63 AT2 SB_DQ_63
CRESTLINE_1p0 CRESTLINE_1p0
D D
Title
Crestline (DDR2)

M-08 0.1

1 2 3 4 5 6 7 8
5 4 3 2 1
+3.3V_RUN
U19G U19F
R341 10 D29
+VCC_GMCH AT35 1 2 +VCC_GMCH_L 1 2 AB33
VCC_1 VCC_NCTF_1
AT34 VCC_2 VCC_AXG_NCTF_1 T17 AB36 VCC_NCTF_2
AH28 T18 SDMK0340L-7-F AB37
VCC_3 VCC_AXG_NCTF_2 VCC_NCTF_3
AC32 VCC_5 VCC_AXG_NCTF_3 T19 AC33 VCC_NCTF_4 VSS_NCTF_1 T27
AC31 VCC_4 VCC_AXG_NCTF_4 T21 AC35 VCC_NCTF_5 VSS_NCTF_2 T37
AK32 T22 AC36 U24
VCC CORE
VCC_6 VCC_AXG_NCTF_5 VCC_NCTF_6 VSS_NCTF_3
AJ31 VCC_7 VCC_AXG_NCTF_6 T23 AD35 VCC_NCTF_7 VSS_NCTF_4 U28
AJ28 T25 +1.05V_VCCP AD36 V31
AH32 VCC_9 VCC_AXG_NCTF_8 U15 AF33 VCC_NCTF_9 VSS_NCTF_6 V35
D
AH31 VCC_10 VCC_AXG_NCTF_9 U16 AF36 VCC_NCTF_10 VSS_NCTF_7 AA19 D
AH29 U17 +VCC_GMCH AH33 AB17
AF32 VCC_12 VCC_AXG_NCTF_11 U19 AH35 VCC_NCTF_12 VSS_NCTF_9 AB35
VSS NCTF
VCC_AXG_NCTF_12 U20 AH36 VCC_NCTF_13 VSS_NCTF_10 AD19
1
U21 + AH37 AD37
VCC_AXG_NCTF_13 C202 C192 C512 C513 C517 VCC_NCTF_14 VSS_NCTF_11
VCC_AXG_NCTF_14 U23 AJ33 VCC_NCTF_15 VSS_NCTF_12 AF17
R30 U26 Layout Note: 220U/2.5V 22U/4V 0.22U/10V 0.22U/10V 0.1U/10V AJ35 AF35
2
VCC_AXG_NCTF_16 V16 370 mils from edge. AK33 VCC_NCTF_17 VSS_NCTF_14 AK17
VCC_AXG_NCTF_17 V17 AK35 VCC_NCTF_18 VSS_NCTF_15 AM17
VCC_AXG_NCTF_18 V19 Layout Note: AK36 VCC_NCTF_19 VSS_NCTF_16 AM24
VCC_AXG_NCTF_19 V20 Inside GMCH cavity. AK37 VCC_NCTF_20 VSS_NCTF_17 AP26
VCC_AXG_NCTF_20 V21 AD33 VCC_NCTF_21 VSS_NCTF_18 AP28
VCC_AXG_NCTF_21 V23 AJ36 VCC_NCTF_22 VSS_NCTF_19 AR15
VCC_AXG_NCTF_22 V24 AM35 VCC_NCTF_23 VSS_NCTF_20 AR19
VCC NCTF
Y15 AL33 AR28
+VCC_SM
POWER VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
Y16
Y17
AL35
AA33
VCC_NCTF_24
VCC_NCTF_25
VCC_NCTF_26
VSS_NCTF_21
AU32 VCC_SM_1 VCC_AXG_NCTF_26 Y19 AA35 VCC_NCTF_27

AU33 VCC_SM_2 VCC_AXG_NCTF_27 Y20 AA36 VCC_NCTF_28
AU35 VCC_SM_3 VCC_AXG_NCTF_28 Y21 AP35 VCC_NCTF_29
AV33 VCC_SM_4 VCC_AXG_NCTF_29 Y23 AP36 VCC_NCTF_30
AW33 VCC_SM_5 VCC_AXG_NCTF_30 Y24 AR35 VCC_NCTF_31
AW35 VCC_SM_6 VCC_AXG_NCTF_31 Y26 AR36 VCC_NCTF_32
AY35 VCC_SM_7 VCC_AXG_NCTF_32 Y28 Y32 VCC_NCTF_33
BA32 Y29 Y33
BA33
BA35
VCC_SM_8
VCC_SM_9
VCC_SM_10
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
AA16
AA17
Y35
Y36
VCC_NCTF_34
VCC_NCTF_35
VCC_NCTF_36
POWER
BB33 VCC_SM_11 VCC_AXG_NCTF_36 AB16 Y37 VCC_NCTF_37 VSS_SCB1 A3
BC32 AB19 T30 B2
VSS SCB
VCC_SM_12 VCC_AXG_NCTF_37 VCC_NCTF_38 VSS_SCB2
BC33 VCC_SM_13 VCC_AXG_NCTF_38 AC16 T34 VCC_NCTF_39 VSS_SCB3 C1
C BC35 VCC_SM_14 VCC_AXG_NCTF_39 AC17 T35 VCC_NCTF_40 VSS_SCB4 BL1 C
BD32 VCC_SM_15 VCC_AXG_NCTF_40 AC19 U29 VCC_NCTF_41 VSS_SCB5 BL51
BD35 VCC_SM_16 VCC_AXG_NCTF_41 AD15 U31 VCC_NCTF_42 VSS_SCB6 A51
BE32 VCC_SM_17 VCC_AXG_NCTF_42 AD16 U32 VCC_NCTF_43
BE33 VCC_SM_18 VCC_AXG_NCTF_43 AD17 U33 VCC_NCTF_44
BE35 VCC_SM_19 VCC_AXG_NCTF_44 AF16 U35 VCC_NCTF_45
VCC GFX NCTF
BF33 AF19 U36

VCC SM
VCC_SM_20 VCC_AXG_NCTF_45 VCC_NCTF_46

BF34 VCC_SM_21 VCC_AXG_NCTF_46 AH15 V32 VCC_NCTF_47
BG32 VCC_SM_22 VCC_AXG_NCTF_47 AH16 V33 VCC_NCTF_48
BH32 VCC_SM_25 VCC_AXG_NCTF_50 AJ16
BH34 VCC_SM_26 VCC_AXG_NCTF_51 AJ17 VCC_AXM_1 AT33 +VCC_AXM
BH35 AJ19 AT31
VCC AXM
VCC_SM_27 VCC_AXG_NCTF_52 VCC_AXM_2
BJ32 VCC_SM_28 VCC_AXG_NCTF_53 AK16 VCC_AXM_3 AK29
BJ33 VCC_SM_29 VCC_AXG_NCTF_54 AK19 VCC_AXM_4 AK24
BJ34 VCC_SM_30 VCC_AXG_NCTF_55 AL16 Layout Note: VCC_AXM_5 AK23
BK32 AL17 +1.05V_VCCP AL24 AJ26
VCC_SM_31 VCC_AXG_NCTF_56 Inside GMCH cavity. VCC_AXM_NCTF_1 VCC_AXM_6
BK33 VCC_SM_32 VCC_AXG_NCTF_57 AL19 AL26 VCC_AXM_NCTF_2 VCC_AXM_7 AJ23
BK34 AL20 +VCC_AXM AL28
VCC_SM_33 VCC_AXG_NCTF_58 VCC_AXM_NCTF_3
BK35 VCC_SM_34 VCC_AXG_NCTF_59 AL21 AM26 VCC_AXM_NCTF_4
BL33 VCC_SM_35 VCC_AXG_NCTF_60 AL23 AM28 VCC_AXM_NCTF_5
VCC AXM NCTF

AU30 VCC_SM_36 VCC_AXG_NCTF_61 AM15 AM29 VCC_AXM_NCTF_6
AM16 C523 C521 C526 AM31
VCC_AXG_NCTF_62 0.1U/10V 0.1U/10V 0.1U/10V VCC_AXM_NCTF_7
AM19 AM32
2
VCC_AXG_NCTF_63 VCC_AXM_NCTF_8
VCC_AXG_NCTF_64 AM20 AM33 VCC_AXM_NCTF_9
R20
VCC_AXG_NCTF_65 AM21
AM23
Non-iAMT AP29
AP31
VCC_AXM_NCTF_10
VCC_AXG_1 VCC_AXG_NCTF_66 VCC_AXM_NCTF_11
T14 VCC_AXG_2 VCC_AXG_NCTF_67 AP15 AP32 VCC_AXM_NCTF_12
B
W13 VCC_AXG_3 VCC_AXG_NCTF_68 AP16 AP33 VCC_AXM_NCTF_13 B
W14 VCC_AXG_4 VCC_AXG_NCTF_69 AP17 AL29 VCC_AXM_NCTF_14
Y12 VCC_AXG_5 VCC_AXG_NCTF_70 AP19 AL31 VCC_AXM_NCTF_15
1
AA20 VCC_AXG_6 VCC_AXG_NCTF_71 AP20 AL32 VCC_AXM_NCTF_16
AA23 AP21 C239 C527 C529 AR31
VCC_AXG_7 VCC_AXG_NCTF_72 22U/4V 0.22U/10V 0.22U/10V VCC_AXM_NCTF_17
AA26 AP23 AR32
2
VCC_AXG_8 VCC_AXG_NCTF_73 VCC_AXM_NCTF_18
AA28 VCC_AXG_9 VCC_AXG_NCTF_74 AP24 AR33 VCC_AXM_NCTF_19
AB21 VCC_AXG_10 VCC_AXG_NCTF_75 AR20
AB24 VCC_AXG_11 VCC_AXG_NCTF_76 AR21
AB29 VCC_AXG_12 VCC_AXG_NCTF_77 AR23 Layout Note:
AC20 VCC_AXG_13 VCC_AXG_NCTF_78 AR24 Place close to GMCH edge.
AC21 AR26 CRESTLINE_1p0
VCC_AXG_14 VCC_AXG_NCTF_79
VCC GFX
AC23 VCC_AXG_15 VCC_AXG_NCTF_80 V26

AC28 Y31 +1.8V_SUS +VCC_SM
VCC_AXG_18 VCC_AXG_NCTF_83
AC29 VCC_AXG_19
AD20 VCC_AXG_20
AD23 VCC_AXG_21
1
AD24 AW45 VCCSM_LF1
VCC SM LF
VCC_AXG_22 VCC_SM_LF1
1
AD28 BC39 VCCSM_LF2 +
VCC_AXG_23 VCC_SM_LF2 VCCSM_LF3 C530 C572 C253 C254
AF21 VCC_AXG_24 VCC_SM_LF3 BE39
AF26 BD17 VCCSM_LF4 0.1U/10V 330U/6.3V 22U/4V 22U/4V
2
VCC_AXG_25 VCC_SM_LF4 VCCSM_LF5
AA31 VCC_AXG_26 VCC_SM_LF5 BD4
AH20 AW8 VCCSM_LF6
VCC_AXG_27 VCC_SM_LF6 VCCSM_LF7
AH21 VCC_AXG_28 VCC_SM_LF7 AT6 Layout Note:
AH23 VCC_AXG_29 Place C901 where LVDS
1
AH24 VCC_AXG_30 and DDR2 taps. Layout Note:

AH26 C531 C537 C549 C547 C557 C536 C534 Place on the edge.
VCC_AXG_31 0.1U/10V 0.1U/10V 0.22U/10V 0.22U/10V 0.47U/10V 1U/10V 1U/10V
AD31
2
VCC_AXG_32
A AJ20 VCC_AXG_33
A
AN14 VCC_AXG_34
CRESTLINE_1p0 Title
Crestline (VCC,NCTF)

M-08 0.1

5 4 3 2 1
5 4 3 2 1
U19H
+1.05V_VCCP
J32 U13
VCC_HV
VCCSYNC VTT_1
2
VTT_2 U12
A33 VCCA_CRT_DAC_1 VTT_3 U11
1
B33 U9 D30
VCCA_CRT_DAC_2 VTT_4 C497 C493 CH751H-40HPT_NC
U8
CRT
VTT_5 2.2U/6.3V 4.7U/10V
U7
1
VTT_6 +VCC_HV_L
A30 VCCA_DAC_BG VTT_7 U5
VTT_8 U3
1
B32 VSSA_DAC_BG VTT_9 U2
U1 +1.05V_VCCP
D VTT_10 R342 D
VTT_11 T13 Place on the edge.
B49 T11 10_NC
VCCA_DPLLA VTT_12
VTT
T10
2
VTT_13
H49 VCCA_DPLLB VTT_14 T9
Non-iAMT 45mA MAx. T7
PLL
VTT_15
1
+VCCA_HPLL AL2 T6
VCCA_HPLL VTT_16 C496 C499 + C235
+1.25V_RUN
FB_120ohm+-25%_100mHz VTT_17 T5
+VCCA_MPLL AM2 T3 0.47U/6.3V 4.7U/10V 220U/4V +3.3V_RUN
_200mA_0.2ohm DC
2
VCCA_MPLL VTT_18
T2 Non-iAMT
2
L36 VTT_19
R3
A LVDS
+VCCA_HPLL VTT_20 +1.25V_RUN
2 1 A41 VCCA_LVDS VTT_21 R2
BLM11A121S R1 +1.25V_RUN
VTT_22
B41 VSSA_LVDS
Place on the edge. PJP17
1
+3.3V_RUN
C241 C519 AT23 +VCC_AXD_L 1 2+VCC_AXD_R 2 1
22U/10V 0.1U/10V VCC_AXD_1 L39 0
AU28
2
VCC_AXD_2
K50 VCCA_PEG_BG VCC_AXD_3 AU24 Reserved L81 pad for
1
AT29
A PEG
VCC_AXD_4 inductor.
AXD
L37 K49 AT25 C533 C251
BLM11A121S VSSA_PEG_BG VCC_AXD_5 1U/10V 22U/10V +VCC_AXF
AT30
2
VCC_AXD_6
1
2 1 +VCCA_MPLL C466 Place caps close
R411 0.1U/10V +VCCA_PEG_PLL U51 AR29 to VCC_AXD.
VCCA_PEG_PLL VCC_AXD_NCTF
1
0.5/F/0603
2
1 2 C452 C453
1
AW18 B23 +VCC_AXF 1U/10V 10U/6.3V
2
+VCCA_MPLL_L C528 VCCA_SM_1 VCC_AXF_1
AV19 B21
AXF
VCCA_SM_2
POWER VCC_AXF_2
1
0.1U/10V AU19 A21

2
C242 VCCA_SM_3 VCC_AXF_3

AU18 VCCA_SM_4
22U/10V AU17 AJ50 +1.25V_RUN
PJP16
2
VCCA_SM_5 VCC_DMI
C Place caps close C
A SM
1
+1.25V_RUN 1 2 +VCCA_SM AT22 to VCC_AXF
VCCA_SM_7 +VCC_SM_CK C518
AT21 BK24
SM CK
VCCA_SM_8 VCC_SM_CK_1
1
AT19 BK23 0.1U/10V
2
VCCA_SM_9 VCC_SM_CK_2
2
1
+ C246 C525 C532 C541 C524 AT18 BJ24
100U/6.3V 4.7U/6.3V 22U/4V 22U/4V 1U/10V VCCA_SM_10 VCC_SM_CK_3
AT17 VCCA_SM_11 VCC_SM_CK_4 BJ23
Non-iAMT AR17
2
2
VCCA_SM_NCTF_1
AR16 VCCA_SM_NCTF_2
A43
A CK
PJP18 VCC_TX_LVDS
BC29 VCCA_SM_CK_1
1 2 +VCCA_SM_CK BB29 +3.3V_RUN
+1.25V_RUN VCCA_SM_CK_2
VCC_HV_1 C40
C25 B40
HV
VCCA_TVA_DAC_1 VCC_HV_2
1
C548 C538 C539 1 C555 B25 VCCA_TVA_DAC_2
1
22U/4V 1U/10V 1U/10V 0.1U/10V C27 VCCA_TVB_DAC_1 C463
B27 AD51
TV
2
VCCA_TVB_DAC_2 VCC_PEG_1 0.1U/10V +VCC_PEG +1.05V_VCCP

B28 W50
2
VCCA_TVC_DAC_1 VCC_PEG_2
A28 VCCA_TVC_DAC_2 VCC_PEG_3 W51
PEG
V49 L25
D TV/CRT
+1.5V_RUN VCC_PEG_4
VCC_PEG_5 V50 2 1
1
M32 91nH/1.5A
VCCD_CRT
1
C450 C483 C451 L29 91uH+-20%_1.5A
VCCD_TVDAC
1
10U/6.3V 0.1U/10V 0.022U/16V AH50 +VCC_RXR_DMI +
DMI
2
VCC_RXR_DMI_1 C216 C514

N28 VCCD_QDAC VCC_RXR_DMI_2 AH51
220U/4V 10U/6.3V
2
AN2 VCCD_HPLL
+1.25V_RUN A7 +VTTLF1 +1.05V_VCCP
VTTLF
+1.25V_RUN VTTLF1
L35 +VCCA_PEG_PLL U48 F2 +VTTLF2
+VCCA_PEG_PLL VCCD_PEG_PLL VTTLF2 +VTTLF3 L27
1 2 Non-iAMT AH1
LVDS
VTTLF3
1
B B
BLM21PG221SN1D J41 2 1
VCCD_LVDS_1
1
C457 C500 H42 91nH/1.5A

VCCD_LVDS_2
1
0.1U/10V 0.1U/10V 91uH+-20%_1.5A
2
1
FB_220ohm+-25%_100MHz R394 +
1/F/0603 C233 C515
_2A_0.1ohm DC
1
CRESTLINE_1p0 220U/4V 10U/6.3V

1 2
2
C509
0.1U/10V
2
C494
10U/6.3V +VTTLF1
2
+VTTLF2
+VTTLF3 1
1
L38 +1.8V_SUS
C516 C473 C454 1uH/300mA
0.47U/10V 0.47U/10V 0.47U/10V +VCC_SM_CK 2 1
2
1
1uH+-20%_300mA
R423
1
1/F/0603
C252 C550
1 2
22U/10V 0.1U/10V +VCC_SM_CK_L
2
C552
10U/6.3V
2
A A
Title
Crestline (POWER)

M-08 0.1

5 4 3 2 1
5 4 3 2 1
U19I U19J
C46 VSS_199 VSS_287 W11
A13 VSS_1 VSS_100 AW24 C50 VSS_200 VSS_288 W39
A15 VSS_2 VSS_101 AW29 C7 VSS_201 VSS_289 W43
A17 VSS_3 VSS_102 AW32 D13 VSS_202 VSS_290 W47
A24 VSS_4 VSS_103 AW5 D24 VSS_203 VSS_291 W5
AA21 VSS_5 VSS_104 AW7 D3 VSS_204 VSS_292 W7
AA24 VSS_6 VSS_105 AY10 D32 VSS_205 VSS_293 Y13
AA29 VSS_7 VSS_106 AY24 D39 VSS_206 VSS_294 Y2
D
AB20 VSS_8 VSS_107 AY37 D45 VSS_207 VSS_295 Y41 D
AB23 VSS_9 VSS_108 AY42 D49 VSS_208 VSS_296 Y45
AB26 VSS_10 VSS_109 AY43 E10 VSS_209 VSS_297 Y49
AC10 VSS_13 VSS_112 AY50 E28 VSS_212 VSS_300 Y11
AC13 VSS_14 VSS_113 B10 E32 VSS_213 VSS_301 P29
AC3 VSS_15 VSS_114 B20 E47 VSS_214 VSS_302 T29
AC39 VSS_16 VSS_115 B24 F19 VSS_215 VSS_303 T31
AC43 VSS_17 VSS_116 B29 F36 VSS_216 VSS_304 T33
AC47 VSS_18 VSS_117 B30 F4 VSS_217 VSS_305 R28
AD1 VSS_19 VSS_118 B35 F40 VSS_218
AD21 VSS_20 VSS_119 B38 F50 VSS_219
AD26 VSS_21 VSS_120 B43 G1 VSS_220
AD29 VSS_22 VSS_121 B46 G13 VSS_221 VSS_306 AA32
AD3 VSS_23 VSS_122 B5 G16 VSS_222 VSS_307 AB32
AD41 VSS_24 VSS_123 B8 G19 VSS_223 VSS_308 AD32
AD45 VSS_25 VSS_124 BA1 G24 VSS_224 VSS_309 AF28
AD49 VSS_26 VSS_125 BA17 G28 VSS_225 VSS_310 AF29
AD5 VSS_27 VSS_126 BA18 G29 VSS_226 VSS_311 AT27
AD50 VSS_28 VSS_127 BA2 G33 VSS_227 VSS_312 AV25
AD8 VSS_29 VSS_128 BA24 G42 VSS_228 VSS_313 H50
AE10 VSS_30 VSS_129 BB12 G45 VSS_229
AE14 VSS_31 VSS_130 BB25 G48 VSS_230
AE6 VSS_32 VSS_131 BB40 G8 VSS_231
AF20 BB44 H24
AF23
AF24
VSS_33
VSS_34
VSS_35
VSS VSS_132
VSS_133
VSS_134
BB49
BB8
H28
H4
VSS_232
VSS_233
VSS_234
AF31 VSS_36 VSS_135 BC16 H45 VSS_235
AG2 VSS_37 VSS_136 BC24 J11 VSS_236
C AG38 VSS_38 VSS_137 BC25 J16 VSS_237
C
AG43 VSS_39 VSS_138 BC36 J2 VSS_238
AG47 VSS_40 VSS_139 BC40 J24 VSS_239
AG50 VSS_41 VSS_140 BC51 J28 VSS_240
AH3 BD13 J33
AH40
AH41
VSS_42
VSS_43
VSS_44
VSS_141
VSS_142
VSS_143
BD2
BD28
J35
J39
VSS_241
VSS_242
VSS_243
VSS
AH7 VSS_45 VSS_144 BD45
AH9 VSS_46 VSS_145 BD48 K12 VSS_245
AJ11 VSS_47 VSS_146 BD5 K47 VSS_246
AJ13 VSS_48 VSS_147 BE1 K8 VSS_247
AJ21 VSS_49 VSS_148 BE19 L1 VSS_248
AJ24 VSS_50 VSS_149 BE23 L17 VSS_249
AJ29 VSS_51 VSS_150 BE30 L20 VSS_250
AJ32 VSS_52 VSS_151 BE42 L24 VSS_251
AJ43 VSS_53 VSS_152 BE51 L28 VSS_252
AJ45 VSS_54 VSS_153 BE8 L3 VSS_253
AJ49 VSS_55 VSS_154 BF12 L33 VSS_254
AK20 VSS_56 VSS_155 BF16 L49 VSS_255
AK21 VSS_57 VSS_156 BF36 M28 VSS_256
AK26 VSS_58 VSS_157 BG19 M42 VSS_257
AK28 VSS_59 VSS_158 BG2 M46 VSS_258
AK31 VSS_60 VSS_159 BG24 M49 VSS_259
AK51 VSS_61 VSS_160 BG29 M5 VSS_260
AL1 VSS_62 VSS_161 BG39 M50 VSS_261
AM11 VSS_63 VSS_162 BG48 M9 VSS_262
AM13 VSS_64 VSS_163 BG5 N11 VSS_263
AM3 VSS_65 VSS_164 BG51 N14 VSS_264
AM4 VSS_66 VSS_165 BH17 N17 VSS_265
B
AM41 VSS_67 VSS_166 BH30 N29 VSS_266 B
AM45 VSS_68 VSS_167 BH44 N32 VSS_267
AN1 VSS_69 VSS_168 BH46 N36 VSS_268
AN38 VSS_70 VSS_169 BH8 N39 VSS_269
AN39 VSS_71 VSS_170 BJ11 N44 VSS_270
AN43 VSS_72 VSS_171 BJ13 N49 VSS_271
AN5 VSS_73 VSS_172 BJ38 N7 VSS_272
AN7 VSS_74 VSS_173 BJ4 P19 VSS_273
AP4 VSS_75 VSS_174 BJ42 P2 VSS_274
AP48 VSS_76 VSS_175 BJ46 P23 VSS_275
AP50 VSS_77 VSS_176 BK15 P3 VSS_276
AR11 VSS_78 VSS_177 BK17 P50 VSS_277
AR2 VSS_79 VSS_178 BK25 R49 VSS_278
AR39 VSS_80 VSS_179 BK29 T39 VSS_279
AR44 VSS_81 VSS_180 BK36 T43 VSS_280
AR47 VSS_82 VSS_181 BK40 T47 VSS_281
AR7 VSS_83 VSS_182 BK44 U41 VSS_282
AT10 VSS_84 VSS_183 BK6 U45 VSS_283
AT14 VSS_85 VSS_184 BK8 U50 VSS_284
AT41 VSS_86 VSS_185 BL11 V2 VSS_285
AT49 VSS_87 VSS_186 BL13 V3 VSS_286
AU1 VSS_88 VSS_187 BL19
AU29 BL37 CRESTLINE_1p0
VSS_90 VSS_189
AU36 VSS_92 VSS_191 C12
AU49 VSS_93 VSS_192 C16
AU51 VSS_94 VSS_193 C19
AV39 VSS_95 VSS_194 C28
AV48 VSS_96 VSS_195 C29
A AW1 VSS_97 VSS_196 C33 A
AW12 VSS_98 VSS_197 C36
AW16 VSS_99 VSS_198 C41
CRESTLINE_1p0 DELL CONFIDENTIAL/PROPRIETARY

Title
Crestline (VSS)

M-08 0.1

5 4 3 2 1
1 2 3 4 5 6 7 8
32.768KHZ R259 10M +RTC_CELL +RTC_CELL

2 1
1
W1
R251 0 R272 R283
ICH_RTCX1 1 4 1 2 ICH_RTCX2 332K/F 332K/F
2
2 3 ICH_INTVRMEN ICH_LAN100_SLP
1
1
C378 32.768KHZ C369
A A
15P/50V 15P/50V
2
2
R265 R282
0_NC 0_NC
2
ICH8M Internal VR Enable Strap ICH8M LAN100 SLP Strap
+RTC_CELL
(Internal VR for VccSus1.05, VccSus1.5, VccCL1.5) (Internal VR for VccLAN1.05 and VccCL1.05)
Low = Internal VR Disabled Low = Internal VR Disabled
ICH_INTVRMEN High = Internal VR Enabled(Default) ICH_LAN100_SLP High = Internal VR Enabled(Default)
1
+1.05V_VCCP
R269 R238
1M 20K U8A
ICH_RTCX1 AG25 E5 LPC_LAD0 <28>
2
RTCX1 FWH0/LAD0
2
ICH_RTCRST# ICH_RTCX2 AF24 F5
RTCX2 FWH1/LAD1 LPC_LAD1 <28>
ICH_INTRUDER# G8 R257 R264 R276
FWH2/LAD2 LPC_LAD2 <28>
ICH_RTCRST# AF23 F6 56_NC 56_NC 56
RTCRST# FWH3/LAD3 LPC_LAD3 <28>
1
LPC
RTC
C359 Reserved for ICH_INTRUDER# AD22 C4 LPC_LFRAME# <28>
1
1U/10V INTRUDER# FWH4/LFRAME# H_DPRSTP#
Intel Nineveh
2
ICH_INTVRMEN AF25 G9 LPC_LDRQ0# H_DPSLP#

design. INTVRMEN LDRQ0# PAD T68
ICH_LAN100_SLP AD21 E6 LPC_LDRQ1# H_FERR#
LAN100_SLP LDRQ1#/GPIO23 PAD T63
T76 PAD GLAN_CLK B24 AF13 SIO_A20GATE

GLAN_CLK A20GATE SIO_A20GATE <28>
A20M# AG26 H_A20M# <3>
LAN_RSTSYNC D22
R23 ACZ_BIT_CLK LAN_RSTSYNC H_DPRSTP# +3.3V_RUN
<26> ICH_AZ_MDC_BITCLK 1 2 33 DPRSTP# AF26 H_DPRSTP# <3,6,45>
B R24 1 2 10 T73 PAD LAN_RXD0 C21 AE26 H_DPSLP# B
LAN / GLAN
<32> ICH_AZ_CODEC_BITCLK LAN_RXD0 DPSLP# H_DPSLP# <3>
T75 PAD LAN_RXD1 B21
LAN_RXD2 LAN_RXD1 H_FERR#
23 T16 PAD C22 LAN_RXD2 FERR# AD24 H_FERR# <3>
2
2
T70 PAD LAN_TXD0
C46 C47 T72 PAD LAN_TXD1 D21 AG29 R256 R248
27P/50V_NC 27P/50V_NC LAN_TXD2 LAN_TXD0 CPUPWRGD/GPIO49 H_PWRGOOD <3> 10K 10K
T74 PAD E20
1
LAN_TXD1
C20 LAN_TXD2 IGNNE# AF27 H_IGNNE# <3>
CPU
1
T5 PAD AH21 AE24 SIO_A20GATE
GLAN_DOCK#/GPIO13 INIT# H_INIT# <3>
R228 1 2 33 ACZ_SYNC AC20 SIO_RCIN#
<26> ICH_AZ_MDC_SYNC INTR H_INTR <3>
R229 1 2 33 R306 24.9/F D25 AH14 SIO_RCIN#
<32> ICH_AZ_CODEC_SYNC GLAN_COMPI RCIN# SIO_RCIN# <28>
R230 1 2 33 ACZ_RST# +1.5V_PCIE_ICH 1 2 GLAN_COMP C25
<26> ICH_AZ_MDC_RST# GLAN_COMPO
R231 1 2 33 AD23
<32> ICH_AZ_CODEC_RST# NMI H_NMI <3>
R236 1 2 33 ACZ_SDOUT ACZ_BIT_CLK AJ16 AG28
<26> ICH_AZ_MDC_SDOUT HDA_BIT_CLK SMI# H_SMI# <3> +1.05V_VCCP
R237 1 2 33 ACZ_SYNC AJ15
<32> ICH_AZ_CODEC_SDOUT HDA_SYNC
STPCLK# AA24 H_STPCLK# <3>
ACZ_RST# AE14 HDA_RST#
2
Place all series terms close to ICH8 except for SDIN input AE27 THERMTRIP#_ICH
THRMTRIP# R268
lines,which should be close to source.Placement of R23, R228, <32> ICH_AZ_CODEC_SDIN0 AJ17 HDA_SDIN0 PAD T61
AH17 AA23 56
<26> ICH_AZ_MDC_SDIN1
IHDA
R230 & R236 should equal distance to the T split trace point as HDA_SDIN1 TP8 IDE_DD[0..15]
T8 PAD AH15 HDA_SDIN2 IDE_DD[0..15] <23>
R24, R229, R231 & R237 respective. Basically,keep the same T48 PAD AD13 V1 IDE_DD0
1
HDA_SDIN3 DD0 IDE_DD1 THERMTRIP#_ICH
distance from T for all series termination resistors. DD1 U2
ACZ_SDOUT AE13 V3 IDE_DD2
HDA_SDOUT DD2 IDE_DD3
DD3 T1
SPEAKER_DET# AE10 V4 IDE_DD4
<32> SPEAKER_DET# HDA_DOCK_EN#/GPIO33 DD4
RTC_BAT_DET# AG14 T5 IDE_DD5
<30> RTC_BAT_DET# HDA_DOCK_RST#/GPIO34 DD5
AB2 IDE_DD6
C361 DD6
<23> SATA_TX0- 2 1 3900P/25V SATA_TX0-_C SATA_ACT#_R AF10 SATALED# DD7 T6 IDE_DD7
C360 2 1 3900P/25V SATA_TX0+_C T3 IDE_DD8
C <23> SATA_TX0+ DD8 C
AF6 R2 IDE_DD9
<23> SATA_RX0- SATA0RXN DD9
AF5 T4 IDE_DD10
<23> SATA_RX0+ SATA0RXP DD10
C362 2 1 3900P/25V SATA_TX2-_C SATA_TX0-_C AH5 V6 IDE_DD11
<23> SATA_TX2- SATA0TXN DD11
C363 2 1 3900P/25V SATA_TX2+_C SATA_TX0+_C AH6 V5 IDE_DD12
<23> SATA_TX2+ SATA0TXP DD12
U1 IDE_DD13
IDE
DD13 IDE_DD14
AG3 SATA1RXN DD14 V2
AG4 U6 IDE_DD15
SATA1RXP DD15
Distance between the ICH-8 M and cap on the "P" AJ4 SATA1TXN
signal should be identical distance between the 9/20 Move from SATA port 1 AJ3 AA4 IDE_DA0
SATA
SATA1TXP DA0 IDE_DA0 <23>
AA1 IDE_DA1
ICH-6 M and cap on the "N" signal for same pair. DA1 IDE_DA1 <23>
AF2 AB3 IDE_DA2
<23> SATA_RX2- SATA2RXN DA2 IDE_DA2 <23>
<23> SATA_RX2+ AF1 SATA2RXP
SATA_TX2-_C AE4 Y6 IDE_DCS1#
SATA2TXN DCS1# IDE_DCS1# <23>
SATA_TX2+_C AE3 Y5 IDE_DCS3#
SATA2TXP DCS3# IDE_DCS3# <23>
This circuit is
AB7 W4
only needed if the +3.3V_RUN
<17> CLK_PCIE_SATA#
AC6
SATA_CLKN DIOR#
W3
IDE_DIOR# <23>
<17> CLK_PCIE_SATA SATA_CLKP DIOW# IDE_DIOW# <23>
platform has the DDACK# Y2 IDE_DDACK# <23>
SNIFFER. Place within 500mils R250 24.9/F AG1 Y3
SATARBIAS# IDEIRQ IDE_IRQ <23>
1
of ICH8 ball 2 1 SATABIAS AG2 SATARBIAS IORDY Y1 IDE_DIORDY <23>

R263 W5
DDREQ IDE_DDREQ <23>
10K
<29,37> LED_MASK#
ICH8M REV 1.0 AJ0QN230T00
2
3 1 SATA_ACT#_R +3.3V_RUN +3.3V_RUN

<37> SATA_ACT#
2
Q29 R244 2 1 100K RTC_BAT_DET#

D 2N7002W-7-F XOR Chain Entrance Strap R235 R495 2 1 100K SPEAKER_DET# D
1K_NC
R278 0_NC ICH RSVD HDA SDOUT Description
1 2
1
0 0 RSVD ACZ_SDOUT
ICH_RSVD <13>
0 1 Enter XOR Chain
2
1 0 Normal Operation (Default) R22 Title

1K_NC ICH8-M (CPU,IDE,SATA,LPC,AC97,LAN)
1 1 Set PCIE port config bit 1
1
M-08 0.1

1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
Place TX DC blocking caps close ICH8. U8D

<25> PCIE_RX1- P27 PERN1 DMI0RXN V27 DMI_MTX_IRX_N0 <6>
C90 1 2 0.1U/10V PCIE_TXN1_C P26 V26
Direct Media Interface

<25> PCIE_TX1- <25> PCIE_RX1+ PERP1 DMI0RXP DMI_MTX_IRX_P0 <6>
C97 1 2 0.1U/10V PCIE_TXP1_C PCIE_TXN1_C N29 U29
<25> PCIE_TX1+ PETN1 DMI0TXN DMI_MRX_ITX_N0 <6>
WWAN PCIE_TXP1_C N28 U28
PETP1 DMI0TXP DMI_MRX_ITX_P0 <6>
C101 1 2 0.1U/10V PCIE_TXN2_C M27 Y27
<24> PCIE_TX2- <24> PCIE_RX2- PERN2 DMI1RXN DMI_MTX_IRX_N1 <6>
C106 1 2 0.1U/10V PCIE_TXP2_C M26 Y26
<24> PCIE_TX2+ <24> PCIE_RX2+ PERP2 DMI1RXP DMI_MTX_IRX_P1 <6>
PCIE_TXN2_C L29 W29
PETN2 DMI1TXN DMI_MRX_ITX_N1 <6>
WLAN PCIE_TXP2_C L28 W28
PETP2 DMI1TXP DMI_MRX_ITX_P1 <6>
C114 1 2 0.1U/10V PCIE_TXN3_C
<24> PCIE_TX3-
C116 1 2 0.1U/10V PCIE_TXP3_C K27 AB26
PCI-Express
<24> PCIE_TX3+ <24> PCIE_RX3- PERN3 DMI2RXN DMI_MTX_IRX_N2 <6>
A <24> PCIE_RX3+ K26 PERP3 DMI2RXP AB25 DMI_MTX_IRX_P2 <6> A
PCIE_TXN3_C J29 AA29
C127 1 2 0.1U/10V PCIE_TXN4_C WPAN PCIE_TXP3_C J28 AA28
<26> PCIE_TX4- PETP3 DMI2TXP DMI_MRX_ITX_P2 <6>
C120 1 2 0.1U/10V PCIE_TXP4_C
<26> PCIE_TX4+
<26> PCIE_RX4- H27 PERN4 DMI3RXN AD27 DMI_MTX_IRX_N3 <6>
<26> PCIE_RX4+ H26 PERP4 DMI3RXP AD26 DMI_MTX_IRX_P3 <6>
PCIE_TXN4_C G29 AC29
Express Card PCIE_TXP4_C
Non-iAMT +3.3V_SUS
G28 PETP4 DMI3TXP AC28 DMI_MRX_ITX_P3 <6>
RP27
F27 PERN5 DMI_CLKN T26 CLK_PCIE_ICH# <17>
OC7# 6 5 F26 T25
PERP5 DMI_CLKP CLK_PCIE_ICH <17>
OC9# 7 4 USB_OC0_1# E29
OC5# USB_OC2_3# PETN5 R281 24.9/F
8 3 E28 PETP5 DMI_ZCOMP Y23
OC6# 9 2 OC4# Y24 DMI_COMP 2 1 Place within 500mils of ICH8
DMI_IRCOMP +1.5V_PCIE_ICH
10 1 USB_OC8# D27
+3.3V_SUS PERN6/GLAN_RXN
D26 PERP6/GLAN_RXP USBP0N G3 ICH_USBP0- <27>
10P8R-10K C29 PETN6/GLAN_TXN USBP0P G2 ICH_USBP0+ <27> USB[1B]
C28 PETP6/GLAN_TXP USBP1N H5 ICH_USBP1- <27>
H4 ICH_USBP1+ <27> USB[1A] PCI Pullups +3.3V_RUN
R313 1 ICH_EC_SPI_CLK_R USBP1P RP35
<28> ICH_EC_SPI_CLK 2 15 C23 SPI_CLK USBP2N H2 ICH_USBP2- <27>
Layout Note: ICH_SPI_CS# B23 H1 ICH_USBP2+ <27> USB[2B] 6 5
ICH_SPI_CS1#_R SPI_CS0# USBP2P
Place R313,R311 and R327 E22 J3 ICH_USBP3- <27> 7 4
SPI
SPI_CS1# USBP3N PCI_STOP#
within 500 mils from ICH. USBP3P J2 ICH_USBP3+ <27> USB[2A] 8 3
R311 1 2 15 ICH_EC_SPI_DO_R D23 K5 ICH_USBP4- <24> 9 2 PCI_FRAME#
<28> ICH_EC_SPI_DO SPI_MOSI USBP4N
F21 K4 ICH_USBP4+ <24> 3rd MINI CARD 10 1 PCI_REQ1#
<28> ICH_EC_SPI_DIN SPI_MISO USBP4P +3.3V_RUN
USBP5N K2 ICH_USBP5- <33>
USB_OC0_1# AJ19 K1 ICH_USBP5+ <33> CAMERA
<27> USB_OC0_1# OC0# USBP5P 10P8R-8.2K
AG16 L3 ICH_USBP6- <26> +3.3V_RUN
+3.3V_ALW USB_OC2_3# OC1#/GPIO40 USBP6N RP34
<27> USB_OC2_3# AG15 OC2#/GPIO41 USB USBP6P L2 ICH_USBP6+ <26> Express Card
AE15 M5 ICH_USBP7- <37> PCI_SERR# 6 5
R327 OC4# OC3#/GPIO42 USBP7N SB_WLAN_PCIE_RST# 7 PCI_PIRQD#
B AF15 OC4#/GPIO43 USBP7P M4 ICH_USBP7+ <37> BT 4 B
5
U11 15 OC5# AG17 M2 ICH_USBP8- <27> PCI_TRDY# 8 3 SB_NB_PCIE_RST#

R328 15_NC ICH_SPI_CS# OC6# OC5#/GPIO29 USBP8N SB_MCARD3_PCIE_RST#9
2 1 2 AD12 OC6#/GPIO30 USBP8P M1 ICH_USBP8+ <27> USB[3A] 2
1 2 4 OC7# AJ18 N3 ICH_USBP9- <25> 10 1 PCI_DEVSEL#
<30> SPI_CS0# OC7#/GPIO31 USBP9N +3.3V_RUN
1 USB_OC8# AD14 N2 ICH_USBP9+ <25> WWAN USB
SIO_SPI_CS# <28> <27> USB_OC8# OC8# USBP9P
R93 0 OC9# AH18 OC9# 10P8R-8.2K
1 2 7SH08_NC F2 +3.3V_RUN
USBRBIAS# USBRBIAS RP31
USBRBIAS F3
PCI_PERR# 6 5
ICH8M REV 1.0 PCI_IRDY# 7 4 PCI_PIRQC#
PCI_PIRQA# 8 3 PCI_PLOCK#
2
WWAN Noise - ICH improvements 18 Short F2 and F3 at the package PCI_REQ0# 9 2 PCI_PIRQB#
ICH_SPI_CS1#_R Boot BIOS Strap and keep length to less than R301 10 1
OC4# C876 0.1U/10V PCI_GNT0# 22.6/F +3.3V_RUN
1 2
OC5# C871 0.1U/10V GNT0# SPI_CS1# 500mils. Trace Impedance
1 2 10P8R-8.2K 35
2
OC6# C872 1 2 0.1U/10V should be 60ohms +/- 15%.
1
OC7# C873 1 2 0.1U/10V LPC 11 No stuff No stuff
OC9# C878 1 2 0.1U/10V R304 R292
USB_OC8# C874 1 2 0.1U/10V 1K 1K_NC PCI 10 No stuff Stuff
USB_OC0_1# C875 0.1U/10V
1 2 Non-iAMT
1
USB_OC2_3# C877 1 2 0.1U/10V SPI 01 Stuff No stuff LOM REQ0 GNT0 PIRQB +3.3V_SUS Add Buffers as needed for
C84 Loading and fanout concerns.
PIRQC 1 2
1394/MediaCard REQ1 GNT1 PIRQD 0.047U/10V
5
U10
<20,35> PCI_AD[0..31] U8B 2
PCI_AD0 D20 A4 PCI_REQ0# 4
AD0 REQ0# PCI_REQ0# <35> PCI_RST# <20,35>
PCI_AD1 PCI_GNT0# PCI_RST#_G
PCI_AD2
E19
D19
AD1 PCI GNT0# D7
E18 PCI_REQ1#
PCI_GNT0# <35> 1
C AD2 REQ1#/GPIO50 PCI_REQ1# <20> C
PCI_AD3 A20 C18 PCI_GNT1# 7SH32
AD3 GNT1#/GPIO51 PCI_GNT1# <20>
PCI_AD4 D17 B19 SB_WWAN_PCIE_RST#
AD4 REQ2#/GPIO52 SB_WWAN_PCIE_RST# <25>
PCI_AD5 A21 F18 +3.3V_SUS
PCI_AD6 AD5 GNT2#/GPIO53 SB_LOM_PCIE_RST# SB_NB_PCIE_RST# C357
A19 AD6 REQ3#/GPIO54 A11 SB_LOM_PCIE_RST#
PCI_AD7 C19 C10 1 2
AD7 GNT3#/GPIO55
2
PCI_AD8 A18
PCI_AD9 AD8 0.047U/10V
B16 AD9 C/BE0# C17 PCI_C_BE0# <20,35>
5
PCI_AD10 A12 E15 R307 U28
AD10 C/BE1# PCI_C_BE1# <20,35>
PCI_AD11 E16 F16 1K_NC 2
AD11 C/BE2# PCI_C_BE2# <20,35>
PCI_AD12 A14 E17 4
PCI_C_BE3# <20,35> PLTRST# <6,28>
1
PCI_AD13 AD12 C/BE3# PCI_PLTRST#
G16 AD13 1
PCI_AD14 A15 C8 PCI_IRDY#
AD14 IRDY# PCI_IRDY# <20,35>
PCI_AD15 B6 D9 7SH32
AD15 PAR PCI_PAR <20,35>
PCI_AD16 C11 G6 PCI_RST#_G A16 away override strap.
PCI_AD17 AD16 PCIRST# PCI_DEVSEL#
A9 AD17 DEVSEL# D16 PCI_DEVSEL# <20,35>
PCI_AD18 D11 A7 PCI_PERR# Low = A16 swap override enabled. +3.3V_SUS
AD18 PERR# PCI_PERR# <20,35>
PCI_AD19 B12 B7 PCI_PLOCK# SB_NB_PCIE_RST# High = Default. C355
AD19 PLOCK# PCI_PLOCK#
PCI_AD20 C12 F10 PCI_SERR# 1 2
AD20 SERR# PCI_SERR# <20,35>
PCI_AD21 D10 C16 PCI_STOP#
AD21 STOP# PCI_STOP# <20,35>
PCI_AD22 C7 C9 PCI_TRDY# 0.047U/10V
AD22 TRDY# PCI_TRDY# <20,35>
5
PCI_AD23 F13 A17 PCI_FRAME# U27
AD23 FRAME# PCI_FRAME# <20,35>
PCI_AD24 E11 SB_MCARD3_PCIE_RST# R291 2 1 20K_NC CLK_PCI_ICH 2
PCI_AD25 AD24
E13 AD25 PLTRST# AG24 PCI_PLTRST# SB_WWAN_PCIE_RST# R314 2 1 20K 4 PLTRST1# <24,25,26>
2
PCI_AD26 E12 B10 CLK_PCI_ICH SB_WLAN_PCIE_RST# R300 2 1 20K_NC PCI_PLTRST# 1
AD26 PCICLK CLK_PCI_ICH <17>
PCI_AD27 D8 G7 SB_LOM_PCIE_RST# R324 2 1 20K R310
AD27 PME# ICH_PME# <29>
PCI_AD28 A6 SB_NB_PCIE_RST# R302 2 1 20K_NC 10 7SH32
PCI_AD29 AD28
E8 AD29
PCI_AD30 D6 BIOS should not enable the
2 1
PCI_AD31 AD30
A3 AD31 internal GPIO pull up resistor.
D D
C417
PCI_PIRQA# F9
Interrupt I/F F8 SB_MCARD3_PCIE_RST# 9P/50V
SB_MCARD3_PCIE_RST# <24>
1
PCI_PIRQB# B5 PIRQA# PIRQE#/GPIO2 SB_WLAN_PCIE_RST#
<35> PCI_PIRQB# PIRQB# PIRQF#/GPIO3 G11 SB_WLAN_PCIE_RST# <24>
PCI_PIRQC# C5 F12 SB_NB_PCIE_RST#
<20> PCI_PIRQC#
<20> PCI_PIRQD#
PCI_PIRQD# A10 PIRQC#
PIRQD#
PIRQG#/GPIO4
PIRQH#/GPIO5 B3 PCIE_MCARD2_DET#
SB_NB_PCIE_RST# <6>
PCIE_MCARD2_DET# <25> Reserved for EMI. DELL CONFIDENTIAL/PROPRIETARY
ICH8M REV 1.0
Place resister and cap
PCI_PIRQB: for LOM close to ICH. Title
PCI_PIRQC: for Media Card
35 ICH8-M (USB,DMI,PCIE,PCI)
PCI_PIRQD: for 1394
M-08 0.1

1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
GG request
Place these close to ICH7.
ICH_SMBDATA R518 2 1 0_NC AMT_SMBDAT +3.3V_SUS
9 Non-iAMT
ICH_SMBCLK R519 2 1 0_NC AMT_SMBCLK CLK_ICH_48M
R247 2 1 10K_NC ICH_CL_RST1# 10/1 TDC request
1
A A
R273 2 1 10K AMT_SMBCLK
R271 2 1 10K AMT_SMBDAT +3.3V_RUN R297
R255 2 1 10K ICH_RI# 10_NC
R252 2 1 10K SIO_EXT_SCI#
R261 2 1 1K ICH_PCIE_WAKE#
1 2
2
+3.3V_SUS
Non-iAMT
RP28 R262 C412
1 2 ICH_SMBDATA 8.2K 4.7P/50V_NC
2
3 4 ICH_SMBCLK
1
U8C
4P2R-2.2K ICH_SMBCLK AJ26 AJ12
<24,25,26> ICH_SMBCLK ICH_SMBDATA SMBCLK SATA0GP/GPIO21
<24,25,26> ICH_SMBDATA AD19 SMBDATA SATA1GP/GPIO19 AJ10
Clocks SATA
GPIO
ICH_CL_RST1# AG21 AF11 CLK_ICH_14M
SMB
ICH_CL_RST1# AMT_SMBCLK LINKALERT# SATA2GP/GPIO36
T60 PAD AC17 SMLINK0 SATA3GP/GPIO37 AG11
1
T53 PAD AMT_SMBDAT AE19 SMLINK1 CLK_ICH_14M
CLK14 AG9 CLK_ICH_14M <17>
+3.3V_RUN ICH_RI# AF17 G5 CLK_ICH_48M R254
RI# CLK48 CLK_ICH_48M <17>
10_NC
T69 PAD RSVD_LPCPD# F4 D3 ICH_SUSCLK
PAD T71
1 2
SUS_STAT#/LPCPD# SUSCLK
2
<3,29> ITP_DBRESET# AD15 SYS_RESET#

SLP_S3# AG23 SIO_SLP_S3# <28>
R234 AG12 AF21 C377
<6> PM_BMBUSY# BMBUSY#/GPIO0 SLP_S4# PAD T52
8.2K AD18 4.7P/50V_NC
SIO_SLP_S5# <28>
2
LOM_SMB_ALERT# SLP_S5#
15 <28> LOM_SMB_ALERT# AG22
1
CLKRUN# SMBALERT#/GPIO11 SIO_S4_STATE#

S4_STATE#/GPIO26 AH27 PAD T49
<17> H_STP_PCI# AE20
GPIO
STP_PCI#/GPIO15
1
AG18 AE23 ICH_PWRGD
SYS
<17> H_STP_CPU# STP_CPU#/GPIO25 PWROK ICH_PWRGD <6,38>
DPRSLPVR
DPRSLPVR <6,45>
B R233 CLKRUN# AH11 AJ14 B
Power MGT
10_NC <20,28,35> CLKRUN# CLKRUN#/GPIO32 DPRSLPVR/GPIO16 R270 8.2K
ICH_PCIE_WAKE# AE17 AE21 ICH_BATLOW# 2 1 +3.3V_SUS
<29> ICH_PCIE_WAKE#
2
IRQ_SERIRQ WAKE# BATLOW# ICH_PWRGD R260 2

<20,28> IRQ_SERIRQ AF12 SERIRQ 1 10K
T56 PAD RSV_THRM# AC13 C2
THRM# PWRBTN# SIO_PWRBTN# <28>
Option to " Disable " DPRSLPVR R232 1 2 100K
clkrun. Pulling it down IMVP_PWRGD AJ20 AH20 ICH_LAN_RST#
<28,38,45> IMVP_PWRGD VRMPWRGD LAN_RST# ICH_LAN_RST#
WOL_EN R249 1 2 100K
will keep the clks AJ22 AG27 ICH_RSMRST#
T12 PAD TP7 RSMRST# ICH_RSMRST# <28>
running. ICH_RSMRST# R21 2 1 10K
USB_IDE# AJ8 E1
TACH1/GPIO1 CK_PWRGD CLK_PWRGD <17>
T10 PAD RSVD_GPIO6 AJ9 ICH_LAN_RST# R246 2 1 1M
SIO_EXT_WAKE# TACH2/GPIO6 ICH_CL_PWROK
<29> SIO_EXT_WAKE# AH9 TACH3/GPIO7 CLPWROK E3 ICH_CL_PWROK <6,28>
36 SIO_EXT_SMI# ICH_CL_PWROK R305 2 1 1M
<28> SIO_EXT_SMI#
14<28> SIO_EXT_SCI# SIO_EXT_SCI#
AE16
AC19
GPIO8
AJ25 RSV_SIO_SLP_M# Non-iAMT PLTRST_DELAY# R511 2 1 10K
GPIO12 SLP_M# PAD T9
PCIE_MCARD1_DET# AG8
<24> PCIE_MCARD1_DET# TACH0/GPIO17
USB_MCARD1_DET# R547 1 2 4.7K AH12 F23 9/26 Add PD 10K
Controller Link
<24> USB_MCARD1_DET# GPIO18 CL_CLK0 CL_CLK0 <6>
35 AE11 AE18 RSV_ICH_CL_CLK1
GPIO
T81 PAD GPIO20 CL_CLK1 PAD T58
USB_MCARD2_DET# AG10
<25> USB_MCARD2_DET# SCLOCK/GPIO22
USB_MCARD3_DET# AH25 F22
<24> USB_MCARD3_DET# QRT_STATE0/GPIO27 CL_DATA0 CL_DATA0 <6>
AD16 AF19 RSV_ICH_CL_DATA1
<23> IDE_RST_MOD# QRT_STATE1/GPIO28 CL_DATA1 PAD T4
<17> SATA_CLKREQ# AG13 SATACLKREQ#/GPIO35
PLTRST_DELAY# AF9 D24 CL_VREF0
<18> PLTRST_DELAY# SLOAD/GPIO38 CL_VREF0
15 30<24> WPAN_RADIO_DIS_MINI# AJ11 AH23 CL_VREF1
SDATAOUT0/GPIO39 CL_VREF1 PAD T50
26 <33> CCD_VDD_ON CCD_VDD_ON AD10 SDATAOUT1/GPIO48
CL_RST# AJ23 ICH_CL_RST0# <6>
SPKR AD9
<32> SPKR SPKR
AJ27 PCIE_MCARD3_DET#
MISC
MEM_LED/GPIO24 PCIE_MCARD3_DET# <24>
R241 2 1 0 MCH_ICH_SYNC#_R AJ13 AJ24 ME_EC_ALERT
<6> MCH_ICH_SYNC# MCH_SYNC# ME_EC_ALERT/GPIO10 PAD T11
C EC_ME_ALERT/GPIO14 AF22 PAD T6 C
AJ21 AG19 WOL_EN 10/1 TDC request
<11> ICH_RSVD TP3 WOL_EN/GPIO9 PAD T55
R258 2 1 100K_NC CCD_VDD_ON 26 ICH8M REV 1.0 R227 8.2K 9
2 1 +3.3V_SUS
53 +3.3V_RUN +3.3V_ALW
Non-iAMT
2
+3.3V_SUS
+3.3V_RUN +3.3V_RUN R296 R240
R243 2 1 10K SIO_EXT_SMI# Non-iAMT 3.24K/F 3.24K/F_NC
SMbus address D2
2
R510 2 1 10K LOM_SMB_ALERT# 15
1
2
4
R267 These are for CL_VREF0 CL_VREF1
1K_NC backdrive issue. RP16
+3.3V_RUN 4P2R-2.2K
1
1
SPKR
2
1
C416 R299 C365 R239
1
3
R84 2 1 2.2K_NC IMVP_PWRGD Q8 0.1U/10V 453/F 0.1U/10V_NC 453/F_NC

No Reboot strap. <24,25,26> ICH_SMBDATA 3 1 MEM_SDATA <15>
2
2
2
Low = Default.
SPKR High = No Reboot. 2N7002W-7-F
+3.3V_RUN
+3.3V_RUN
2
D R277 2 1 10K RSV_THRM# +3.3V_RUN Q6 D

R245 2 1 10K_NC MCH_ICH_SYNC#_R 3 1
<24,25,26> ICH_SMBCLK MEM_SCLK <15>
R266 2 1 10K IRQ_SERIRQ
2
R274 2 1 10K RSVD_GPIO6

R540 1 2 100K WPAN_RADIO_DIS_MINI# 2N7002W-7-F
R25
8.2K
30
1
USB_IDE# Title
9/20 Delete R258 ICH8-M (PM,GPIO,SMB,CL)

M-08 0.1

1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
+RTC_CELL U8E
+1.05V_VCCP
A23 VSS[001] VSS[099] K7
2
A5 VSS[002] VSS[100] L1
2
C374 C384 C380 AA2 L13
1U/10V 0.1U/10V 0.1U/10V C407 C402 VSS[003] VSS[101]
AA7 L15
1
U8F 0.1U/10V 0.1U/10V +1.05V_VCCP +1.5V_RUN VSS[004] VSS[102]
A25 L26
1
R91 1 VSS[005] VSS[103]
+5V_RUN 2 100_0402 AD25 VCCRTC VCC1_05[01] A13 D25 AB1 VSS[006] VSS[104] L27
VCC1_05[02] B13 1 R288 AB24 VSS[007] VSS[105] L4
D9 A16 C13 AC11 L5
+ICH_V5REF_RUN V5REF[1] VCC1_05[03] VSS[008] VSS[106]
+3.3V_RUN 2 1 T7 V5REF[2] VCC1_05[04] C14 3 1 2 AC14 VSS[009] VSS[107] M12
VCC1_05[05] D14 AC25 VSS[010] VSS[108] M13
2
SDMK0340L-7-F G4 E14 2 10/0805 AC26 M14
C144 V5REF_SUS VCC1_05[06] VSS[011] VSS[109]
A VCC1_05[07] F14 AC27 VSS[012] VSS[110] M15 A
0.1U/10V AA25 G14 BAT54C AD17 M16
1
VCC1_5_B[01] VCC1_05[08] VSS[013] VSS[111]
Non-iAMT R56 10
AA26
AA27
VCC1_5_B[02] VCC1_05[09] L11
L12
AD20
AD28
VSS[014] VSS[112] M17
M23
VCC1_5_B[03] VCC1_05[10] VSS[015] VSS[113]
+5V_SUS 1 2 AB27 VCC1_5_B[04] VCC1_05[11] L14 AD29 VSS[016] VSS[114] M28
AB28 VCC1_5_B[05] VCC1_05[12] L16 AD3 VSS[017] VSS[115] M29
D7 AB29 L17 AD4 M3
+ICH_V5REF_SUS VCC1_5_B[06] VCC1_05[13] VSS[018] VSS[116]
+3.3V_SUS 2 1 D28 VCC1_5_B[07] VCC1_05[14] L18 AD6 VSS[019] VSS[117] N1
D29 VCC1_5_B[08] VCC1_05[15] M11 AE1 VSS[020] VSS[118] N11
2
CORE
SDMK0340L-7-F E25 M18 AE12 N12
C104 VCC1_5_B[09] VCC1_05[16] VSS[021] VSS[119]
E26 VCC1_5_B[10] VCC1_05[17] P11 1uH+-20%_800mA AE2 VSS[022] VSS[120] N13
0.1U/10V E27 P18 AE22 N14
1
VCC1_5_B[11] VCC1_05[18] L18 +1.5V_RUN VSS[023] VSS[121]

F24 VCC1_5_B[12] VCC1_05[19] T11 AD1 VSS[024] VSS[122] N15
F25 T18 1uH_800MA R52 AE25 N16
VCC1_5_B[13] VCC1_05[20] +1.5V_DMIPLL VSS[025] VSS[123]
G24 VCC1_5_B[14] VCC1_05[21] U11 2 1+1.5V_DMIPLL_R 2 1 AE5 VSS[026] VSS[124] N17
H23 VCC1_5_B[15] VCC1_05[22] U18 AE6 VSS[027] VSS[125] N18
H24 V11 0_0603 AE9 N26
VCC1_5_B[16] VCC1_05[23] VSS[028] VSS[126]
2
J23 VCC1_5_B[17] VCC1_05[24] V12 AF14 VSS[029] VSS[127] N27
J24 V14 C95 C91 AF16 N4
VCC1_5_B[18] VCC1_05[25] 0.01U/25V 10U/6.3V VSS[030] VSS[128]
K24 V16 AF18 N5
1
VCC1_5_B[19] VCC1_05[26] VSS[031] VSS[129]
K25 VCC1_5_B[20] VCC1_05[27] V17 AF3 VSS[032] VSS[130] N6
+1.5V_RUN L23 V18 AF4 P12
VCC1_5_B[21] VCC1_05[28] VSS[033] VSS[131]
L24 VCC1_5_B[22] AG5 VSS[034] VSS[132] P13
VCCA3GP
L25 VCC1_5_B[23] VCCDMIPLL R29 AG6 VSS[035] VSS[133] P14
1
M24 VCC1_5_B[24] AH10 VSS[036] VSS[134] P15

FB_330ohm+-25%_100mHz_ M25 AE28 +VCC_DMI +1.25V_RUN AH13 P16
L31 VCC1_5_B[25] VCC_DMI[1] VSS[037] VSS[135]
N23 AE29 AH16 P17
1.5A_0.09 ohm DC VCC1_5_B[26] VCC_DMI[2] VSS[038] VSS[136]
1
BLM21PG331SN1D N24 AH19 P23
VCC1_5_B[27] +V_CPU_IO C375 C59 VSS[039] VSS[137]
N25 VCC1_5_B[28] V_CPU_IO[1] AC23 AH2 VSS[040] VSS[138] P28
+1.5V_PCIE_ICH P24 AC24 0.1U/10V 22U/10V AF28 P29
2
2
VCC1_5_B[29] V_CPU_IO[2] +1.05V_VCCP VSS[041] VSS[139]
B P25 VCC1_5_B[30] AH22 VSS[042] VSS[140] R11 B
R24 VCC1_5_B[31] VCC3_3[01] AF29 +3.3V_RUN AH24 VSS[043] VSS[141] R12
R25 +V_CPU_IO AH26 R13
VCC1_5_B[32] VSS[044] VSS[142]
1
R26 VCC1_5_B[33] VCC3_3[02] AD2 AH3 VSS[045] VSS[143] R14

1
+ R27 VCC1_5_B[34] AH4 VSS[046] VSS[144] R15
1
C63 C404 C382 C406 T23 AC8 C409 C392 C394 AH8 R16
220U/4V 22U/10V 22U/10V 2.2U/10V VCC1_5_B[35] VCC3_3[03] C390 C381 0.1U/10V 0.1U/10V 4.7U/10V VSS[047] VSS[145]
T24 AD8 AJ5 R17
2
VCC1_5_B[36] VCC3_3[04] VSS[048] VSS[146]
VCCP_CORE
T27 AE8 0.1U/10V 0.1U/10V B11 R18
2
VCC1_5_B[37] VCC3_3[05] VSS[049] VSS[147]
T28 VCC1_5_B[38] VCC3_3[06] AF8 B14 VSS[050] VSS[148] R28
T29 VCC1_5_B[39] B17 VSS[051] VSS[149] R4
U24 VCC1_5_B[40] VCC3_3[07] AA3 B2 VSS[052] VSS[150] T12
U25 VCC1_5_B[41] VCC3_3[08] U7 B20 VSS[053] VSS[151] T13
V23 VCC1_5_B[42] VCC3_3[09] V7 B22 VSS[054] VSS[152] T14
2
V24 VCC1_5_B[43] VCC3_3[10] W1 B8 VSS[055] VSS[153] T15
V25 W6 C411 WWAN Noise - ICH improvements C24 T16
IDE
+1.5V_RUN VCC1_5_B[44] VCC3_3[11] 0.1U/10V VSS[056] VSS[154]

W25 W7 C26 T17
1
VCC1_5_B[45] VCC3_3[12] +3.3V_RUN VSS[057] VSS[155]
Y25 VCC1_5_B[46] VCC3_3[13] Y7 C27 VSS[058] VSS[156] T2
18 C6 VSS[059] VSS[157] U12
1
+VCCSATPLL AJ6 A8 D12 U13

R29 VCCSATAPLL VCC3_3[14] VSS[060] VSS[158]
VCC3_3[15] B15 D15 VSS[061] VSS[159] U14
1
0 +1.5V_RUN AE7 B18 D18 U15
VCC1_5_A[01] VCC3_3[16] VSS[062] VSS[160]
2
AF7 B4 C867 C868 C869 C870 D2 U16
VCC1_5_A[02] VCC3_3[17] VSS[063] VSS[161]
ARX
AG7 B9 C415 C418 C397 0.1U/10V 0.1U/10V 0.1U/10V 0.1U/10V D4 U17

1 2
2
VCC1_5_A[03] VCC3_3[18] VSS[064] VSS[162]
1
+VCCSATPLL_L AH7 C15 0.1U/10V 0.1U/10V 0.1U/10V E21 U23
1
C386 VCC1_5_A[04] VCC3_3[19] VSS[065] VSS[163]
AJ7 D13 E24 U26
PCI
L11 1U/10V VCC1_5_A[05] VCC3_3[20] VSS[066] VSS[164]

D5 E4 U27
2
10uH/100MA VCC3_3[21] VSS[067] VSS[165]

AC1 VCC1_5_A[06] VCC3_3[22] E10 E9 VSS[068] VSS[166] U3
10uH+-20%_100mA AC2 VCC1_5_A[07] VCC3_3[23] E7
+3.3V_SUS +3.3V_RUN
F15 VSS[069] VSS[167] U5
ATX
AC3
AC4
VCC1_5_A[08] VCC3_3[24] F11 Non-iAMT E23
F28
VSS[070] VSS[168] V13
V15
2
C
+VCCSATPLL VCC1_5_A[09] VSS[071] VSS[169] C
+1.5V_RUN AC5 VCC1_5_A[10] VCCHDA AC12 F29 VSS[072] VSS[170] V28
F7 VSS[073] VSS[171] V29
1
AC10 VCC1_5_A[11] VCCSUSHDA AD11 G1 VSS[074] VSS[172] W2
2
C368 C57 C389 AC9 E2 W26
VCC1_5_A[12] VSS[075] VSS[173]
2
1U/10V 10U/6.3V 1U/10V J6 TP_VCCSUS1.05_1 C401 G10 W27
2
VCCSUS1_05[1] TP_VCCSUS1.05_2 PAD T62 C376 0.1U/10V VSS[076] VSS[174]

AA5 AF20 G13 Y28
1
VCC1_5_A[13] VCCSUS1_05[2] PAD T7 0.1U/10V VSS[077] VSS[175]
AA6 G19 Y29
1
VCC1_5_A[14] TP_VCCSUS1.5_1 VSS[078] VSS[176]
VCCSUS1_5[1] AC16 PAD T59 G23 VSS[079] VSS[177] Y4
G12 VCC1_5_A[15] G25 VSS[080] VSS[178] AB4
TP_VCCSUS1.5_2 +3.3V_SUS
G17
H7
VCC1_5_A[16] VCCSUS1_5[2] J7 PAD T64 Non-iAMT G26
G27
VSS[081] VSS[179] AB23
AB5
VCC1_5_A[17] +VCCSUS3_3[0~6] VSS[082] VSS[180]
VCCSUS3_3[01] C3 H25 VSS[083] VSS[181] AB6
AC7 VCC1_5_A[18] H28 VSS[084] VSS[182] AD5
1
+1.5V_RUN AD7 AC18 C128 C387 H29 U4
VCC1_5_A[19] VCCSUS3_3[02] 0.022U/16V 0.022U/16V VSS[085] VSS[183]
VCCSUS3_3[03] AC21 H3 VSS[086] VSS[184] W24
D1 AC22 H6
2
VCCUSBPLL VCCSUS3_3[04] VSS[087]
VCCPSUS
VCCSUS3_3[05] AG20 J1 VSS[088] VSS_NCTF[01] A1

+1.5V_RUN F1 VCC1_5_A[20] VCCSUS3_3[06] AH28 J25 VSS[089] VSS_NCTF[02] A2
USB CORE
Non-iAMT L6 VCC1_5_A[21] J26 VSS[090] VSS_NCTF[03] A28

2
L7 VCC1_5_A[22] VCCSUS3_3[07] P6 J27 VSS[091] VSS_NCTF[04] A29

Place C929 C414 C398 M6 P7 WWAN Noise - ICH improvements 18 J4 AH1
0.1U/10V 0.1U/10V VCC1_5_A[23] VCCSUS3_3[08] VSS[092] VSS_NCTF[05]
close to A24. M7 C1 J5 AH29
1
VCC1_5_A[24] VCCSUS3_3[09] +VCCSUS3_3[7~19] VSS[093] VSS_NCTF[06]

VCCSUS3_3[10] N7 K23 VSS[094] VSS_NCTF[07] AJ1
W23 VCC1_5_A[25] VCCSUS3_3[11] P1 K28 VSS[095] VSS_NCTF[08] AJ2
1
1
+1.5V_RUN P2 C866 C748 C864 C865 C405 K29 AJ28
TP_VCCSUSLAN1 F17 VCCSUS3_3[12] 0.1U/10V 0.1U/10V 0.1U/10V 0.1U/10V 0.1U/10V VSS[096] VSS_NCTF[09]
Non-iAMT T67 PAD VCCLAN1_05[1] VCCSUS3_3[13] P3 K3 VSS[097] VSS_NCTF[10] AJ29
VCCPUSB
TP_VCCSUSLAN2 G18 P4 K6 B1
2
2
T66 PAD VCCLAN1_05[2] VCCSUS3_3[14] VSS[098] VSS_NCTF[11]
VCCSUS3_3[15] P5 VSS_NCTF[12] B29
+VCCGLANPLL +3.3V_RUN F19 R1
VCCLAN3_3[1] VCCSUS3_3[16] ICH8M REV 1.0
D G20 VCCLAN3_3[2] VCCSUS3_3[17] R3 D
2
VCCSUS3_3[18] R5
C119 C413 +VCCGLANPLL A24 R6
0.1U/10V 0.1U/10V VCCGLANPLL VCCSUS3_3[19]
1
GLAN POWER
A26 G22 TP_VCCCL1.05

+1.5V_PCIE_ICH A27
VCCGLAN1_5[1]
VCCGLAN1_5[2]
VCCCL1_05
+VCCCL1_5
PAD T65 DELL CONFIDENTIAL/PROPRIETARY
B26 VCCGLAN1_5[3] VCCCL1_5 A22
2
B27 C419 C422

VCCGLAN1_5[4] 0.1U/10V_NC 1U/10V_NC Title
B28 VCCGLAN1_5[5] VCCCL3_3[1] F20 +3.3V_RUN
1
C146 G21 ICH8-M (POWER,GND)

1
4.7U/6.3V VCCCL3_3[2]
B25 VCCGLAN3_3 Non-iAMT Size Document Number Rev
2
ICH8M REV 1.0 M-08 0.1

+3.3V_RUN
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
A is required to route to Top +1.8V_SUS +1.8V_SUS +1.8V_SUS +1.8V_SUS

DDR_A_DM[0..7] <7>
SoDIMM for AMTto function. DDR_A_D[0..63] <7> DDR_B_DM[0..7] <7>
V_DDR_MCH_REF V_DDR_MCH_REF
DDR_A_DQS[0..7] <7> DDR_B_D[0..63] <7>
Ch.A SODIMM needs to be TOP DDR_A_DQS#[0..7] <7> BOT DDR_B_DQS[0..7] <7>
populated for Intel AMT support. DDR_A_MA[0..14] <6,7,16> DDR_B_DQS#[0..7] <7>
JDIM1 JDIM2
DDR_B_MA[0..14] <6,7,16>
1 VREF VSS46 2 1 VREF VSS46 2
3 4 DDR_A_D1 V_DDR_MCH_REF 3 4 DDR_B_D0
DDR_A_D4 VSS47 DQ4 DDR_A_D0 DDR_B_D1 VSS47 DQ4 DDR_B_D4 V_DDR_MCH_REF
5 DQ0 DQ5 6 5 DQ0 DQ5 6
DDR_A_D5 7 8 DDR_B_D5 7 8
DQ1 VSS15 DDR_A_DM0 DQ1 VSS15 DDR_B_DM0
9 VSS37 DM0 10 9 VSS37 DM0 10
DDR_A_DQS#0 11 12 DDR_B_DQS#0 11 12
DQS#0 VSS5 DQS#0 VSS5
1
DDR_A_DQS0 13 14 DDR_A_D6 DDR_B_DQS0 13 14 DDR_B_D6
DQS0 DQ6 DQS0 DQ6
1
A A
15 16 DDR_A_D7 C277 C276 15 16 DDR_B_D7
DDR_A_D2 VSS48 DQ7 0.1U/10V 2.2U/6.3V DDR_B_D2 VSS48 DQ7 C274 C275
17 18 17 18
2
DDR_A_D3 DQ2 VSS16 DDR_A_D13 DDR_B_D3 DQ2 VSS16 DDR_B_D13 0.1U/10V 2.2U/6.3V
19 20 19 20
2
DQ3 DQ12 DDR_A_D9 DQ3 DQ12 DDR_B_D12
21 VSS38 DQ13 22 21 VSS38 DQ13 22
DDR_A_D8 23 24 DDR_B_D9 23 24
DDR_A_D12 DQ8 VSS17 DDR_A_DM1 DDR_B_D8 DQ8 VSS17 DDR_B_DM1
25 DQ9 DM1 26 25 DQ9 DM1 26
27 VSS49 VSS53 28 27 VSS49 VSS53 28
DDR_A_DQS#1 29 30 DDR_B_DQS#1 29 30
DQS#1 CK0 M_CLK_DDR0 <6> DQS#1 CK0 M_CLK_DDR2 <6>
DDR_A_DQS1 31 32 DDR_B_DQS1 31 32
DQS1 CK0# M_CLK_DDR#0 <6> DQS1 CK0# M_CLK_DDR#2 <6>
33 VSS39 VSS41 34 33 VSS39 VSS41 34
DDR_A_D15 35 36 DDR_A_D10 DDR_B_D15 35 36 DDR_B_D10
DDR_A_D14 DQ10 DQ14 DDR_A_D11 DDR_B_D11 DQ10 DQ14 DDR_B_D14
37 DQ11 DQ15 38 37 DQ11 DQ15 38
39 VSS50 VSS54 40 39 VSS50 VSS54 40
PC4800 DDR2 SDRAM
PC4800 DDR2 SDRAM

41 VSS18 VSS20 42 41 VSS18 VSS20 42
45 DQ17 DQ21 46 45 DQ17 DQ21 46
47 VSS1 VSS6 48 47 VSS1 VSS6 48
DDR_A_DQS#2 49 50 PM_EXTTS#0 PM_EXTTS#0 <6> DDR_B_DQS#2 49 50 PM_EXTTS#1 PM_EXTTS#1 <6>
DDR_A_DQS2 DQS#2 NC3 DDR_A_DM2 DDR_B_DQS2 DQS#2 NC3 DDR_B_DM2
51 52 51 52
SO-DIMM (200P)
SO-DIMM (200P)
DQS2 DM2 DQS2 DM2
53 VSS19 VSS21 54 53 VSS19 VSS21 54
DDR_A_D23 55 56 DDR_A_D22 DDR_B_D18 55 56 DDR_B_D22 +1.8V_SUS Place these Caps near So-Dimm1.
57 DQ19 DQ23 58 57 DQ19 DQ23 58
59 VSS22 VSS24 60 59 VSS22 VSS24 60
63 DQ25 DQ29 64 63 DQ25 DQ29 64
1
65 66 65 66 C270 C269 C279 C280 C281
DDR_A_DM3 VSS23 VSS25 DDR_A_DQS#3 DDR_B_DM3 VSS23 VSS25 DDR_B_DQS#3 2.2U/6.3V 2.2U/6.3V 2.2U/6.3V 2.2U/6.3V 2.2U/6.3V
67 DM3 DQS#3 68 67 DM3 DQS#3 68
69 70 DDR_A_DQS3 69 70 DDR_B_DQS3
2
NC4 DQS3 NC4 DQS3
B 71 VSS9 VSS10 72 71 VSS9 VSS10 72 B
75 DQ27 DQ31 76 75 DQ27 DQ31 76
77 VSS4 VSS8 78 77 VSS4 VSS8 78
79 80 79 80 +1.8V_SUS
<6,16> DDR_CKE0_DIMMA CKE0 CKE1 DDR_CKE1_DIMMA <6,16> <6,16> DDR_CKE2_DIMMB CKE0 CKE1 DDR_CKE3_DIMMB <6,16>
81 VDD7 VDD8 82 81 VDD7 VDD8 82
83 NC1 A15 84 83 NC1 A15 84 Place these Caps near So-Dimm2.
DDR_A_BS2 85 86 DDR_A_MA14 DDR_B_BS2 85 86 DDR_B_MA14
<7,16> DDR_A_BS2 A16_BA2 A14 <7,16> DDR_B_BS2 A16_BA2 A14
87 VDD9 VDD11 88 87 VDD9 VDD11 88
DDR_A_MA12 89 90 DDR_A_MA11 DDR_B_MA12 89 90 DDR_B_MA11
A12 A11 A12 A11
1
DDR_A_MA9 91 92 DDR_A_MA7 DDR_B_MA9 91 92 DDR_B_MA7 C588 C575 C586 C587 C576
DDR_A_MA8 A9 A7 DDR_A_MA6 DDR_B_MA8 A9 A7 DDR_B_MA6 2.2U/6.3V 2.2U/6.3V 2.2U/6.3V 2.2U/6.3V 2.2U/6.3V
93 A8 A6 94 93 A8 A6 94
95 96 95 96
2
DDR_A_MA5 VDD5 VDD4 DDR_A_MA4 DDR_B_MA5 VDD5 VDD4 DDR_B_MA4
97 A5 A4 98 97 A5 A4 98
DDR_A_MA3 99 100 DDR_A_MA2 DDR_B_MA3 99 100 DDR_B_MA2
DDR_A_MA1 A3 A2 DDR_A_MA0 DDR_B_MA1 A3 A2 DDR_B_MA0
101 A1 A0 102 101 A1 A0 102
103 VDD10 VDD12 104 103 VDD10 VDD12 104
DDR_A_MA10 105 106 DDR_A_BS1 DDR_B_MA10 105 106 DDR_B_BS1
A10/AP BA1 DDR_A_BS1 <7,16> A10/AP BA1 DDR_B_BS1 <7,16>
DDR_A_BS0 107 108 DDR_A_RAS# DDR_B_BS0 107 108 DDR_B_RAS# +1.8V_SUS
<7,16> DDR_A_BS0 BA0 RAS# DDR_A_RAS# <7,16> <7,16> DDR_B_BS0 BA0 RAS# DDR_B_RAS# <7,16>
DDR_A_WE# 109 110 DDR_B_WE# 109 110 Place these Caps near So-Dimm1.
<7,16> DDR_A_WE# WE# S0# DDR_CS0_DIMMA# <6,16>
<7,16> DDR_B_WE# WE# S0# DDR_CS2_DIMMB# <6,16>
111 VDD2 VDD1 112 111 VDD2 VDD1 112
DDR_A_CAS# 113 114 M_ODT0 DDR_B_CAS# 113 114 M_ODT2
<7,16> DDR_A_CAS# CAS# ODT0 M_ODT0 <6,16> <7,16> DDR_B_CAS# CAS# ODT0 M_ODT2 <6,16>
115 116 DDR_A_MA13 115 116 DDR_B_MA13
<6,16> DDR_CS1_DIMMA# S1# A13 <6,16> DDR_CS3_DIMMB# S1# A13
1
117 VDD3 VDD6 118 117 VDD3 VDD6 118
M_ODT1 119 120 M_ODT3 119 120 C272 C278 C271 C273
<6,16> M_ODT1 ODT1 NC2 <6,16> M_ODT3 ODT1 NC2
121 122 121 122 0.1U/10V 0.1U/10V 0.1U/10V 0.1U/10V
2
DDR_A_D32 VSS11 VSS12 DDR_A_D36 DDR_B_D32 VSS11 VSS12 DDR_B_D37
123 DQ32 DQ36 124 123 DQ32 DQ36 124
DQ33 DQ37 DQ33 DQ37
127 VSS26 VSS28 128 127 VSS26 VSS28 128
DDR_A_DQS#4 129 130 DDR_A_DM4 DDR_B_DQS#4 129 130 DDR_B_DM4 +1.8V_SUS
C
DDR_A_DQS4 DQS#4 DM4 DDR_B_DQS4 DQS#4 DM4 C
131 DQS4 VSS42 132 131 DQS4 VSS42 132 Place these Caps near So-Dimm2.
133 134 DDR_A_D34 133 134 DDR_B_D38
DDR_A_D35 VSS2 DQ38 DDR_A_D39 DDR_B_D34 VSS2 DQ38 DDR_B_D35
135 DQ34 DQ39 136 135 DQ34 DQ39 136
DDR_A_D38 +3.3V_RUN DDR_B_D39
137 DQ35 VSS55 138 Non-iAMT 137 DQ35 VSS55 138
1
139 140 DDR_A_D40 139 140 DDR_B_D45
DDR_A_D44 VSS27 DQ44 DDR_A_D41 DDR_B_D41 VSS27 DQ44 DDR_B_D44 C574 C584 C578 C577
141 DQ40 DQ45 142 141 DQ40 DQ45 142
DDR_A_D45 143 144 DDR_B_D40 143 144 0.1U/10V 0.1U/10V 0.1U/10V 0.1U/10V
2
DQ41 VSS43 DQ41 VSS43
1
145 146 DDR_A_DQS#5 145 146 DDR_B_DQS#5

DDR_A_DM5 VSS29 DQS#5 DDR_A_DQS5 C580 C579 DDR_B_DM5 VSS29 DQS#5 DDR_B_DQS5
147 DM5 DQS5 148 147 DM5 DQS5 148
149 150 2.2U/6.3V 0.1U/10V 149 150
2
DDR_A_D42 VSS51 VSS56 DDR_A_D43 DDR_B_D47 VSS51 VSS56 DDR_B_D43

151 DQ42 DQ46 152 151 DQ42 DQ46 152
DQ43 DQ47 DQ43 DQ47
155 VSS40 VSS44 156 155 VSS40 VSS44 156
159 DQ49 DQ53 160 159 DQ49 DQ53 160
161 VSS52 VSS57 162 161 VSS52 VSS57 162
163 NCTEST CK1 164 M_CLK_DDR1 <6> 163 NCTEST CK1 164 M_CLK_DDR3 <6>
165 VSS30 CK1# 166 M_CLK_DDR#1 <6> 165 VSS30 CK1# 166 M_CLK_DDR#3 <6>
DDR_A_DQS#6 DDR_B_DQS#6 +3.3V_RUN
DDR_A_DQS6
167
169
DQS#6 VSS45 168
170 DDR_A_DM6 DDR_B_DQS6
167
169
DQS#6 VSS45 168
170 DDR_B_DM6 Non-iAMT
DQS6 DM6 DQS6 DM6
171 VSS31 VSS32 172 171 VSS31 VSS32 172
DQ50 DQ54 DQ50 DQ54
1
DQ51 DQ55 DQ51 DQ55 C264 C268
177 VSS33 VSS35 178 177 VSS33 VSS35 178
DDR_A_D56 179 180 DDR_A_D61 DDR_B_D61 179 180 DDR_B_D57 2.2U/6.3V 0.1U/10V
2
181 DQ57 DQ61 182 181 DQ57 DQ61 182
183 VSS3 VSS7 184 183 VSS3 VSS7 184
DDR_A_DM7 185 186 DDR_A_DQS#7 DDR_B_DM7 185 186 DDR_B_DQS#7
DM7 DQS#7 DDR_A_DQS7 DM7 DQS#7 DDR_B_DQS7
D DDR_A_D59
187
189
VSS34 DQS7 188
190 DDR_B_D59
187
189
VSS34 DQS7 188
190
Non-iAMT D
DDR_A_D63 DQ58 VSS36 DDR_A_D58 DDR_B_D62 DQ58 VSS36 DDR_B_D58
191
193
DQ59 DQ62 192
194 DDR_A_D62 Non-iAMT 191
193
DQ59 DQ62 192
194 DDR_B_D63
MEM_SDATA VSS14 DQ63 MEM_SDATA VSS14 DQ63 +3.3V_RUN
<13> MEM_SDATA 195 SDA VSS13 196 195 SDA VSS13 196
MEM_SCLK 197 198 MEM_SCLK 197 198
<13> MEM_SCLK
+3.3V_RUN 199
SCL
VDD(SPD)
SA0
SA1 200 +3.3V_RUN 199
SCL
VDD(SPD)
SA0
SA1 200 R449 2 1 10K DELL CONFIDENTIAL/PROPRIETARY
2
FOX_AS0A426-N2RN-7F FOX_ AS0A426-N2SN-7F

SMbus address A0 R169 R170 SMbus address A4 R448 Title
10K 10K 10K DDR2 SO-DIMM (200P) X 2
Non-iAMT CLOCK 0,1 CLOCK 2,3
CKE 2,3 CKE 0,1
1
M-08 0.1

1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
TOP
+0.9V_DDR_VTT Layout note: Place 1 cap close to every 1 R-pack terminated to SMDDR_VTERM.
A A
1
C287 C267 C265 C285 C283 C282 C257 C260 C266 C263 C286 C261 C259 C258
0.1U/10V 0.1U/10V 0.1U/10V 0.1U/10V 0.1U/10V 0.1U/10V 0.1U/10V 0.1U/10V 0.1U/10V 0.1U/10V 0.1U/10V 0.1U/10V 0.1U/10V 0.1U/10V
2
+0.9V_DDR_VTT BOT
1
C581 C585 C592 C288 C582 C284 C583 C596 C597 C591 C593 C595 C594 C262
0.1U/10V 0.1U/10V 0.1U/10V 0.1U/10V 0.1U/10V 0.1U/10V 0.1U/10V 0.1U/10V 0.1U/10V 0.1U/10V 0.1U/10V 0.1U/10V 0.1U/10V 0.1U/10V
2
2
B B
+0.9V_DDR_VTT
<6,7,15> DDR_A_MA[0..14] DDR_B_MA[0..14] <6,7,15>
RP26 RP41
DDR_A_MA7 2 1 1 2 DDR_B_MA7
4P2R-S-56 4P2R-S-56
RP25 RP40
4P2R-S-56 4P2R-S-56
RP23 RP37
<7,15> DDR_A_RAS# DDR_A_RAS# 2 1 1 2 DDR_B_RAS#
DDR_B_RAS# <7,15>
<7,15> DDR_A_BS1 DDR_A_BS1 4 3 3 4 DDR_B_BS1
DDR_B_BS1 <7,15>
4P2R-S-56 4P2R-S-56
RP22 RP18
DDR_A_MA13 2 1 1 2 DDR_A_MA10
M_ODT0 4 3 3 4 DDR_A_BS0
<6,15> M_ODT0 DDR_A_BS0 <7,15>
4P2R-S-56 4P2R-S-56
RP21 RP44
<7,15> DDR_A_BS2 DDR_A_BS2 2 1 1 2 DDR_B_MA3
4P2R-S-56 4P2R-S-56
RP20 RP46
C C
Please these resistor DDR_A_MA9 2 1 1 2 DDR_B_MA12 Please these resistor
closely DIMMA,all DDR_A_MA8 4 3 3 4 DDR_B_MA9 closely DIMMB,all
trace length<750 mil. 4P2R-S-56 4P2R-S-56 trace length<750 mil.
RP19 RP45
4P2R-S-56 4P2R-S-56
RP38 RP43
DDR_B_MA13 2 1 1 2 DDR_B_MA10
M_ODT2 4 3 3 4 DDR_B_BS0
<6,15> M_ODT2 DDR_B_BS0 <7,15>
4P2R-S-56 4P2R-S-56
RP17 RP42
DDR_A_WE# 2 1 1 2 DDR_B_WE#
<7,15> DDR_A_WE# DDR_B_WE# <7,15>
DDR_A_CAS# 4 3 3 4 DDR_B_CAS#
<7,15> DDR_A_CAS# DDR_B_CAS# <7,15>
4P2R-S-56 4P2R-S-56
RP24 RP39
4P2R-S-56 4P2R-S-56
R164 1 2 56 R450 2 1 56
<6,15> M_ODT1 M_ODT3 <6,15>
DDR_A_MA1 R165 1 2 56 R451 2 1 56
DDR_B_BS2 <7,15>
R173 1 2 56 R446 2 1 56
<6,15> DDR_CS0_DIMMA# DDR_CS2_DIMMB# <6,15>
R168 1 2 56 R459 2 1 56
<6,15> DDR_CS1_DIMMA# DDR_CS3_DIMMB# <6,15>
R166 1 2 56 R452 2 1 56
<6,15> DDR_CKE0_DIMMA DDR_CKE2_DIMMB <6,15>
D R174 1 2 56 R167 2 1 56 D
<6,15> DDR_CKE1_DIMMA DDR_CKE3_DIMMB <6,15>
DDR_A_MA14 R171 1 2 56 R447 2 1 56 DDR_B_MA14
Title
DDR2 RES ARRAY

M-08 0.1

1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
Y2
R55 0
Non-iAMT CLK_XTAL_IN 1 2 1 2 CLK_XTAL_OUT +3.3V_RUN
+3.3V_RUN +3.3V_RUN CLK_3GPLLREQ# R28 2 1 10K

14.318MHZ
1
SATA_CLKREQ# R38 2 1 10K
C109 C108 CARD_CLK_REQ# R31 2 1 10K
27P/50V 27P/50V MINI1CLK_REQ# R71 2 1 10K
2
2
2
MINI2CLK_REQ# R72 2 1 10K
R39 MINI3CLK_REQ# R59 10K
A
10K_NC R73 14.318MHz 2 1 A
10K
1
1
FSA PCI_LOM PGMODE R42 1 2 10K_NC
2
2
U9
Populate for Napa platforms only.
R47
10K_NC R74 1 7 +CK_VDD_A
10K_NC VDD_SRC_01 VDDA
49 VDD_SRC_02 VSSA 8
Non-iAMT 54
CK505
1
+3.3V_RUN VDD_SRC_03
65 VDD_SRC_04 PCI_STP# 25 H_STP_PCI# <13>
CPU_STP# 24 H_STP_CPU# <13>
0=UMA R61 1 2 10K PCI_PCCARD +CK_VDD_MAIN2 30 23
VDD_PCI_01 MCH_BCLK
36 VDD_PCI_02 CPUT1_MCH 11 4 3 RP12 CLK_MCH_BCLK <5>
1 = Disc. GRFX down 10 MCH_BCLK# 2 1 4P2R-S-22
CPUC1_MCH CLK_MCH_BCLK# <5>
+CK_VDD_MAIN 12 VDD_CPU CPU_BCLK
CPUT0 14 4 3 RP13 CLK_CPU_BCLK <3>
+CK_VDD_48 40 13 CPU_BCLK# 2 1 4P2R-S-22
VDD_48 CPUC0 CLK_CPU_BCLK# <3>
+CK_VDD_REF 18 6 CPU_ITP 4 3 RP10
VDD_REF CPUT2_ITP/SRCT_10 CLK_CPU_ITP <3>
34 5 CPU_ITP# 2 1 4P2R-S-22
+3.3V_RUN CPUC2_ITP/SRCC_10 CLK_CPU_ITP# <3>
CLK_XTAL_IN
Non-iAMT C87 4.7P/50V_NC CLK_XTAL_OUT
20 XIN PGMODE R41 2 10K_NC
1 2 19 XOUT PGMODE 9 1 +3.3V_RUN Non-iAMT
2
Enable ITP R49 1 2 33

<13> CLK_ICH_48M
L64 1 2 0_0603 R44 2.2K_0402 FSA 41 3 PCIE_EXPCARD 4 3 RP8
<3,6> CPU_MCH_BSEL0 48M/FSA SRCT_9 CLK_PCIE_EXPCARD <26>
10K FSB 45 2 PCIE_EXPCARD# 2 1 4P2R-S-33
<3,6> CPU_MCH_BSEL1 FSB/TEST_MODE SRCC_9 CLK_PCIE_EXPCARD# <26>
R43 R58 1 2 2.2K_0402 FSC 23 72
<3,6> CPU_MCH_BSEL2 REF0/FSC_TEST_SEL CLKREQ9# CARD_CLK_REQ# <26>
59 C121 1 2 4.7P/50V_NC 70 PCIE_VGA 4 3 RP3 CLK_PCIE_VGA <18>
1
L65 CLKREF SRCT_8 PCIE_VGA#

<13> CLK_ICH_14M 1 2 BLM18SG260 R57 2 1 15 22 REF1 SRCC_8 69 2 1 4P2R-S-33 CLK_PCIE_VGA# <18> Discrete
B PCI_ICH R60 2 1 51 71 23 B
BK1005LL330 <28> CLK_PCI_5025 CLKREQ8#
C122 1 2 4.7P/50V_NC PCI_SIO 27 66 PCIE_ICH 2 1 RP4
CX5LL330000 PCI1 SRCT_7 CLK_PCIE_ICH <12>
R62 2 1 22 PCI_PCCARD 32 67 PCIE_ICH# 4 3 4P2R-S-0
<20> CLK_PCI_PCCARD PCI2/TME SRCC_7 CLK_PCIE_ICH# <12>
C123 1 2 6P/50V 33 38
R63 PCI_LOM PCI3 CLKREQ7# MCH_3GPLL
<35> CLK_PCI_LOM 2 1 43 34 PCI4/FCTSEL1 SRCT_6 63 2 1 RP5
CLK_MCH_3GPLL <6>
C124 1 2 6P/50V 64 MCH_3GPLL# 4 3 4P2R-S-33
SRCC_6 CLK_MCH_3GPLL# <6>
43 62 R32 2 1 475/F
DOT96T/27M_NSS CLKREQ6# CLK_3GPLLREQ# <6>
44 60 PCIE_MINI2 2 1 RP6
DOT96C/27M_SS SRCT_5 CLK_PCIE_MINI2 <24>
C81 1 2 4.7P/50V 61 PCIE_MINI2# 4 3 4P2R-S-33
SRCC_5 CLK_PCIE_MINI2# <24>
R48 2 1 33 PCI_ICH 37 29 MINI2CLK_REQ# R543 1 2 0
<12> CLK_PCI_ICH PCIF0/ITP_SEL CLKREQ5# MINI2CLK_REQ#_R <24>
SRCT_4 58
<13> CLK_PWRGD 39 VTT_PWRDG#/PD(CKPWRGD/PD#) SRCC_4 59
CLKREQ4# 57
CLK_SCLK 16 55 PCIE_MINI1 2 1 RP7
SCLK SRCT_3 CLK_PCIE_MINI1 <24>
CLK_SDATA 17 56 PCIE_MINI1# 4 3 4P2R-S-33
SDATA SRCC_3 CLK_PCIE_MINI1# <24>
28 MINI1CLK_REQ# R186 1 2 0
CLKREQ3# MINI1CLK_REQ#_R <24>
52 PCIE_MINI3 2 1 4P2R-S-0
+3.3V_RUN SRCT_2 CLK_PCIE_MINI3 <25>
PCIE_MINI3# 3 RP9
Discrete without iAMT 15
31
VSS_01 SRCC_2 53
26 MINI3CLK_REQ#
4
R544 1
CLK_PCIE_MINI3# <25>
2
VSS_02 CLKREQ2# MINI3CLK_REQ#_R <25>
L12 35 50 PCIE_SATA 2 1 RP11 0_0402
VSS_03 SRCT_1/SATAT CLK_PCIE_SATA <11>
1 2 +CK_VDD_MAIN 21 51 PCIE_SATA# 4 3 4P2R-S-33
VSS_04 SRCC_1/SATAC CLK_PCIE_SATA# <11>
BLM21PG600SN1D 4 46
VSS_05 CLKREQ1# SATA_CLKREQ# <13>
120 ohms@100Mhz 42 VSS_06
1
68 VSS_07 SRCT_0/LCD100MT 47
C64 C65 C60 C85 C75 C61 48
0.1U/10V 0.1U/10V 0.1U/10V 0.1U/10V 0.1U/10V 10U/6.3V SRCC_0/LCD100MC
2
CY28547BLFXC FSC FSB FSA CPU SRC PCI

C
R37 2.2
1 0 1 100 100 33 C
+CK_VDD_A +3.3V_ALW +3.3V_RUN 0 0 1 133 100 33

1 2 Non-iAMT
SMbus address D2 0 1 1 166 100 33
1
2
4
C77 C72 0 1 0 200 100 33
L19 0.047U/10V 4.7U/6.3V These are for
2
1 2 +CK_VDD_MAIN2 backdrive issue. R289 RP30 0 0 0 266 100 33

BLM21PG600SN1D 2.2K 4P2R-2.2K
120 ohms@100Mhz 1 1 0 0 333 100 33
1
1
3
C110 C111 C113 Q30 1 1 0 400 100 33
0.1U/10V 0.1U/10V 10U/6.3V 3 1 CLK_SDATA
<28> CKG_SMBDAT
2
1 1 1 RSVD 100 33
2N7002W-7-F
R287 0_NC PCI_LOM = FCTSEL1

R53 2.2 1 2
1 2 +CK_VDD_48 FCTSEL1 PIN43 PIN44 PIN47 PIN48
+3.3V_ALW +3.3V_RUN (PIN34)
1
C99 C93
96/ 96/
0=UMA DOT96T DOT96C 100M_T 100M_C
2
0.047U/10V 4.7U/6.3V
2
R280 1 = Disc.
2.2K
GRFX down 27Mout 27MSSout SRCT0 SRCC0
1
D R54 1 D
2
1 2 +CK_VDD_REF
Q28
3 1 CLK_SCLK
<28> CKG_SMBCLK
1
C100
0.047U/10V
2N7002W-7-F
2
R285 0_NC Title

1 2 CLOCK GENERATOR

M-08 0.1
Date: Wednesday, March 07, 2007 Sheet 17 of 51

1 2 3 4 5 6 7 8
E D C B A
YPRPB_DET: SIGNAL FROM SVIDEO CONNECTOR,

TO SWICH TO COMPONENT OUT.
JVDO1 Delete R236,R247

+3.3V_RUN pre ref schematic.
1 2
3 4 YPRPB_DET# <19>
5 6 +5V_ALW
1
7 8 LCD_SMBCLK <28> SMBUS Address 58 for Inverter.
C372 C371 C373 9 10 SMBUS Address 98 for Temp.sensor.
LCD_SMBDAT <28>
.047U/10V/0402 .047U/10V/0402 .047U/10V/0402 11 12
2
4 4
13 14 TV_Y <19>
15 16
17 18 TV_CVBS <19>
19 20
21 22 TV_C <19>
23 24
25 26 VSYNC <19>
27 28 HSYNC <19>
29 30
31 32 VGA_BLU <19>
33 34
35 36 VGA_GRN <19>
37 38
39 40 VGA_RED <19>
41 42
43 44 G_CLK_DDC2 <19>
45 46 G_DAT_DDC2 <19>
47 48 LCD_TST <29>
49 50
51 52
53 54 PLTRST_DELAY# <13>
55 56
PCIE_MTX_GRX_P0 2 1 PCIE_MTX_C_GRX_P0 57 58 CLK_PCIE_VGA <17>
PCIE_MTX_GRX_N0 C66 .1U/10V/0402 2 1 PCIE_MTX_C_GRX_N0 59 60 CLK_PCIE_VGA# <17>
C69 .1U/10V/0402 61 62
PCIE_MTX_GRX_P1 2 1 PCIE_MTX_C_GRX_P1 63 64 PCIE_MRX_GTX_P0
PCIE_MTX_GRX_N1 C70 .1U/10V/0402 2 1 PCIE_MTX_C_GRX_N1 65 66 PCIE_MRX_GTX_N0
<6> PCIE_MTX_GRX_N[0..15]
C74 .1U/10V/0402 67 68
PCIE_MTX_GRX_N0 PCIE_MTX_GRX_P2 2 1 PCIE_MTX_C_GRX_P2 69 70 PCIE_MRX_GTX_P1
PCIE_MRX_GTX_N[0..15] <6>
PCIE_MTX_GRX_N1 PCIE_MTX_GRX_N2 C76 .1U/10V/0402 2 1 PCIE_MTX_C_GRX_N2 71 72 PCIE_MRX_GTX_N1
PCIE_MTX_GRX_N2 C79 .1U/10V/0402 73 74 PCIE_MRX_GTX_N0
PCIE_MTX_GRX_N3 PCIE_MTX_GRX_P3 2 1 PCIE_MTX_C_GRX_P3 75 76 PCIE_MRX_GTX_P2 PCIE_MRX_GTX_N1
3 PCIE_MTX_GRX_N4 PCIE_MTX_GRX_N3 C80 .1U/10V/0402 PCIE_MTX_C_GRX_N3 PCIE_MRX_GTX_N2 PCIE_MRX_GTX_N2 3
2 1 77 78
PCIE_MTX_GRX_N7 PCIE_MTX_GRX_N4 C88 .1U/10V/0402 2 1 PCIE_MTX_C_GRX_N4 83 84 PCIE_MRX_GTX_N3 PCIE_MRX_GTX_N5
<6> PCIE_MTX_GRX_P[0..15]
PCIE_MTX_GRX_N7 C105 .1U/10V/0402 2 1 PCIE_MTX_C_GRX_N7 101 102 PCIE_MRX_GTX_N6 PCIE_MRX_GTX_N14
PCIE_MTX_GRX_P0 C112 .1U/10V/0402 103 104 PCIE_MRX_GTX_N15
PCIE_MTX_GRX_P1 PCIE_MTX_GRX_P8 2 1 PCIE_MTX_C_GRX_P8 105 106 PCIE_MRX_GTX_P7
PCIE_MTX_GRX_P2 PCIE_MTX_GRX_N8 C115 .1U/10V/0402 2 1 PCIE_MTX_C_GRX_N8 107 108 PCIE_MRX_GTX_N7
PCIE_MRX_GTX_P[0..15] <6>
PCIE_MTX_GRX_P3 C117 .1U/10V/0402 109 110
PCIE_MTX_GRX_P4 PCIE_MTX_GRX_P9 2 1 PCIE_MTX_C_GRX_P9 111 112 PCIE_MRX_GTX_P8 PCIE_MRX_GTX_P0
PCIE_MTX_GRX_P5 PCIE_MTX_GRX_N9 C118 .1U/10V/0402 2 1 PCIE_MTX_C_GRX_N9 113 114 PCIE_MRX_GTX_N8 PCIE_MRX_GTX_P1
PCIE_MTX_GRX_P6 C125 .1U/10V/0402 115 116 PCIE_MRX_GTX_P2
PCIE_MTX_GRX_P7 PCIE_MTX_GRX_P10 2 1 PCIE_MTX_C_GRX_P10 117 118 PCIE_MRX_GTX_P9 PCIE_MRX_GTX_P3
PCIE_MTX_GRX_P8 PCIE_MTX_GRX_N10 C126 .1U/10V/0402 2 1 PCIE_MTX_C_GRX_N10 119 120 PCIE_MRX_GTX_N9 PCIE_MRX_GTX_P4
PCIE_MTX_GRX_P9 C129 .1U/10V/0402 121 122 PCIE_MRX_GTX_P5 +G_PWR_SRC
PCIE_MTX_GRX_P10 PCIE_MTX_GRX_P11 2 1 PCIE_MTX_C_GRX_P11 123 124 PCIE_MRX_GTX_P10 PCIE_MRX_GTX_P6 +PWR_SRC
PCIE_MTX_GRX_P11 PCIE_MTX_GRX_N11 C130 .1U/10V/0402 2 1 PCIE_MTX_C_GRX_N11 125 126 PCIE_MRX_GTX_N10 PCIE_MRX_GTX_P7 80 mil
PCIE_MTX_GRX_P12 C131 .1U/10V/0402 127 128 PCIE_MRX_GTX_P8 80 mil 6
PCIE_MTX_GRX_P13 PCIE_MTX_GRX_P12 2 1 PCIE_MTX_C_GRX_P12 129 130 PCIE_MRX_GTX_P11 PCIE_MRX_GTX_P9 4 5
PCIE_MTX_GRX_P14 PCIE_MTX_GRX_N12 C132 .1U/10V/0402 2 1 PCIE_MTX_C_GRX_N12 131 132 PCIE_MRX_GTX_N11 PCIE_MRX_GTX_P10 2
1
PCIE_MTX_GRX_P15 C134 .1U/10V/0402 133 134 PCIE_MRX_GTX_P11 1
2
PCIE_MTX_GRX_P13 2 1 PCIE_MTX_C_GRX_P13 135 136 PCIE_MRX_GTX_P12 PCIE_MRX_GTX_P12
PCIE_MTX_GRX_N13 C135 .1U/10V/0402 2 1 PCIE_MTX_C_GRX_N13 137 138 PCIE_MRX_GTX_N12 PCIE_MRX_GTX_P13 R94 C160 Q9
C138 .1U/10V/0402 139 140 PCIE_MRX_GTX_P14 100K_0402 .1U/50V/0603 SI3457BDV-T1-E3
3
2 PCIE_MTX_GRX_P14 PCIE_MTX_C_GRX_P14 PCIE_MRX_GTX_P13 PCIE_MRX_GTX_P15 2
2 1 141 142
2
C139 .1U/10V/0402 145 146 INV_PWR_SRC_ON
PCIE_MTX_GRX_P15 2 1 PCIE_MTX_C_GRX_P15 147 148 PCIE_MRX_GTX_P14
1
C156 .1U/10V/0402 151 152
153 154 PCIE_MRX_GTX_P15
+3.3V_SUS 155 156 PCIE_MRX_GTX_N15 R103
157 158 100K_0402
159 160
2
161 162 +3.3V_RUN
163 164 INV_PWR_SRC_ON_R
+1.8V_RUN GFX_PWRGD <38>
3
165 166 LCDVCC_TST_EN <28>
1
167 168 THERMATRIP_VGA# <34> 2 RUN_ON <28,38,39>

For Discrete: C429 C428 169 170 +5V_RUN
Populate C178,C181 .1U/10V/0402 .1U/10V/0402 171 172 Q11
+15V_ALW PANEL_BKEN <29>
2
1
173 174 2N7002W-7-F
<28,29,38,45> RUNPWROK +G_PWR_SRC
+2.5V_RUN 175 176
177 178
1
2
179 180
181 182 C166 C169 C175 C177 C425
183 184 .1U/50V/0402 .1U/50V/0402 .1U/50V/0402 .1U/50V/0402 10U/25V/1206
2
1
185 186
187 188
189 190
191 192
193 194 +3.3V_RUN
195 196
197 198
199 200
5
U13
2 SIO_GFX_PWR <34>
1 CFX_PWR_LIMIT 1
4
1 ACAV_IN <28,34,40>
HONDA_LPF-SC200SMYGA+
7SH08_NC 3
QUANTA
1
R109
2
0_NC
Title
COMPUTER
VGA CARD Connector

FM1 0.1

E D C B A
A B C D E
+5V_RUN
2
D22
SDM10K45-7-F
Setting R,G,B treac
impedance to 50 ohm.
1
L13
1 2 RED
<18> VGA_RED
1
BLM11B750SB
PAD T14 M_SEN#_R R279
L14 0/1206 Place D23,D24,D26 close
1 2 GREEN to JVGA1 <200 mils
4 <18> VGA_GRN 4
BLM11B750SB JVGA1
2
6
CRT_VCC_R
L16 11
1 2 BLUE 1
<18> VGA_BLU
BLM11B750SB 7 +3.3V_RUN
2
12
1
R45 R35 R33 2
150/F 150/F 150/F C86 C68 C62 C82 C73 C67 8 1
22P/50V_NC 22P/50V_NC 22P/50V_NC 10P/50V_NC 10P/50V_NC 10P/50V_NC 13
2
3 3 RED
1
1
D23
9
14 2
PAD T15 M_ID2# 4
10 DA204U_NC
CRT_VCC 15
5
CRT_VCC
FOX_DZ11A91-NB211-9F
3
1
+3.3V_RUN
RP29
4P2R-2.2K
1
D27 SDM10K45-7-F 3 GREEN
4
2
D24
+5V_RUN 2 1 <18> G_DAT_DDC2
2
R290 1K
2
2 1 C400
DA204U_NC
0.01U/25V
5
3 3
1
U29
R286 10
2 4 VGAHSYNC_R 1 2
<18> HSYNC <18> G_CLK_DDC2
+3.3V_RUN
1
74AHCT1G125GW
C408 C395 C399
0.1U/10V Place near U29 10P/50V_NC 10P/50V_NC 1
2
2 1 , U30 < 200 mil
3 BLUE
L15 D26
1 2 JVGA_HS 2
5
BLM11A121S
U30
DA204U_NC
R293 10 L17
2 4 VGAVSYNC_R 1 2 1 2 JVGA_VS
<18> VSYNC
Place All of those BLM11A121S +3.3V_RUN
Inductors Caps close
1
74AHCT1G125GW to JTV <200 mils
C103 C71 C78 C92 1
10P/50V_NC 10P/50V_NC 10P/50V 10P/50V
2
3 SVIDEO_C
C5 22P_NC
2
<18> TV_C 1 2
L4 D20
1
BLM18BD151SN1D Place near JVGA1 connector < DA204U_NC

1
R6 C10 C6
200 mil
2 2
150/F_0402 6P/50V/0402 6P/50V/0402 JTV1 Update it
2
per ref
2
3 +3.3V_RUN
schematic.
SVIDEO_C 6
SVIDEO_CVBS D21
7
C7 22P_NC 5 1
2
<18> TV_Y 1 2 SVIDEO_Y 4 3 SVIDEO_Y
L5 1
1
BLM18BD151SN1D 2
1
R7 C11 C8 FOX_MH1177L-BG6N-7FL
150/F_0402 6P/50V/0402 6P/50V/0402 DA204U_NC
2
11/1 Update FP
2
+3.3V_RUN
C3 22P_NC +3.3V_RUN
1
<18> TV_CVBS 1 2
L3 R218 1
1
+5V_RUN BLM18BD151SN1D 47K_0603

1
3 SVIDEO_CVBS
2
R5 C9 C4
2 1 150/F_0402 6P/50V/0402 6P/50V/0402 2
R212
2
C336 SP_DIF_E 1 2 YPRPB_DET# <18>

2
.1U/10V/0402 2 1 R216 0_0805 D19

2
DA204U_NC
10K
Populate R218 & De-populate R216
1
1 R215 when component VIDEO is enable. 1

5
C342 0_NC
300P_NC
2
<32> AUD_SPDIF_OUT 2 4 SP_DIF 1

R214
2
220_0603
SP_DIFB 2
C337
1 SP_DIFC
.01U/25V/0402
1
R213
2
0_0805
SP_DIF_D QUANTA
U4
COMPUTER
1
74AHCT1G125GW
3
Add R213 pre Title

R211 ref CRT&TV CONN
110_0603 schematic.
1 2 Size Document Number Rev
2
R210 0_0603_NC M-08 0.1

A B C D E
A B C D E
+3.3V_R5C832
+3.3V_R5C832
1 +3.3V_R5C832 1
C149 C152 C154 C155 C438 C162
10U/10V/0805 .01U/25V/0402 .01U/25V/0402 .01U/25V/0402 .01U/25V/0402 .01U/25V/0402
+3.3V_RUN +3.3V_R5C832
Place the power caps close
U12B to the relation pins.
10 VCC_PCI1 VCC_3V 67 1 2
C455 C471 C468 C464 Place the power caps close 20 R142 0_0805
10U/10V/0805 .01U/25V/0402 .1U/10V/0402 .01U/25V/0402 VCC_PCI2
to the relation pins. 27 VCC_PCI3
32 VCC_PCI4
41 C480 C220
VCC_PCI5 .01U/25V/0402 10U/10V/0805
128 VCC_PCI6
61 VCC_RIN
16 VCC_ROUT1
34 VCC_ROUT2
64 VCC_ROUT3
114 VCC_ROUT4
C153 C433 C173 C477 120
.01U/25V/0402 .01U/25V/0402 .47U/10V/0603 .47U/10V/0603 VCC_ROUT5
VCC_MD 86
GND1 4
<12,35> PCI_AD[31..0] GND2 13
PCI Bus PCI_AD31 125 22
PCI_AD30 AD31 GND3
126 AD30 GND4 28
PCI_AD29 127 54
2 PCI_AD28 AD29 GND5 2
PowerOnReset for VccCore 1 AD28 GND6 62
PCI_AD27 2 63
PCI_AD26 AD27 GND7
3 AD26 GND8 68
PCI_AD25 5 118
PCI_AD24 AD25 GND9
6 AD24 GND10 122
PCI_AD23 9
PCI_AD22 AD23
11 AD22
+3.3V_R5C832 PCI_AD21 12 99
PCI_AD20 AD21 AGND1 +3.3V_R5C832
14 AD20 AGND2 102
PCI_AD19 15 103
AD19 AGND3
1
PCI_AD18 17 107
PCI_AD17 AD18 AGND4
18 AD17 AGND5 111
2
R136 PCI_AD16 19
100K_0402 PCI_AD15 AD16 R134 +3.3V_R5C832 +3.3V_R5C832
36 AD15
Route to GPIOG6 (pin 94) on the
PCI_AD14 37 10K_0402 SIO companion chip ECE5011, with
2
PCI_AD13 AD14
38 AD13 the signal named CB_HWSPND#
PCI_AD12 39
1
AD12
1
PCI_AD11
PCI / OTHER
40 AD11
GBRST# should be asserted only C219 PCI_AD10 42 69
1U/10V/0603 PCI_AD9 AD10 HWSPND# R367 R365
43
when system power supply is on. PCI_AD8 44
AD9 10K_0402 100K_0402
PCI_AD7 AD8
46
2
PCI_AD6 AD7 Memory Stick Enable
47 AD6 MSEN 58
PCI_AD5 48
PCI_AD4 AD5
49 AD4 XDEN 55 XD Card Enable
PCI_AD3 50
PCI_AD2 AD3
PCI Bus 51 AD2 Serial ROM disable
PCI_AD1 52 57
PCI_AD0 AD1 UDIO5
53 AD0
<12,35> PCI_PAR 33 SD Card Enable
PAR
<12,35> PCI_C_BE3# 7 C/BE3# UDIO3 65 MMC Card Enable
<12,35> PCI_C_BE2# 21 C/BE2# UDIO4 59
3 3
<12,35> PCI_C_BE1# 35 C/BE1#
<12,35> PCI_C_BE0# 45 C/BE0# UDIO2 56
PCI_AD17 1 2 8
R87 100_0402 IDSEL
UDIO1 60
<12> PCI_REQ1# 124 REQ#
<12> PCI_GNT1# 123 GNT# UDIO0/SRIRQ# 72 IRQ_SERIRQ <13,28>
<12,35> PCI_FRAME# 23 FRAME#
<12,35> PCI_IRDY# 24 IRDY#
<12,35> PCI_TRDY# 25 TRDY# PCI Bus
<12,35> PCI_DEVSEL# 26 DEVSEL#
<12,35> PCI_STOP# 29 115 PCI_PIRQD# <12> 1394 Interrupt
STOP# INTA#
<12,35> PCI_PERR# 30 PERR#
<12,35> PCI_SERR# 31 116 PCI_PIRQC# <12>
Media card Interrupt
SERR# INTB#
71 GBRST#
<12,35> PCI_RST# 119 PCIRST#
<17> CLK_PCI_PCCARD 121 PCICLK
<29,35> SYS_PME# 2 1 70 PME# TEST 66 T33 PAD

R135 0_NC
117 CLKRUN#
CoreLogic CLOCKRUN# <13,28,35> CLKRUN#
The ICH schematics need to include a

2
pull-up resistor to implement CLKRUN#,

and the ICH schematics must have a R5C833T_V00
AJ5C8320H00 R133
pull-down, or constantly drive thesignal 100K_0402
low, in order to disable CLKRUN#.
1
CLK_PCI_PCCARD
4 Refer to DELL 4
1
R102
M07 schematic
33 X06
QUANTA
1 2
C167
12P Title
COMPUTER
2
CRT&TV CONN

M-08 0.1

A B C D E
A B C D E
+3.3V_R5C832
80 mils
+3.3V_RUN_PHY
L22
BLM18PG181SN1D
1 1
U12A C168 C178 C176 C196 modify
10U/10V/0805 .1U/10V/0402 .01U/25V/0402 1000P/50V/0402
98 Place these caps as close to the U26 as possible.

AVCC_PHY1
AVCC_PHY2 106
AVCC_PHY3 110
AVCC_PHY4 112
AS CLOSE AS POSSIBLE TO R5C832

113 TPBIAS0
GUARD GND TPBIAS0 C180 .33U/16V/0603
1394_XI 94
C214 22P/50V/0402 XI R110 R115
56.2/F_0603 56.2/F_0603 C181 .01U/25V/0402
Y4
24.576MHz 104 TPB0N
TPBN0
1394_XO 1 2 95 105 TPB0P
C215 22P/50V/0402 R132 0_0402 XO TPBP0
IEEE1394/SD
Populate C197 for *TPA0P/TPA0N,TPB0P/TPB0N pair trace : As close as possible.

R5C832 chip 108 TPA0N *TPA0P/TPA0N,TPB0P/TPB0N pair trace : Same length electrically.
TPAN0 *Termination resistor for TPA+/- TPB+/- : As close as possible to its cable driver (device pin out).
RICOH_FILO 96 109 TPA0P
C197 .01U/25V/0402_NC FIL0 TPAP0
2 2
RICOH_REXT101
R124 10K/F_0402 REXT
R117 R121 C183 270P/25V/0402
56.2/F_0603 56.2/F_0603
RICOH_VREF100
C191 .01U/25V/0402 VREF
R122 5.11K/F_0402
Circuit area : As small as possible.

Place these caps as close L24
to the U26 as possible. 87 XD_DATA7 DLW21HN121SQ2_NC
MDIO17 XD_DATA7 <22>
3 3 4 4 AS CLOSE AS POSSIBLE TO
92 XD_DATA6
XD_DATA5
2 2 1 1 1394 CONNECTOR.
MDIO15 89 XD_DATA5 <22>
CON2
91 XD_DATA4 UV31413-WSU0D-7F
90 SD/XD/MS_DATA3 TPB0N TPB0- 1
MDIO13 SD/XD/MS_DATA3 <22> 1
1
R119 0_0805
93 SD/XD/MS_DATA2 TPB0P TPB0+ 2
R114 0_0805
81 SD/XD/MS_DATA1 TPA0N TPA0- 3
R79 0_0805
82 SD/XD/MS_DATA0 TPA0P TPA0+ 4
R86 0_0805
5
6
7
8
75 XD_WP# <22>
5
6
7
8
MDIO05
3 SD/XD/MS_CMD 3
MDIO08 88 SD/XD/MS_CMD <22>
+3.3V_R5C832 3 3 4 4
MDIO19 83 XD_ALE <22>
2 2 1 1
MDIO18 85 XD_CLE <22> 11/1 Update FP
L20
2
78 DLW21HN121SQ2_NC
MDIO02 XD_CE# <22>
R146
SD_WP#(XDR/B#) 10K_NC
MDIO03 77 SD_WP#(XDR/B#) <22>
1
80 SD_CD# 2 1
MDIO00 D11 1SS355
SD_CD# <22> close to the Chip
XD_CDSW# <22>
79 MS_INS# 2 1
MDIO01 D10 1SS355
MS_INS# <22>
MDIO09 84 SD/XD/MS_CLK <22>
MDIO04 76 MC_PWR_CTRL_0 <22>
MDIO06 74
T34 PAD
97 RSV
MDIO07 73
R5C833T_V00
4 4
QUANTA
Title
COMPUTER
CRT&TV CONN

M-08 0.1

A B C D E
A B C D E
+3.3V_RUN_CARD
+3.3V_RUN_CARD
1 1
CON6
1 22 SD/XD/MS_DATA2
SD_CD# SD(CD2/WP2/GND) MS-5(DATA2)
<21> SD_CD# 2 SD(CD1) XD-9(GND) 23
SD_WP# 3 24
SD(WP1) MS-6(INS) MS_INS# <21>
49 4 XD-18(VCC) SD-3(VSS1) 25
XD_DATA7 5 26 SD/XD/MS_DATA3
XD_DATA6 XD-17(D7) MS-7(DATA3) XD_WP# +3.3V_RUN_CARD
6 XD-16(D6) XD-8(-WP) 27
XD_DATA5 7 28 2 1 SD/XD/MS_CLK
SD/XD/MS_DATA1 XD-15(D5) MS-8(SCLK) R131 0_0402SD/XD/MS_CMD
8 SD-8(DAT1) SD-2(CMD) 29
XD_DATA4 9 30
SD/XD/MS_DATA0 XD-14(D4) MS-9(VCC) SD/XD/MS_CMD
10 SD-7(DAT0) XD-7(WE) 31
SD/XD/MS_DATA3 11 32
SD/XD/MS_DATA2 XD-13(D3) MS-10(VSS) SD/XD/MS_DATA3 C229 C225 C511 R397
12 XD-12(D2) SD-1(DAT3) 33
13 34 XD_ALE .01U/25V/0402 .01U/25V/0402 .01U/25V/0402 150K_0402
SD-6(GND/VSS2) XD-6(ALE) SD/XD/MS_DATA2
14 MS-1(VSS) SD-9(DAT2) 35
SD/XD/MS_DATA1 15 36 XD_CLE
SD/XD/MS_CMD XD-11(D1) XD-5(CLE) XD_CE#
16 MS-2(BS) XD-4(CE) 37
SD/XD/MS_CLK 2 1 17 38 SD/XD/MS_CLK
SD/XD/MS_DATA1 R149 0_0402 SD-5(CLK) XD-3(RE) SD_WP#(XDR/B#)
18 MS-3(VCC/DATA1) XD-2(R/-B) 39
SD/XD/MS_DATA0 19 40 XD_CDSW#
SD/XD/MS_DATA0 XD-10(D0) XD-1(CD)
20 MS-4(SDIO/DATA0) XD-0(GND) 41
21 SD-4(VCC/VDD)
TAI-SOL144-2400000900
C243
2.2U/6.3V/0603
2
8 IN1 CARD READER 2
<21> XD_CDSW#
<21> SD_WP#(XDR/B#)
<21> XD_DATA7
<21> XD_DATA6
<21> XD_DATA5
<21> XD_DATA4
+3.3V_R5C832
<21> SD/XD/MS_DATA3
<21> SD/XD/MS_DATA2 U16

5 1 +3.3V_RUN_CARD
<21> SD/XD/MS_DATA1 IN OUT
3 NC
<21> SD/XD/MS_DATA0
<21> MC_PWR_CTRL_0 4 EN GND 2
C199
<21> SD/XD/MS_CMD
TPS2051BDBV 1U/10V/0603
<21> XD_WP#
C198
3 <21> XD_ALE 3
.1U/10V/0402
<21> XD_CLE AAT4250 will be tested
by 2'nd source after
<21> XD_CE# proto2 build.
<21> SD/XD/MS_CLK
SD Protect
R558 0_0402_NC
49 Q77
2N7002W-7-F
SD_WP#(XDR/B#) 3 1 SD_WP#
2
XD_CDSW#
4 4
QUANTA
Title
COMPUTER
CRT&TV CONN

M-08 0.1

A B C D E
1 2 3 4 5 6 7 8
+5V_MOD +5V_MOD
SATA 1 & 2 Connector. CON4 ODD Connector.
CON5
R500
56 1 2
23 GND1 GND1 1 3 4
24 2 SATA_TX2+ <11> IDE_RST_MOD# 1 2 IDE_DD8
<11> SATA_TX0+ RXP RXP <13> IDE_RST_MOD# 5 6
25 3 SATA_TX2- <11> IDE_DD7 IDE_DD9
<11> SATA_TX0- RXN RXN 7 8
26 4 IDE_DD6 IDE_DD10
SATA_RX0-_C GND2 GND2 SATA_RX2-_C +3.3V_RUN IDE_DD5 9 10 IDE_DD11
27 TXN TXN 5 11 12
SATA_RX0+_C 28 6 SATA_RX2+_C IDE_DD4 IDE_DD12
TXP TXP IDE_DD3 13 14 IDE_DD13
29 GND3 GND3 7 15 16
1
IDE_DD2 IDE_DD14
0506: ref IDE_DD1 17 18 IDE_DD15
A CL1301 R486 IDE_DD0 19 20 IDE_DDREQ A
+3.3V_RUN 30 3.3V_0 3.3V_0 8 +3.3V_RUN 21 22
31 9 P52 4.7K_0402 IDE_DIOR#
3.3V_1 3.3V_1 IDE_DIOW# 23 24
32 10
2
3.3V_2 3.3V_2 IDE_DIORDY 25 26 IDE_DDACK#_R 2 IDE_DDACK# +5V_MOD
33 GND4 GND4 11 27 28 1
34 12 R191 2 1 8.2K IDE_IRQ R488 22_0402
GND5 GND5 +3.3V_RUN 29 30
35 13 IDE_DA1 2 1
GND6 GND6 +5V_MOD IDE_DA0 31 32 IDE_DA2 R484 100K_0402_NC
+5V_HDD 36 5V_0 5V_0 14 +5V_HDD 33 34
37 15 IDE_DCS1# IDE_DCS3#
5V_1 5V_1 IDE_LED# 35 36
38 5V_2 5V_2 16 2 1 37 38
39 17 R483 510/F_0402_NC
GND7 GND7 39 40
40 RSVD RSVD 18 PLATFORM_BID <29> 41 42
41 19 +5V_MOD
GND8 GND8 43 44
1
Corsica 42 12V_0 12V_0 20 Low : Gilligan 45 46
43 21 R554 2 1
DFHS22FR012 12V_1 12V_1 0 ( with 2nd HDD ) R482 470_NC 47 48
44 22
51
52
12V_2 12V_2 49 50
High : Corsica
51
52
Pin.47 Cable select tyco_1909380-1
QT600806-400S-9F H=Slave,L=Master
Place close to
2
connector side 10/20 Update FP
R481
470_0402
Only for Corsica
Locate caps C626, C627, C628, C629 near HDD Conn. +5V_HDD
1
Length match SATA_C_RX0- & SATA_C_RX0+ within 0 mils.
B B
1
1
C627 2 1 3900P/25V SATA_RX0-_C
<11> SATA_RX0-
C626 2 1 3900P/25V SATA_RX0+_C C888 C889 C890 C891
<11> SATA_RX0+
.1U/10V/0402 1U/10V/0603 .1U/10V/0402 1000P/50V/0402 +5V_MOD
2
2
C629 2 1 3900P/25V SATA_RX2-_C IDE_DD[0..15]
<11> SATA_RX2- <11> IDE_DD[0..15]
C628 2 1 3900P/25V SATA_RX2+_C
<11> SATA_RX2+
IDE_DDREQ
<11> IDE_DDREQ
1
IDE_DIOW#
<11> IDE_DIOW#
Only for Corsica +3.3V_RUN IDE_DIOR# C296 C294 C295 C297 C298
<11> IDE_DIOR#
IDE_DIORDY 10U/10V/0805 1U/10V/0603 .1U/10V/0402 1000P/50V/0402 .1U/10V/0402
<11> IDE_DIORDY
2
IDE_DDACK#
<11> IDE_DDACK#
IDE_IRQ
<11> IDE_IRQ
1
1
IDE_DA1
<11> IDE_DA1
C892 C893 C894 C895 IDE_DA0
<11> IDE_DA0
10U/10V/0805_NC 1U/10V/0603_NC .1U/10V/0402_NC 1000P/50V/0402_NC IDE_DCS1# Place closed to
<11> IDE_DCS1#
2
2
IDE_DA2 MOD connector
<11> IDE_DA2
IDE_DCS3#
<11> IDE_DCS3#
SATA PWR ODD PWR

+5V_MOD +5V_RUN
+5V_ALW +5V_HDD +5V_HDD +5V_RUN
Q52 +5V_ALW +5V_MOD 1 2

SI3456BDV 1 2 R489 0_0805
6 R485 0_0805_NC Q56
C C
5 4 17 SI4800BDY_NC
2 8 3
1
+3.3V_ALW2 +3.3V_ALW2
17 1 7 2
1
C609 +5V_ALW2 6 1
1
10U/10V R479 5
3
1
+5V_ALW2 +15V_ALW 100K C618 R517
2
1
1
1U/16V_NC C613 C610 100K_NC
2
4
1
PR194 PR195 10U/10V_NC 0.01U/25V_NC
2
100K_0402 R478 100K_0402_NC R490
2
1
100K 100K_NC R494 100K_NC

R476 2 1 HDD_EN_5V +15V_ALW 2 1
2
2
100K_NC SATA drive vendors will use only 5V
2
supply from the system and will derive
3
1
3.3V on the drive. If drive power 17
2
5 5 C612
Q51A C608 goals are not achieved, drive vendors Q55A 0.1U/25V_NC
17
2
2N7002DW 0.1U/25V will use both 5V and 3.3V supplies 17 2N7002DW_NC
4
4
6
from the system. Initial power saving
6
17 using 3.3V from system is less than 5%. <29> MODC_EN 2

2 Q55B
<29> HDDC_EN
1
Q51B 2N7002DW_NC
Power Estimate:
1
2N7002DW R515
1
1
SATA drive power consumption estimate at 100K_NC

R514 MobileMark is 1.1W. An additional 150mW
100K can be saved using Intel's IMST driver.
2
2
D D
QUANTA
Title
COMPUTER
SATA (HDD&CD_ROM)

M-08 0.1

1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
+3.3V_WLAN
+3.3V_RUN MiniCard WLAN connector
R155 2 1 100K PCIE_MCARD1_DET# 22
4
2
R145 2 1 100K USB_MCARD1_DET#
+3.3V_WLAN +3.3V_WLAN +1.5V_RUN RP51

4P2R-2.2K
J5 Q75
2
2N7002W-7-F_NC
3
1
<25,26,29> PCIE_WAKE# 1 WAKE# 3.3V_1 2
R157 1 2 0 3 4 J8 WLAN_SMBCLK 1 3
<37> COEX2_WLAN_ACTIVE RESERVED_1 GND0 ICH_SMBCLK <13,25,26>
R158 1 2 0 5 6 MOLEX_48099-6701
A <37> COEX1_BT_ACTIVE RESERVED_2 1.5V_1 A
MINI1CLK_REQ#_R 7 8 40
<17> MINI1CLK_REQ#_R CLKREQ# UIM_PWR
9 10 R242 0_NC
GND1 UIM_DATA
29 <17> CLK_PCIE_MINI1# 11 REFCLK- UIM_CLK 12 2 1
<17> CLK_PCIE_MINI1 13 REFCLK+ UIM_RESET 14
15 16 R550 1 2 0
GND2 UIM_VPP HOST_DEBUG_TX <28> +3.3V_WLAN
MINI1CLK_REQ#_R
40 R380 0_0402
1 2 Q74
PLTRST1# <12,25,26>
1
2
29 R275 1 2 0 17 18 2N7002W-7-F_NC
<28> HOST_DEBUG_RX UIM_C8 GND3
C649 R549 1 2 0 19 20 R387 0_0402_NC WLAN_RADIO_OFF#
220P/50V/0402 <28> 8051_TX UIM_C4 W_DISABLE# WLAN_SMBDATA
21 22 1 2 1 3 ICH_SMBDATA <13,25,26>
2
GND4 PERST# SB_WLAN_PCIE_RST# <12>

<12> PCIE_RX2- 23 PERn0 3.3VAUX1 24 +3.3V_WLAN
<12> PCIE_RX2+ 25 PERp0 GND5 26
27 GND6 1.5V_2 28
29 30 WLAN_SMBCLK R516 0_NC
GND7 SMB_CLK WLAN_SMBDATA
<12> PCIE_TX2- 31 PETn0 SMB_DATA 32 2 1
<12> PCIE_TX2+ 33 PETp0 GND8 34
35 GND9 USB_D- 36 PAD T108
PCIE_MCARD1_DET# 37 38
<13> PCIE_MCARD1_DET# RESERVED_3 USB_D+ PAD T109
USB_MCARD1_DET#
PCI-Express TX and RX direct to connector
39
41
RESERVED_4 GND10 40
42 R551 1 2 0
USB_MCARD1_DET# <13> Suport for WoW
RESERVED_5 LED_WWAN# 8051_RX <28>
43 RESERVED_6 LED_WLAN# 44 LED_WLAN_OUT# <37>
RSV_ICH_CL_CLK1 45 46 1 2 WLAN_RADIO_OFF# 2 1
T101 PAD RESERVED_7 LED_WPAN# LED_WPAN# <37> WLAN_RADIO_DIS# <29>
RSV_ICH_CL_DATA1 R520 0_0402_NC
Non-iAMT T100 PAD
RSV_ICH_CL_RST1#
47
49
RESERVED_8 1.5V_3 48
50 D12
T96 PAD RESERVED_9 GND11
51 52 40 SDMK0340L-7-F
RESERVED_10 3.3V_2
DEBUG PINS 2 1 Prevent backdrive when
JMINI Pin Debug Pin Name EC Pin MOLEX_67910-6700 R152
B 0_NC WoW is enabled. B
16 HOST_DEBUG_TX 70
Place caps close to
17 HOST_DEBUG_RX 71 +3.3V_WLAN
connector. +PWR_SRC +PWR_SRC +3.3V_ALW +3.3V_WLAN
+1.5V_RUN +3.3V_WLAN Q10
19 8051_TX 82
1
SI3456DV_NC
42 8051_RX 81 R112 6
1
100K_NC 5 4
1
1
R113 2
1
C482 C479 C486 C495 + 100K_NC 1
2
0.1U/10V 0.047U/10V 0.1U/10V 0.047U/10V C481 C240 C232 C224 C234
2
4.7U/10V 330U/6.3V/ESR25_NC 0.047U/10V 0.047U/10V 0.1U/10V_NC
3
+3.3V_WLAN +3.3V_RUN WLAN_ENABLE
3
R107 C174
1
1 2 5 470K_0402_NC 4700P/50V/0603_NC
R118 0_0805 Q12A
1
4
2 R111 2N7002DW_NC
MiniCard WPAN connector <28> AUX_EN_WOWL
200K_NC
2
Q12B
1
+3.3V_SUS 2N7002DW_NC
2
+3.3V_RUN +3.3V_RUN +1.5V_RUN
R100 2 1 100K PCIE_MCARD3_DET#
R104 2 1 100K USB_MCARD3_DET# J3
<25,26,29> PCIE_WAKE# 1 WAKE# 3.3V_1 2

R96 1 2 0 3 4 10/22 GG request Place caps close to connector.
<37> COEX2_WLAN_ACTIVE RESERVED_1 GND0
R95 1 2 0 5 6
C <37> COEX1_BT_ACTIVE_MINI RESERVED_2 1.5V_1 +3.3V_RUN C
MINI2CLK_REQ#_R 7 8 +1.5V_RUN
<17> MINI2CLK_REQ#_R CLKREQ# UIM_PWR
9 GND1 UIM_DATA 10
29 <17> CLK_PCIE_MINI2# 11 REFCLK- UIM_CLK 12
13 14 J7
COEX2_WLAN_ACTIVE <17> CLK_PCIE_MINI2 REFCLK+ UIM_RESET MOLEX_48099-6701
15 GND2 UIM_VPP 16
1
1
R98 0_0402 C159 C150 C424

R88 C157 1 2 0.047U/10V 0.047U/10V 0.1U/10V_NC
2
100K_NC 33P/50V_NC PLTRST1# <12,25,26>
17 18
2
UIM_C8 GND3 R99 0_0402_NC

19 UIM_C4 W_DISABLE# 20 WPAN_RADIO_DIS_MINI# <13> 41
21 22 1 2
2
GND4 PERST# SB_MCARD3_PCIE_RST# <12>
1
<12> PCIE_RX3- 23 PERn0 3.3VAUX1 24 +3.3V_RUN
25 26 C164
<12> PCIE_RX3+ PERp0 GND5
27 28 100P/50V_NC
2
GND6 1.5V_2 +3.3V_RUN
29 GND7 SMB_CLK 30 ICH_SMBCLK <13,25,26>
<12> PCIE_TX3- 31 PETn0 SMB_DATA 32 ICH_SMBDATA <13,25,26>
35 36 USBP4_D-
PCIE_MCARD3_DET# GND9 USB_D- USBP4_D+
<13> PCIE_MCARD3_DET# 37 RESERVED_3 USB_D+ 38
2
39 40 USB_MCARD3_DET#
RESERVED_4 GND10 USB_MCARD3_DET# <13>
PCI-Express TX and RX direct to connector 41 42 C170 C171 C158 C151 C161
RESERVED_5 LED_WWAN# 0.1U/10V 0.047U/10V 0.1U/10V 0.047U/10V 4.7U/10V
43 44
1
RESERVED_6 LED_WLAN#
45 RESERVED_7 LED_WPAN# 46 R552 1 2 0LED_WPAN# LED_WPAN# <37>
47 RESERVED_8 1.5V_3 48
MINI2CLK_REQ#_R 49 50
RESERVED_9 GND11
51 RESERVED_10 3.3V_2 52
1
29
C880 Change USBP7 to USBP4
220P/50V/0402 MOLEX_67910-6700
2
D 16 D
L32
USBP4_D- 1 2 ICH_USBP4- <12>
USBP4_D+ 4 3
DLW21SN900SQ2B_NC
ICH_USBP4+ <12>
QUANTA
R326
1
0
2
Layout Note:
R222 and R223 Title
COMPUTER
close to choke MINI-PCI
R325 0 as possible to
1 2 minimize stubs. Size Document Number Rev
M-08 0.1

1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
A A
+3.3V_RUN
R150 2 1 100K PCIE_MCARD2_DET#

R153 2 1 100K USB_MCARD2_DET#
MiniCard WWAN connector
+3.3V_RUN +3.3V_RUN +1.5V_RUN
J4
1 2 J15
<24,26,29> PCIE_WAKE# WAKE# 3.3V_1 MOLEX_48099-4000
B
T98 PAD 3 RESERVED_1 GND0 4 B
T99 PAD 5 RESERVED_2 1.5V_1 6

MINI3CLK_REQ#_R 7 8 UIM_PWR
<17> MINI3CLK_REQ#_R CLKREQ# UIM_PWR C484
9 10 UIM_DATA
GND1 UIM_DATA UIM_CLK
<17> CLK_PCIE_MINI3# 11 REFCLK- UIM_CLK 12 1 2 Place C484 close to J4
13 14 UIM_RESET
<17> CLK_PCIE_MINI3 REFCLK+ UIM_RESET UIM_VPP
15 GND2 UIM_VPP 16 100P/50V_NC
R138 0_0402
1 2 PLTRST1# <12,24,26>
17 18 +1.5V_RUN +3.3V_RUN Place caps close to connector.
UIM_C8 GND3 R141 0_0402_NC
19 UIM_C4 W_DISABLE# 20 WWAN_RADIO_DIS# <29>
21 GND4 PERST# 22 1 2 SB_WWAN_PCIE_RST# <12>
<12> PCIE_RX1- 23 PERn0 3.3VAUX1 24 +3.3V_RUN
<12> PCIE_RX1+ 25 PERp0 GND5 26 41
1
27 GND6 1.5V_2 28
29 30 C211 C221 C222
GND7 SMB_CLK ICH_SMBCLK <13,24,26> 0.047U/10V/0402 33P/50V/0402 0.1U/10V/0402_NC
31 32
2
<12> PCIE_TX1- PETn0 SMB_DATA ICH_SMBDATA <13,24,26>
35 36 ICH_USBP9_D-
PCIE_MCARD2_DET# GND9 USB_D- ICH_USBP9_D+
<12> PCIE_MCARD2_DET# 37 RESERVED_3 USB_D+ 38
39 40 USB_MCARD2_DET#
RESERVED_4 GND10 USB_MCARD2_DET# <13>
PCI-Express TX and RX direct to connector 41 RESERVED_5 LED_WWAN# 42 PAD T32
43 RESERVED_6 LED_WLAN# 44 27
45 46 +3.3V_RUN
MINI3CLK_REQ#_R RESERVED_7 LED_WPAN#
47 RESERVED_8 1.5V_3 48
49 RESERVED_9 GND11 50
1
29 51 RESERVED_10 3.3V_2 52
1
C881
1
220P/50V/0402 + C238 + C217
2
C C
MLX_67910-0002 C230 C226 C227 C231 330U/6.3V/ESR25 330U/6.3V/ESR25
33P/50V/0402 0.047U/10V/0402 33P/50V/0402 0.047U/10V/0402
2
10/4 EMI agree to change P/N
Place C383, C367 close to JSIM1
ESD1
JSIM1 UIM_RESET UIM_VPP UIM_PWR
1 1 6 6
UIM_PWR 5 6 2 5 UIM_PWR
VCC GND UIM_CLK 2 5 UIM_DATA L26
3 3 4 4
UIM_RESET 3 4 UIM_VPP ICH_USBP9_D- 1 2 ICH_USBP9- <12>
RST VPP
2
2
C478 C485 SRV05-4.TCT C498 C475 C228 ICH_USBP9_D+ 4 3 ICH_USBP9+ <12>
UIM_CLK 1 2 UIM_DATA 33P/50V/0402 33P/50V/0402 C510 33P/50V/0402 33P/50V/0402 1U/10V/0603
CLK DATA
1
100P/50V_NC DLW21SN900SQ2B_NC
1
1
1
C367 Layout Note:

C383 100P/50V_NC R140 0_0402 R139 and R140
2
100P/50V_NC SUY_254020MA006H555ZL 1 2
2
close to choke
R139 0_0402 as possible to
Note: Place caps on UIMlines close to WWAN connector 1 2 minimize stubs.
9/27 Change PN
Update FP
Place as close as possible to WWAN connector
D D
QUANTA
Title
COMPUTER
WWAN

VC-08B 0.1

1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
EXPRESS+MDC
+3.3V_SUS
CON3
1 GND0 IAC_SDATAOUT 28 ICH_AZ_MDC_SDOUT <11>

<12> ICH_USBP6- ICH_USBP6- 2 29
A
ICH_USBP6+ USB- RSV2 A
<12> ICH_USBP6+ 3 USB+ RSV3 30
CPUSB# 4 31
CPUSB# +3.3VMDC
5 RSV0 GND5 32
6 RSV1 GND6 33
<13,24,25> ICH_SMBCLK 7 SMBCLK IAC_SYNC 34 ICH_AZ_MDC_SYNC <11>
<13,24,25> ICH_SMBDATA 8 SMBDATA GND7 35
MDC I/F
Express card I/F
9 +1.5VCARD0 IAC_SDATAIN 36 ICH_AZ_MDC_SDIN1 <11>
+1.5V_CARD 10 +1.5VCARD1 GND8 37
11 38 ICH_AZ_MDC_RST1# +1.5V_CARD Max. 650mA, Average 500mA.
<24,25,29> PCIE_WAKE# WAKE# IAC_PESET#
12 39 ICH_AZ_MDC_BITCLK <11>
+3.3V_CARDAUX
CARD_RESET# 13
+3.3VAUX IAC_BITCLK
40
+3V_CARD Max. 1300mA, Average 1000mA.
PERST# GND9
+3.3V_CARD 14 +3.3VCARD0
15 +3.3VCARD1
<17> CARD_CLK_REQ# 16 CLKREQ#
<29> EXPRCRD_PWREN# 17 CPPE#
18 +1.5V_RUN +3.3V_RUN +3.3V_SUS +3.3V_CARDAUX +3.3V_CARD +1.5V_CARD
<17> CLK_PCIE_EXPCARD# REFCLF- U33
<17> CLK_PCIE_EXPCARD 19 REFCLK+
20 GND1
21 GND2 17 AUXIN AUXOUT 15
<12> PCIE_RX4- 22 PERn0 2 3.3VIN_0 3.3VOUT_0 3
<12> PCIE_RX4+ 23 PERp0 4 3.3VIN_1 3.3VOUT_1 5
24 GND3 12 1.5VIN_0 1.5VOUT_0 11
<12> PCIE_TX4- 25 PETn0 14 1.5VIN_1 1.5VOUT_1 13
<12> PCIE_TX4+ 26 PETp0
27 R477 100K
GND4 +3.3V_SUS
+3.3V_SUS 2 1 ExpressSwitch
R475 0_NC 20 8 CARD_RESET#
SHDN# PERST# EXPRCRD_PWREN# R480
<29> EXPRCRD_STDBY# 1 2 1 STBY# CPPE# 10 2 1 100K
B Fox_QT100406-5101-9F 6 9 CPUSB# R474 2 1 100K B
<12,24,25> PLTRST1# SYSRST# CPUSB#
OC# 19
16
Update PN 7
NC
GND0 RCLKEN 18
R5538D001-TR-F
+1.5V_RUN +3.3V_RUN +3.3V_SUS +3.3V_CARDAUX +3.3V_CARD +1.5V_CARD
1
C604 C605 C607 C606 C603 C602
0.1U/10V 0.1U/10V 0.1U/10V 0.1U/10V 0.1U/10V 0.1U/10V
2
Please the cap Please the cap Please the cap Please the cap Please the cap Please the cap
near pin 12 & near pin 2 & 4 near pin 17 near pin 15 near pin 3 & 5 near pin 11 &
14(1.5VIN). (3.3VIN). (AUXIN). (AUXOUT). (3.3VOUT). 13(1.5VOUT).
R184 0
1 2
Q23
BSS138_NL_NC
C C
<11> ICH_AZ_MDC_RST# 3 1 ICH_AZ_MDC_RST1#

2
+5V_SUS
2
2
R185
100K_NC
R188
1
10K_NC
1
<34> MDC_RST_DIS#
NOTE : MDC DISABLE

If platform requires MDC disable,populate this circuit.
If MDC disable isn't required, connect ICH_AZ_MDC_RST# directly to
JMDC connector.
D D
QUANTA
Title
COMPUTER
ExpressCard/SmartCard

M-08 0.1

1 2 3 4 5 6 7 8
A B C D E
1 1
PJP1
L6
USB_OCP 0/1 1 2 <12> ICH_USBP1- 1 2 ICH_USB_P1-
+5V_ALW <12> ICH_USBP1+ 4 3 ICH_USB_P1+
FS1 USB_SIDE_PWR JUSB3
455/5A_NC U26 DLW21SN900SQ2B_NC UB1112C-TB212-7F
1
1 2 2 1 USB_SIDE_PWR
IN GND
1
R9 0 + 1
C32 C31 ICH_USB_P1- A_VCC
1 2 2 A_DATA-
3 7 150U/6.3V/ESR45 .1U/10V/0402 ICH_USB_P1+ 3
<29> USB_SIDE_EN#
2
EN1# OUT1 R8 0 A_DATA+
OC1# 8 4 A_GND SHIELD1 9
1 2 SHIELD2 10
4 EN2# OUT2 6 SHIELD3 11
1
OC2# 5 USB_OC0_1# <12> SHIELD4 12

C12 C17 5
.1U/10V/0402 10U/10V_NC L8 ICH_USB_P0- B_VCC
6
2
B_DATA-
1
C344 <12> ICH_USBP0+ 1 2 ICH_USB_P0+ ICH_USB_P0+ 7 B_DATA+
1
TPS2062DR .1U/25V/0603 <12> ICH_USBP0- 4 3 ICH_USB_P0- + 8
C352 C349 B_GND
2
Each channel is 1A DLW21SN900SQ2B_NC 150U_NC .1U/10V/0402
2
R14 0 Right Side
1 2
2 2
R15 0
1 2
L1
USB_OCP 2/3 <12> ICH_USBP3- 1 2 ICH_USB_P3-
PJP13
<12> ICH_USBP3+ 4 3 ICH_USB_P3+ USB_BACK_PWR JUSB1
1 2 UB1112C-TB213-7F
1
+5V_ALW DLW21SN900SQ2B_NC
1
FS2 + 1
455/5A_NC U25 R1 0 C1 C339 ICH_USB_P3- A_VCC
2 A_DATA-
1 2 2 1 USB_BACK_PWR 1 2 150U/6.3V/ESR45 .1U/10V/0402 ICH_USB_P3+ 3
2
IN GND A_DATA+
4 A_GND SHIELD1 9
R3 0 10
SHIELD2
<29> USB_BACK_EN# 3 EN1# OUT1 7 1 2 SHIELD3 11
OC1# 8 SHIELD4 12
5 B_VCC
4 6 ICH_USB_P2- 6
EN2# OUT2 B_DATA-
1
1
5 L2 ICH_USB_P2+ 7
OC2# USB_OC2_3# <12> B_DATA+
1
C343 C341 <12> ICH_USBP2+ 1 2 ICH_USB_P2+ + 8
.1U/10V/0402 10U/10V_NC ICH_USB_P2- C338 C340 B_GND
<12> ICH_USBP2- 4 3
2
150U_NC .1U/10V/0402
2
1
TPS2062DR C345 DLW21SN900SQ2B_NC

.1U/25V/0603 Rear Side
Each channel is 1A R4 0
2
1 2
R2 0
1 2
3 3
ESD Protect
Gilligan Only
Place ESD diodes as
close as USB connector. +5V_ALW
JUSB2
U3
ICH_USB_P1- 1 ICH_USB_P0- 8
I/O I/O 6 7
2 5 USB_BACK2_EN#
VN VP USB_SIDE_PWR <29> USB_BACK2_EN# 6
ICH_USB_P1+ 3 4 ICH_USB_P0+ USB_OC8#
I/O I/O <12> USB_OC8# 5
SRV05-4 ICH_USBP8+ 4
<12> ICH_USBP8+ 3
ICH_USBP8-
<12> ICH_USBP8- 2
Place ESD diodes as
1
close as USB connector. 53398-0819-8P-R
U1
ICH_USB_P3- 1 6 ICH_USB_P2- MLX_ 53398-0871
I/O I/O
2 VN VP 5 USB_BACK_PWR
ICH_USB_P3+ 3 4 ICH_USB_P2+
I/O I/O
SRV05-4
USB8 for back port
4 4
QUANTA
Title
COMPUTER
USB & Flash

FM1 0.1

A B C D E
1 2 3 4 5 6 7 8
+3.3V_ALW
+3.3V_ALW R390 2 1 10K_NC SIO_SPI_CS# +3.3V_ALW 11 39
R126 1 2100K BC_DAT R370 1 2 100K TP_DET# Place cap
R417 1 2100K_NC BC_A_DAT R322 1 2 100K INVERTER_CBL_DET# R386 2 1 10K DOCK_SMB_ALERT# +RTC_CELL
R321 1 2 100K AUX_LCD_CBL_DET# USIO2 close to pin
2.7K/F 121. +RTC_CELL
R358 2 1 SUS_ON LCD_CBL_DET_L R83 1 2 100K LCD_CBL_DET
<33> LCD_CBL_DET_L
100K 21 R82 2 1 200K R345 0
MEC5025 EC-08
1
R379 2 1 DDR_ON 12 121 MEC5025_VCC0 2 1
<17> CKG_SMBDAT KSO17/GPIOA1/AB1H_DATA VCC0
2.7K/F 21 13 R143
<17> CKG_SMBCLK KSO16/GPIOA0/AB1H_CLK
128 PIN VTQFP
1
R355 2 1 RUN_ON 46 12 ATI_Intel 14 21 +3.3V_ALW 100K_0402
100K_NC R538 1 GPIO5/KSO15 VCC1
<32> AUD_AMP_MUTE# 2 0_NC15 GPIO4/KSO14 VCC1 44 C432
R343 2 1AUX_EN_WOWL 16 65 0.1U/10V
<42> 1.8V_SUS_PWRGD
2
0 EC_CPU_PROCHOT# 17 KSO13/GPIO18 VCC1 MAIN_PWR_SW#
<3> EC_CPU_PROCHOT# KSO12/OUT8 POWER PLANES VCC1 83 <31,34> POWER_ SW_IN0# 2 1
R507 2 1 ATI_Intel R156
Non- T106 PAD 18 KSO11/GPIOC7 (6) VCC1 116
1
A A
12 19 10K_0402
<6,13> ICH_CL_PWROK KSO10/GPIOC6
iAMT T86 PAD
ICH_RSMRST#
20 KSO9/GPIOC5 ALWON
C237
1U/10V/0603
<13> ICH_RSMRST# 23 120 ALWON <44>
2
+5V_RUN +3.3V_ALW RSV_M_ON KSO8/GPIOC4 ALWON
T87 PAD 24 KSO7/GPIO3 POWER_ SW_IN2#/GPIO23 119 SNIFFER_PWR_SW# <33>
T93 PAD RSV_SIO_SLP_M# 25 KEYBOARD/MOUSE 126 INSTANT_ON_SW#
DDR_ON KSO6/GPIO2 POWER_ SW_IN1#/GPIO22 MAIN_PWR_SW#
<42> DDR_ON 27 KSO5/GPIO1 (26) POWER_ SW_IN0# 127
1 SIO_S4_STATE#
<31> TP_DET# 28 KSO4/GPIO0 ACAV_IN 128 ACAV_IN <18,34,40>
+RTC_CELL
R371 ALW_PWRGD_3V_5V 29 POWER SWITCH BGPO0/GPIOA5 118 SNIFFER_RTC_GPO T18 PAD
<44> ALW_PWRGD_3V_5V KSO3/GPIOC3
2
4
6
8
100K_0402_NC 30 (6)
<13> SIO_SLP_S3# KSO2/GPIOC2
1
RP32 13 <13> SIO_SLP_S5# 31
8P4R-4.7K KSO1/GPIOC1 LCD_SMBCLK R144
<39> 3.3V_RUN_ON 32 8 LCD_SMBCLK <18>
2
ALW_PWRGD_3V_5V KSO0/GPIOC0 AB1B_CLK/GPIOA4 LCD_SMBDAT 100K_0402

AB1B_DATA/GPIOA2 7 LCD_SMBDAT <18>
AUX_ON
33 ACCESS BUS 6 DOCK_SMBCLK
1
3
5
7
KSI7/GPIO19 AB1A_CLK
1
CLK_KBD SUS_ON 34 (4) 5 DOCK_SMBDAT

<38,39> SUS_ON
2
DAT_KBD C470 RUN_ON KSI6/GPIO17 AB1A_DATA INSTANT_ON_SW#
<18,38,39> RUN_ON 35 KSI5/GPIO10 <31> INSTANT_POWER_SW# 2 1
CLK_DOCK 0.1U/10V_NC R147
Non- <41> AC_OFF 36 93 1.8V_RUN_ON <39>
2
KSI4/GPIO9 GPIO11/AB2_DATA
1
DAT_DOCK T78 PAD RSV_1.05V_1.25V_M_PWRGD 37 94 10K_0402
KSI3/GPIO8 GPIO12/AB2_CLK LCDVCC_TST_EN <18>
iAMT <31> BC_A_INT# 38 KSI2/GPIO7/BC_A_INT# GPIO13/AB1G_DATA 95 AMT_SMBDAT
AMT_SMBCLK
C236
1U/10V/0603
39 96
2
<31> BC_A_DAT KSI1/GPIO6/BC_A_DAT GPIO14/AB1G_CLK PBAT_SMBDAT
<31> BC_A_CLK 40 KSI0/SGPIO30/BC_A_CLK GPIO87/AB1C_DATA 111 PBAT_SMBDAT <40,41>
CLK_PCI_5025 112 PBAT_SMBCLK
GPIO86/AB1C_CLK PBAT_SMBCLK <40,41>
92 9 SBAT_DH_SMBDAT
<11> SIO_A20GATE SGPIO34/A20M GPIO85/AB1D_DATA
1
10 SNIFFER_GREEN# 50 10 SBAT_DH_SMBCLK
R333 <33> SNIFFER_GREEN# OUT5/KBRST GPIO84/AB1D_CLK +5V_ALW
GPIO93/AB1F_DATA 97 1.5V_RUN_ON <43>
33 <31> CLK_TP_SIO 75 GPIO94/IMCLK GPIO92/AB1F_CLK 98 1.25V_RUN_ON <42>
Place close 76 99 THRM_SMBDAT R374 8.2K_NC
<31> DAT_TP_SIO GPIO95/IMDAT GPIO91/AB1E_DATA THRM_SMBDAT <34>
10 CLK_KBD 77 (10) 100 THRM_SMBCLK DOCK_SMBCLK 2 1
to pin 58. THRM_SMBCLK <34>
1 2
DAT_KBD KCLK GPIO90/AB1E_CLK

78 KDAT
CLK_DOCK 79 43 R393 8.2K_NC
GPIOA6/EMCLK GPIO82/FAN_TACH3 IMVP_PWRGD <13,38,45>
B C426 DAT_DOCK 80 42 R348 2 1 +3.3V_RUN DOCK_SMBDAT 2 1 B
3P/50V 8051_RX GPIOA7/EMDAT GPIO16/FAN_TACH2 2.2K_NC
<24> 8051_RX 81 41 FAN1_TACH <34>
2
8051_TX GPIO20/PS2CLK/8051RX GPIO15/FAN_TACH1 +3.3V_ALW

<24> 8051_TX 82 GPIO21/PS2DAT/8051TX
48 R338 1 2 0
OUT2/PWM3 IMVP_VR_ON <45>
GPIO 47 AUX_EN_WOWL 8.2K R373
OUT9/PWM2 AUX_EN_WOWL <24>
57 (36) 46 3.3V_SUS_ON LCD_SMBCLK 2 1
<6,12> PLTRST# LRESET# OUT11/PWM1 3.3V_SUS_ON <39>
CLK_PCI_5025 58 45
+3.3V_ALW <17> CLK_PCI_5025 PCICLK OUT10/PWM0 BREATH_LED# <37>
59 8.2K R385
<11> LPC_LFRAME# LFRAME#
60 66 SIO_EXT_SCI# LCD_SMBDAT 2 1
<11> LPC_LAD0 LAD0 nEC_SCI/SPDIN2 SIO_EXT_SCI# <13>
61 PCI POWER/LPC BUS 55 PS_ID
<11> LPC_LAD1 LAD1 SGPIO45/MSDATA/SPDOUT2 PS_ID <41>
62 (9) 54 R329 2.2K
<11> LPC_LAD2 LAD2 SGPIO44/MSCLK/SPCLK2 SIO_RCIN# <11>
63 69 BEEP PBAT_SMBDAT 2 1
<11> LPC_LAD3 LAD3 SGPIO46/SPDIN1 BEEP <32>
1
64 68 1.25V_GFX_PCIE_ON
<13,20,35> CLKRUN# CLKRUN# SGPIO47/SPDOUT1
C437 C421 C145 C469 C434 56 67 DEBUG_ENABLE# R339 2.2K
10U/6.3V 0.1U/10V 0.1U/10V 0.1U/10V 0.1U/10V <13,20> IRQ_SERIRQ SER_IRQ SGPIO31/TIN1/SPCLK1 PBAT_SMBCLK 2 1
2
SYSOPT0/SGPIO32/LPC_TX 70 HOST_DEBUG_TX <24>

102 71 R384 2.2K
<12> ICH_EC_SPI_CLK HSTCLK SYSOPT1/SGPIO33/LPC_RX HOST_DEBUG_RX <24>
105 R317 2 1 1M +3.3V_ALW SBAT_DH_SMBDAT 2 1
<12> ICH_EC_SPI_DIN HSTDATAIN
Place these caps close to MEC5025. 107 91 LCD_CBL_DET
<12> ICH_EC_SPI_DO HSTDATAOUT SGPIO40
90 INVERTER_CBL_DET# R372 2.2K
SGPIO41 INVERTER_CBL_DET# <33>
103 89 AUX_LCD_CBL_DET# SBAT_DH_SMBCLK 2 1
<30> EC_FLASH_SPI_CLK FLCLK SGPIO42 AUX_LCD_CBL_DET# <33>
106 HOST/8051 SPI 4 SIO_SPI_CS#
<30> EC_FLASH_SPI_DIN FLDATAIN SGPIO43 SIO_SPI_CS# <12>
108 (8) R369 1 2 100K +3.3V_ALW
<30> EC_FLASH_SPI_DO FLDATAOUT
SGPIO35 1 1 2 LOM_SMB_ALERT# <13>
SFPI_EN R337 0_NC +3.3V_ALW
AMT Non-AMT 10 <13> SIO_PWRBTN# 109 GPIO80 SGPIO36 (SFPI_EN) 2
Net & Part SNIFFER_YELLOW# 110 3 DOCK_SMB_ALERT# 11
Intel Broadcom <33> SNIFFER_YELLOW# GPIO81 SGPIO37
1
GPIO96/TOUT1 52 0.9V_DDR_VTT_ON <42> 1 = Enabled.
3.3V_M_PWRGD Pin15 of 5025 NC 87 11 R376
<29> BC_CLK
86
BC_CLK
BC OUT7/nSMI SIO_EXT_SMI# <13> 0 = Disabled 1K_NC
<29> BC_DAT BC_DAT
C ICH_RSMRST# Pin23 of 5025 NC <29> BC_INT# 85 BC_INT# (3) C
MISCELLANEOUS 115 BAT2_LED# <37>
2
nPWR_LED SFPI_EN
M_ON Pin24 of 5025 NC (8) nBAT_LED 114 BAT1_LED# <37>
MEC5025_XTAL1 122 CLOCK 84 FWP#
XTAL1 nFWP
1
SIO_SLP_M# Pin25 of 5025 NC MEC5025_XTAL2 124 73 0.9V_DDR_VTT_PWRGD T120 PAD
R347 1 MEC5025_XOSEL XTAL2 (3) GPIOA3/WINDMON
2 10K 123 XOSEL GPIO83/32KHZ_OUT 117 EC_32KHZ <29>
R378
1.05V_1.25V_M_PWRGD Pin37 of 5025 NC 49 Flash Recovery. 1K
PWRGD RUNPWROK <18,29,38,45>
C474 4.7U/10V 53
nRESET_OUT/OUT6 RESET_OUT# <38>
R238 Pin24 of 5025 NC 2 1 VR_CAP 22 72 MEC_TEST_PIN T77 PAD
2
VR_CAP TEST_PIN
Refer to UMA 2 1 MEC_AGND 125 Populate
AGND
1
LOM_SUPER_IDDQ NC L23 113 for flash
ref pg 32. BLM11A121S 104
VSS
88
MEC_VCC_PLL VCC_PLL VSS R318 corruption
Refer to UMA +3.3V_ALW 1 2 POWER PLANES VSS 74
+3.3V_ALW
LOM_LOW_PWR# NC L34 (9) 51 0 issue.
ref pg 32. VSS
1
BLM11A121S 101 26
2
VSS_PLL VSS
1
Refer to UMA C427
LOM_CABLE_DETECT NC 0.1U/10V Low = R319
ref pg 32.
2
1 2 MEC5025 +3.3V_ALW 100K

L33 LQFP128-16X16-4-JM6 Write Protected.
BLM11A121S Rev 0.01 (11/09/05)
2
FWP#
2
4
For MEC5025 Rev.C: C685=22uF and
1
+3.3V_ALW RP36 Flash Write
32KHz Clock. External Work Around populate workaround circuit.
Debug Serial Port 4P2R-4.7K R320
MEC5025_XTAL2 Circuit. For MEC5025 Rev.D: C685=4.7uF and +3.3V_ALW Protect bottom 100K_NC
Flash Recovery Port.
depopulate workaround circuit. 4K of internal
2
bootblock flash.
1
3
2
R303 R309 THRM_SMBCLK
2
2
R364 100K_NC 10K_NC C423 THRM_SMBDAT
D 0 4.7U/6.3V_NC D
W2
D28 2 1 R80 R315 R81
1
4 1 MEC5025_XTAL1 CH501H_NC R308 R294 0_NC JDEBUG1 1M 10K 10K

1
10K_NC 1 2 VR_CAP
1
5 1
3 2 ALWON 1 2 1 2 2 Q33 8051_RX
4 DELL CONFIDENTIAL/PROPRIETARY
1
MMBT3906_NL_NC 8051_TX
3
3
C467 32.768KHZ C436

3
22P/50V 22P/50V Q31 2

2
2
2N7002W-7-F_NC 1 R316 0_NC Title

R295 100K_NC MLX_53398-0571_NC 1 2 DEBUG_ENABLE# Ultra I/O Controller MEC5025
1
1 2 Not Stuff 0 ohm when doing

Flash recovery. Size Document Number Rev
M-08 0.1

1 2 3 4 5 6 7 8
A B C D E
Update to 5021
Depopulate R529, R530, R531, R532, R533, R534, R535, R536, R92, R97, C142, C133, C137, C141, C179, C165, C172, L21
Populate R537, C879.
RP15 USIO1
2 1 PCIE_WAKE#
1 +3.3V_ALW
4 3 SYS_PME#
<41> PBAT_PRES# 97 GPIOA[0]
ECE5021 GPIOD[3]/VBUS_DET 63 1
6 5 SBAT_PRES# 98 28 MODPRES# 17
GPIOA[1] GPIOD[4]/OCS1_N
8 7 CHG_PBATT
CHG_SBATT
99
100
GPIOA[2] 128 Pin GPIOD[5]/OCS2_N 29
30
DBAY_MODPRES#
PBAT_DSCHG GPIOA[3] GPIOD[6]/OCS3_N HDDC_EN <23>

8P4R-10K
<20,35> SYS_PME#
SYS_PME#
101
102
GPIOA[4]
GPIOA[5]
VTQFP GPIOD[7]/OCS4_N 31 MODC_EN <23>
ECE5011_CTAL1
PCIE_WAKE# 103 C147 33P_NC
<24,25,26> PCIE_WAKE# GPIOA[6]
1
104 119 R539 1 2 0_NC
<27> USB_BACK_EN# GPIOA[7] VCC1_6/GPIOI[1] +3.3V_ALW
EOL 120 R529 1 2 0_NC VDD18 Y3
VDD18(CAP)/GPIOI[2] ECE5011_CTAL2 R85 24MHz_NC
<27> USB_SIDE_EN# 65 GPIOB[0] XTAL2/GPIOI[3] 122
PWRUSB_OC# 66 123 ECE5011_CTAL1 R78 1 2 1K_0402 1M_NC
RP14 GPIOB[1] XTAL1/CLKIN/GPIOI[4] R530 1 0_NC VDDA18PLL
<27> USB_BACK2_EN# 82 USB 124 2
2
SBAT_PRES# HP_NB_SENSE GPIOB[2] VDDA18PLL(CAP)/GPIOI[5] R531 1 0_NC VDDA33 ECE5011_CTAL2
+3.3V_ALW 2 1 81 GPIOB[3] VDDA33PLL(CAP)/GPIOI[6] 125 2
4 3 PWRUSB_OC# DOCK_HP_MUTE# 80 126 R97 1 2 10K_0402_NC C140 33P_NC
SPDIF_SHDN GPIOB[4] ATEST(VCC1)/GPIOI[7] +3.3V_ALW
6 5 79 GPIOB[5]
8 7 DBAY_MODPRES# T51 PAD 78 GPIOB[6] R92 2
<32> NB_MUTE# 77 GPIOB[7] RBIAS/GPIOIJ[0] 127 1 12K/F_0402_NC
8P4R-10K 128 R532 1 2 0_NC
DOCK_SMB_PME# VSS_25/GPIOIJ[1]
11 76 GPIOC[0] USBDP0/GPIOIJ[2] 9 T110 PAD
DOCKED 75 10 T111 PAD
QBUFEN# GPIOC[1] USBDN0/GPIOIJ[3] R533 1
67 GPIOC[2] GPIOs VSS_0/GPIOIJ[4] 11 2 0_NC
R487 2 1 100K PLATFORM_BID DOCK_PWR_EN 68 GPIOC[3] USBDN1/GPIOIJ[5] 12 T112 PAD Route R167 to
R116 1 2 100K MODPRES# 69 13 T113 PAD USIO2 very short
+3.3V_ALW <40> ADAPT_OC GPIOC[4] USBDP1/GPIOIJ[6]
70 14 R534 1 2 0_NC VDDA33
<40> ADAPT_TRIP_SEL GPIOC[5] VDDA33_1/GPIOIJ[7]
ITP_DBRESET# 71
<3,13> ITP_DBRESET# GPIOC[6]
R349 1 2 100K DOCKED 73
<41> PS_ID_DISABLE# GPIOC[7]
R359 1 2 100K PANEL_BKEN 15 T114 PAD
PANEL_BKEN USBDP2/GPIOIK[0]
<18> PANEL_BKEN 74 GPIOD[0] USBDN2/GPIOIK[1] 16 T115 PAD
USBDN3/GPIOIK[2] 18 T116 PAD
1 19 T117 PAD +3.3V_ALW
<37> M_LED_BK# SW_LED GPIOE[0] USBDP3/GPIOIK[3]
2 20 R535 1 2 0_NC VDDA33
SUB_SHDN_ON_BATT GPIOE[1] VDDA33_2/GPIOIK[4] L21
3 GPIOE[2] USBDP4/GPIOIK[5] 21 T118 PAD
2 R120 100K_0402 TOUCH_PAD_LED# VDDA33 2
4 GPIOE[3] USBDN4/GPIOIK[6] 22 T119 PAD 1 2
1 2 IMVP6_PROCHOT# LOW_LIGHT 5 23 R536 1 2 0_NC BLM11A20_NC
+3.3V_RUN GPIOE[4] VSS_2/GPIOK[7]
2
CAM_IMG_CAPTURE 84
DOCK_SMB_PME# MIC_SWITCH GPIOE[5] C179 C165 C172 C182
+5V_ALW 2 1 83 GPIOE[6]
R548 10K 39 LID_CL_PRES# 6 .1U/10V/0402_NC .1U/10V/0402_NC .1U/10V/0402_NC 10U/10V/0805
1
GPIOE[7]
IRMODE 118
+3.3V_ALW GPIOF[0] LID_CL_SIO#
<34> ATF_INT# 117 GPIOF[1] GPIOD[1]/CIRTX 61
BID0 116 62
GPIOF[2] GPIOD[2]/CIRRX 1.05V_RUN_ON <43>
BID1
CHIPSET_ID1
115 GPIOF[3] CIRCC CIRTX 113
50 112 GPIOF[4] CIRRX 114 CIRRX <31>
VGA_IDENTIFY 111
Rsvd_LOM_IDDQ GPIOF[5]
110 GPIOF[6] Place C879 close
2
Rsvd_LOM_TPM_EN# 109 8 VDDA33 C879 .1U/10V/0402 +3.3V_ALW

GPIOF[7] VDDA33_0/VCC1_0 to USIO2.8
R76 R69 R65 R66 R537 1 2 0
10K 10K_0402_NC 10K 10K_0402 88
POWER 34
<35> LOM_LOW_PWR# SC_DET# GPIOG[0] VCC1_0/VCC1_1
89 GPIOG[1] VCC1_1/VCC1_2 42
<11,37> LED_MASK# 90 43
1
GPIOG[2] VCC1_2/VCC1_3
2
BID0 50 PLATFORM_BID 91 57
<23> PLATFORM_BID GPIOG[3] VCC1_3/VCC1_4
BID1 92 85 C439 C143 C209 C210 C213
<13> SIO_EXT_WAKE# GPIOG[4] VCC1_4/VCC1_5
CHIPSET_ID1 93 108 .1U/10V/0402 .1U/10V/0402 .1U/10V/0402 .1U/10V/0402 .1U/10V/0402
<12> ICH_PME#
1
VGA_IDENTIFY GPIOG[5] VCC1_5/VCC1_6
<13> ICH_PCIE_WAKE# 94 GPIOG[6]
<24> WLAN_RADIO_DIS# 95 GPIOG[7] CAP_LDO 86
2
1
R77 R70 R68 R67 24 17
<33> WIRELESS_ON/OFF# GPIOH[0] VSS_1
10K_0402_NC 10K 10K_0402_NC 10K_NC 25 36 C435
<37> BT_RADIO_DIS_DC# GPIOH[1] VSS_3
26 37 4.7U/10V/0805
<26> EXPRCRD_PWREN#
2
GPIOH[4] VSS_4
<26> EXPRCRD_STDBY# 27 38
1
IMVP6_PROCHOT# GPIOH[5] VSS_5

<45> IMVP6_PROCHOT# 32 GPIOH[6] VSS_6 39
33 40 VDD18
<38> 5V_3V_1.8V_1.25V_RUN_PWRGD GPIOH[7] VSS_7
VSS_8 41
105 44 VDDA18PLL
3 <18> LCD_TST OUT65 VSS_9 3
VSS_10 45
<25> WWAN_RADIO_DIS# 106 GPIOH[2] VSS VSS_11 47
1
LOM_CABLE_DETECT 107 GPIOH[3] SIO Reset VSS_12 48
2
49 C137
VGA BID2 BID1 BID0 Board Revision VSS_13 4.7U/10V/0805_NC C141 C142 C133
<28> BC_INT# 58 50
2
1 0 0 0 SST (X00) BC_INT# VSS_14 .1U_NC .1U/10V/0402_NC 4.7U/10V/0805_NC
<28> BC_DAT 59 51
1
1 0 0 1 Pre-PT (X01) BC_DAT BC VSS_15
<28> BC_CLK 60 BC_CLK VSS_16 52
1 0 1 0 PT (X02) R569 53
VSS_17
1 0 1 1 ST (X03)
<18,28,38,45> RUNPWROK 2 1RUNPWROK_R 7 PWRGD VSS_18 54
1 0 0 0 QT (A00) 0_NC 55
1 0 0 1 RAMP-2 (A01) VSS_19
35 TEST_PIN MISCELLANEOUS VSS_20 56
PAD T31 64
VSS_21
<28> EC_32KHz 96 32KHz_IN VSS_22 72
VSS_23 87
46 121 +3.3V_ALW
Reset BID NC VSS_24
1
RUNPWROK_R ECE5021-NU
R129
Update P/N 100K_0402
2
R130 10
2
R568 LID_CL_SIO# 1 2 LID_CL#
LID_CL# <31>
0
1
1
C218
0.047U/10V
2
57
4 4
QUANTA
Title
COMPUTER
SIO (GPIO/BC/USB/CIRR)

FM1 0.1

A B C D E
A B C D E
RTC BATTERY 16Mbit (2M Byte)

+3.3V_SUS
Non-iAMT
Layout Note: +RTC_CELL +3.3V_RTC_LDO +PWR_SRC
Place R471 within 500 mils from SPI flash.
1
Place R498 & R534 within 500 mils of the R105 R125 D2 SDMK0340L-7-F
MEC5025. 10K 10K U6
55 1 2 3 OUT IN 1
4
2
U14 5/3#
1
4 4
1 8 2 5 C43
<12> SPI_CS0# CE# VDD GND SHDN
R127 1 2 15 6 C50 1U/25V
<28> EC_FLASH_SPI_CLK SCK
1
R128 1 2 15 5 C201 2.2U/6.3V MAX1615_NC
<28> EC_FLASH_SPI_DO
2
R101 1 SI
<28> EC_FLASH_SPI_DIN 2 15 2 SO HOLD# 7 0.1U/10V
J2
2
1
D1 SDMK0340L-7-F
Non-iAMT C896
3 WP# VSS 4
RTC_BAT_DET# 1
<11> RTC_BAT_DET#
22P/50V_NC SST25VF016B 1 2+RTC_1 1 2 +RTC 2
2
R20 1K 3
22P : CH02206JB08 2M : AKE28FP0K07 RTC-BATTERY_NC
2
MOLEX_53261-0371
C42
TH1 TH4 TH22 TH11 1U/25V
1
2
2
1 H-E354X354D126p2-4 1 H-TC256BE354X354D126P2-4 1 H-E354X354D126p2-4 1 H-E276X315D126p2-4
5 3 5 3 5 3 5 3
4
4
Gfx SATA BTB Conn. Nut -- Only for Gilligan
3 TH17 TH23 TH12 TH5 TH3 TH20 TH19 TH21 3
TH18
2
2
1 H-TC354BE354X354D126p2-4
1 H-TC354BE354X354D126p2-4 1 H-TC354BE354X354D126p2-4
1 H-TC354BE354X354D126p2-4 1 H-E354X354D126p2-4 1 H-C276D98p2-4 1 H-C276D98p2-4 1 H-C276D126p2-4 1 H-C276D126p2-4
5 3 5 3 5 3 5 3 5 3 5 3 5 3 5 3 5 3
4
4
CPU 10/4 EMI request change to NPTH
10/18 EMI request
11/28 EMI request change back to PTH
TH2 TH6 TH16 TH13 TH9 TH10 TH14 TH15
H-TC236BE354X354D126p2-3
2
2
1 H-TC217BC236D126p2-4 1 H-TC354BE354X354D126p2-4 1 1 H-TC217BC256D126p2-4 1 H-TC315BC236D102p2-4 1 H-TC315BC236D102p2-4 1 H-TC315BC236D102p2-4 1 H-TC315BC236D102p2-4
5 3 5 3 3 5 3 5 3 5 3 5 3 5 3
2 2
4
4
+PWR_SRC +PWR_SRC +3.3V_RUN +PWR_SRC +3.3V_RUN +3.3V_RUN +3.3V_RUN +3.3V_RUN +PWR_SRC +PWR_SRC +1.25V_RUN +PWR_SRC TH24
h-R36X107DR16X87PB DSUB
TH8 TH7
C631 C632 C634 C630 C633 C635 C636 C637 C638 C639 C642 C388 h-tc217bc256d126p2-4 h-tc217bc256d126p2-4
.1U/25V/0603_NC .1U/25V/0603_NC .1U/10V/0402_NC .1U/25V/0603_NC .1U/10V/0402_NC .1U/10V/0402_NC .1U/10V/0402_NC .1U/10V/0402_NC .1U/25V/0603_NC .1U/25V/0603_NC .1U/10V/0402_NC .1U/25V/0603_NC
2
1 1
1
+DC_IN_SS +DC_IN_SS +5V_ALW +5V_ALW +5V_ALW +5V_ALW +5V_ALW +5V_ALW +5V_ALW +5V_ALW +5V_ALW +1.5V_RUN
5 3 5 3
+PWR_SRC +PWR_SRC +PWR_SRC +3.3V_RUN +3.3V_RUN +PWR_SRC +PWR_SRC +PWR_SRC +PWR_SRC +PWR_SRC +1.05V_VCCP +1.05V_VCCP TH25
h-R36X107DR16X87PB
C356 C358 C52 C353 C49 C40 C370 C58 C396 C391 C420 C410
4
.1U/25V/0603_NC .1U/25V/0603_NC .1U/25V/0603_NC .1U/10V/0402_NC .1U/10V/0402_NC .1U/25V/0603_NC .1U/25V/0603_NC .1U/25V/0603_NC .1U/25V/0603_NC .1U/25V/0603_NC .1U/10V/0402_NC .1U/10V/0402_NC
1
+DC_IN_SS +DC_IN_SS +DC_IN_SS +5V_ALW +5V_ALW +5V_ALW +3.3V_RUN +3.3V_RUN +3.3V_RUN +3.3V_RUN +3.3V_RUN +3.3V_RUN
1 1
PV12 PV13 PV14 PV16 PV15 PV9 PV7 PV2 PV8 PV6 PV1 PV5 PV10 PV11 PV3 PV19 PV17 PV18
PAD195X130 PAD195X130 PAD195X130 PAD195X130 PAD195X130 PAD79x130 PAD79x130 PAD79x130 PAD79x130 PAD79x130 PAD79x130 PAD79x130 PAD79x130 PAD79x130 PAD79x130 PAD195X130 PAD195X130 PAD195X130
QUANTA
COMPUTER
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Title
FLASH, RTC & KC
1
1
M-08 0.1

A B C D E
1 2 3 4 5 6 7 8
A A
+3.3V_ALW
TP 44
1
3
+5V_ALW +3.3V_ALW
RP33
4P2R-4.7K
2
4 JTP1
<28> DAT_TP_SIO 1 2 <28> TP_DET# 1
L28 BLM11A601S
2
<28> CLK_TP_SIO 1 2 3
L29 BLM11A601S
M_LED_BK 4
B B
<37> M_LED_BK 5
POWER_ SW_IN0#
<28,34> POWER_ SW_IN0# 6
2
INSTANT_POWER_SW#
<28> INSTANT_POWER_SW# 7
2
2
C245 C244
C247 C248 10P/50V/0402 10P/50V/0402 8
1
10P/50V/0402 10P/50V/0402 9
<28> BC_A_DAT
1
10
11
<28> BC_A_CLK 12
<28> BC_A_INT# 13
<29> LID_CL# 14
15
FOX_HS6115E-M
(Code : 4-1-1)
C C
CIR
+3.3V_ALW
JCIR1
4 4
3 3
2 2 CIRRX <29>
1 1
1
MLX_53398-0471 C335
0.1U/10V/0402
2
D D
QUANTA
Title
COMPUTER
TOUCH PAD, BULE TOOTH & FIR

M-08 0.1

1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
Package 1206 for THD+N INTERNAL SPEAKER AMP Update PN 52

performance for Vista Logo U23
JSPK1
R560 SPEAKER_DET# 1
requirements. AUD_SPK_L1
<11> SPEAKER_DET# 1
2 1 2 2
AUD_LINE_OUT_L C306 1 2 .033U/25V/X7R/1206 LIN- SPKR_LIN+ 3 6 AUD_SPK_L1 AUD_SPK_L2 0_0603 R561 2 1 3
AUD_LINE_OUT_R C307 1 SPKR_RIN+ SPKR_INL OUTL+ 3
2 .033U/25V/X7R/1206 RIN- 2 SPKR_INR OUTL- 7 AUD_SPK_L2 AUD_SPK_R1 0_0603 R562 2 1 4 4
AUD_SPK_R2 0_0603 R563 2 1 5
AUD_HP_OUT_L C326 2 5
1 1uF/25V/X7R/1206 HP_OUT_L 27 20 AUD_SPK_R1 0_0603 6
AUD_HP_OUT_R C329 2 1 1uF/25V/X7R/1206 HP_OUT_R 26
HP_INL
HP_INR
TPA6040A4 OUTR+
OUTR- 19 AUD_SPK_R2 6
2
C334 1U/10V MLX_ 53398-0671
QFN 32PIN HPL
1
C330 C327 C312 C311 1 2 24 16 C620 C621 C622 C623
10/18 Change 2.2u if necessary BIAS AUD_HP_JACK_L <33>
47P/50V_NC 47P/50V_NC 47P/50V_NC 47P/50V_NC AUD_SPK_ENABLE# 23 15 100P/50V_NC 100P/50V_NC 100P/50V_NC 100P/50V_NC
AUD_HP_JACK_R <33>
1
AMP_HP_EN SPKR_EN# HPR
22
2
A
AUD_AMP_MUTE# HP_EN REGEN SPKR_LIN- A
31 <28> AUD_AMP_MUTE# 25 MUTE# REG_EN REGEN 4
SPKR_RIN-
AUD_AMP_GAIN1 31 1 SET
AUD_AMP_GAIN2 GAIN1 SET
32 32 GAIN2
VOUT 29 +VDDA
+5V_SPK_AMP 17 HPVDD L35 +5V_SPK_AMP +VDDA
9 30 VDD
For MAX9789A,depop CPVDD VDD
8
FB_600ohm+-25%_100MHz
PVDD_8 +5V_SPK_AMP
1
R505,pop R506. C328 C616 1 2 1U/16V 10 C1P PVDD_18 18 +5V_SPK_AMP _200mA_0.6ohm DC
+5V_SPK_AMP C318 1U/10V 12 C1N
1
10U/10V 11 28 VDD
2
CPGND GND_28 C617 C323
PGND_5 5
1
10/18 De-pop if not necessary 14 21 1U/10V 1U/10V
2
PVSS PGND_21
1
+5V_SPK_AMP 13 C316 C615 C319
CPVSS
1
R506 1U/10V 1U/10V 0.1U/10V
100K_NC C324 Layout Note:
2
1
R505 C625 1U/16V TPA6040A4 Place close
2
2
0 0.1U/10V U34 Layout Note:
AUDIO_AVDD_ON 1 2 AUD_AMP_MUTE# NC7SZ08P5X_NL +5V_SPK_AMP U22. Place close U22.
2
U36
5
NC7SZ08P5X_NL_NC
5
NB_MUTE# 2
4 AUD_HP_NB_SENSE_R 2 AUDIO_AVDD_ON Layout Note:
AUDIO_AVDD_ON <34> +5V_SPK_AMP +5V_RUN +5V_SPK_AMP
AUD_HP_NB_SENSE 1 4 AMP_HP_EN
Place close to
1
+5V_SPK_AMP CODEC_GPIO_PIN_4 1 C1425/C331 value
R504
need to match with L30 pin 18.
3
0_NC 2 1
3
C326/C290. This BLM21PG600SN1D
2
R545 1 2 0 value be chosen in
1
REGEN Layout Note: C333
B R208 R209 PT phase. C310 C315 C332 C331 0.1U/10V B
Place close to
1
100K 100K +5V_SPK_AMP 1U/10V 10U/10V 1U/10V 10U/10V
2
C619 pin 8.
1
AUD_SPK_ENABLE# 0.033U/16V For MAX9789A,depop
2
1
C619,pop R504. FB_60ohm+-25%_100MHz

_3A_0.05ohm DC
3
R496 R499
AUD_EAPD# 2 100K_NC 100K
For MAX9789A,depop
2
Q25 AUD_AMP_GAIN1 1 2
C614,pop R497. R498
1
2N7002W-7-F AUD_AMP_GAIN2 R501 0_0805

SET 2 1 R207 2 1 0_0603
GAIN1 GAIN2 GAIN +VDDA
2
R189 2 1 0_0603
3
2
R197 R199 0 0 6dB 2.2K_NC R198 2 1 0_0603
2
100K 100K_NC C614 R497 R202 2 1 0_0603
<29> NB_MUTE# 2
0.033U/16V 0_NC
EMI Request
Q24
0 1 10dB
1
1
2N7002W-7-F 1 0 15.6dB
1
1 1 21.6dB
+VDDA Layout Note: R493 +VDDA
ICH_AZ_CODEC_BITCLK AZALIA (HD) CODEC Close to U22 Pin 13. AUD_SENSE_A
5.1K/F
1 2
2
2
R193
1
47_NC U22 10/18 Check package R201 C611
100K R491 R492 1000P/50V
Close to pin 6. ICH_AZ_CODEC_BITCLK 6 13 AUD_SENSE_A 39.2K/F 20K/F
<11> ICH_AZ_CODEC_BITCLK
2 1
2
C
R192 2 HDA_BITCLK SENSE_A C
<11> ICH_AZ_CODEC_SDIN0 1 33 SDIN 8 HDA_SDI_CODEC SENSE_B 34 AUD_SENSE_B
ICH_AZ_CODEC_SDOUT 5
<11> ICH_AZ_CODEC_SDOUT STAC9205 PORT_A_L
3 2
3 2
C305 HDA_SDO AUD_HP_OUT_L
<11> ICH_AZ_CODEC_SYNC 10 HDA_SYNC 39
0.1U/10V_NC 11 41 AUD_HP_OUT_R
<11> ICH_AZ_CODEC_RST#
LQFP 48PIN VREFOUT_A
1
HDA_RST# PORT_A_R AUD_HP_NB_SENSE 2

49 37 <33> AUD_HP_NB_SENSE 2 AUD_MIC_SWITCH <33>
R555 0
AUD_DMIC_CLK 2 0 1 46 21 Q53 Q54
<33> AUD_DMIC_CLK AUD_EXT_MIC_L <33>
1
AUD_DMIC_IN0 DMIC_CLK PORT_B_L 2N7002W-7-F 2N7002W-7-F
<33> AUD_DMIC_IN0 2 1 2 DMIC0/VOL_UP/GPIO1 PORT_B_R 22 AUD_EXT_MIC_R <33>
R556 CODEC_GPIO_PIN_4 4 28
DMIC1/VOL_DN/GPIO2 VREFOUT_B AUD_VREFOUT_B <33>
ICH_AZ_CODEC_SDOUT
For tuning. 23 AUD_MIC_IN_L
PORT_C_L
2
R204 0 AUD_EAPD# 47 24 AUD_MIC_IN_R +VDDA

R195 +3.3V_RUN SPDIF_OUT SPDIF_IN/EAPD#/GPIO0 PORT_C_R
<19> AUD_SPDIF_OUT 2 1 48 SPDIF_OUT VREFOUT_C 29 Close to U22
47_NC +VDDA
1
35 AUD_LINE_OUT_L C300
PORT_D_L
2
Close to pin 5. 43 36 AUD_LINE_OUT_R R196 R194 0.1U/16V

2 1
NC_43 PORT_D_R
2
44 10K 10K 2 1
NC_44
1
C317 C301 C313 R203 R253 45 14

C308 0 100K NC_45 PORT_E_L
15
2
PORT_E_R
5
0.1U/10V_NC 10U/10V_NC 0.1U/10V 1U/10V 31 DOCK_HP_MUTE# C299 R187
1
GPIO4/VREFOUT_E 0.1U/10V 20K

1 1 BEEP <28>
1
DVDD_CORE_1 AUD_PC_BEEP
9 DVDD_CORE_9 PORT_F_L 16 2 1BEEP2 1 2 BEEP1 4
+3.3V_RUN 40 17 2
DVDD_CORE_40 PORT_F_R SPKR <13>
1
3 30 AUD_SPDIF_SHDN
DVDD_IO GPIO3/VREFOUT_F R190
3
2
C643 C309 25 18 +VDDA 10K U21

AUD_DMIC_CLK C325 C321 1000P/50V 0.1U/10V AVDD_25 CD_L 74LVC1G86GW
38 AVDD_38 CD_GND 19
4.7U/10V_NC 0.1U/10V_NC 20
1
2
CD_R
2
2
D 49 37 7 12 AUD_PC_BEEP 10_NC D
C647 DVSS PC_BEEP R200
MONO_OUT 32
4.7P/50V_NC +VDDA Depop R203 & pop C321 & C325 for AD1984. 26
1
AVSS_26 AC97VREFI
42 27
1
AVSS_42 VREFFILT CAP2

33
CAP2 DELL CONFIDENTIAL/PROPRIETARY
1
C314 C304 C320

1
AUD_DMIC_IN0 STAC9205 10U/10V 10U/10V 0.1U/10V_NC

C302 C303 C322 Title
2
0.1U/16V 1U/10V 10U/10V_NC Azelia CODEC(STAC9205))

2
2
2
C648 Size Document Number Rev

4.7P/50V_NC C304 must be 1U & Pop C320 & R200 for AD1984. M-08 0.1
1

1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
Digital Microphone & Camera

R34 2 1 0_0603_NC
Update PN
Q27
+5V_RUN SI2301BDS +3.3V_RUN +3.3V_RUN
1 3 +5V_CCD STEREO MIC
1
A A
LINE IN To Sniffer
1
1
R502 R503
1
C385 R557 C403 C393 100K JAUDIO1 100K
2
1U/10V/0603 100K 1U/10V/0603 10U/10V/0805 SNIFFER2
2
2
1 11
2
2
2 12 SNIFFER1
53
2
3 13
<32> AUD_HP_NB_SENSE 4 14 AUD_MIC_SWITCH <32>
+3.3V_RUN
R564 2 5 15
<32> AUD_HP_JACK_R 1 0_0603 6 16
R565 2 1 0_0603 AUD_EXT_MIC_R <32>
R284 48 L9 +3V_DMIC SNIFFER G_R
10K_0402 BLM11A05 R566 2 7 17
<32> AUD_HP_JACK_L 1 0_0603 8 18
R567 2 1 0_0603 AUD_EXT_MIC_L <32>
1
SNIFFER Y_R
9 19 AUD_VREFOUT_B <32>
C48
10 20
3
10U/10V/0805 53
2
Q26
DTC144EUA FOX_HT1310F
47K 10/19 Update FP
<13> CCD_VDD_ON 2
Place close to Camera connector.
HT1310X-20P-RUV
47K
HEADPHONE
1
LINE OUT
B +3.3V_RUN B
+5V_RUN
1
AUD_DMIC_CLK_R
R509
JCAMERA1 100K
2
<28> AUX_LCD_CBL_DET# 1
C650 +5V_CCD C54 C56 C55 C379 R508 10K
2
+3V_DMIC 2
0.1U/10V_NC .01U/25V/0402 .1U/10V/0402 .1U/10V/0402 150U/6.3V/ESR45
<29> WIRELESS_ON/OFF# 2 1 SNIFFER1
1
ICH_USB_P5+ 3
4
1
ICH_USB_P5-
AUD_DMIC_CLK_R 5 C624
AUD_DMIC_IN0 AUD_DMIC_IN0 6 1U/10V
<32> AUD_DMIC_IN0
2
7
8
<28> INVERTER_CBL_DET# 9
2
49 +3.3V_RUN
<28> LCD_CBL_DET_L 10
C651 +RTC_CELL
0.1U/10V_NC 11
1
12
1
L10 MLX_53398-1271 R335
<12> ICH_USBP5- 1 2 ICH_USB_P5- 100K
<12> ICH_USBP5+ 4 3 ICH_USB_P5+ (Code : 4-1-2)
C51 C45 C44 R334 10K
2
DLW21SN900SQ2B_NC 10U/10V/0805 .1U/10V/0402 .1U/10V/0402
<28> SNIFFER_PWR_SW# 2 1 SNIFFER2
1
R27 0
1 2 C431
1U/10V
2
R26 0 Place close to Camera connector.
1 2
C C
PAID INVERTER_CBL_DET# (Code : 4-1-4)
JCAMERA1 Inverter Camera

Sniffer LED
PIN9 PIN15 PIN1 GND +3.3V_SUS 10 +3.3V_SUS
R206
1 2
SGPIO41
1
0
+3.3V_RUN Q58 Q57
PIN11 DDTA114YUA-7-F DDTA114YUA-7-F
47K 47K
PIN20
2 SNIFFER_YELLOW# <28> 2 SNIFFER_GREEN# <28>
10K 10K
5
U24
1
VCC
3
OE#
LCD_CBL_DET_L (Code : 4-1-3) AUD_DMIC_CLK 2 4 AUD_DMIC_CLK_R SNIFFER Y_R SNIFFER G_R
<32> AUD_DMIC_CLK IN OUT
2 1 3 GND
JCAMERA1 Inverter LVDS R205
D 10K_NC SN74LVC1G125DBVR_NC D
PIN10 PIN17
SGPIO40 DELL CONFIDENTIAL/PROPRIETARY

PIN3 +5V_ALW Title
PIN7 AUDIO CONN

M-08 0.1

1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
+3.3V_RUN
2
REM_DIODE1_N REM_DIODE3_N REM_DIODE4_N
R163
1
10K
1
C545 2 Q14 C543 2 Q17 C542 2 Q34
1
2200P/50V MMST3904 C194 2200P/50V MMST3904 C256 2200P/50V MMST3904 C441
FAN1_TACH <28>
2200P/50V_NC 2200P/50V_NC 2200P/50V_NC
2
2 R162 REM_DIODE1_P REM_DIODE3_P REM_DIODE4_P
0
A
Put C545 close to Guardian. Put C543 close to Guardian. Put C542 close to Guardian. A
D13 JFAN1 Put C194 close to Diode Put C256 close to Diode Put C441 close to Diode
1
CHN202UPT_NC FAN1_VOUT
FAN1_VOUT_FB 1
2
3
3 Place under CPU Place under DIMM ( TOP ) Place under Minicard ( BOT )
1
MLX_53398-0371
C255 Put C546 close to
22U/10V Guardian. U31
2
1
<3> H_THERMDA <28> THRM_SMBDAT 11 SMDATA VCP1 43 PWR_MON <45>

12 46 VCP2
<28> THRM_SMBCLK SMBCLK EMC 4001 VCP2
2
REM_DIODE1_P 38 45 REM_DIODE3_P
C546 REM_DIODE1_N 37
DP1
DN1
QFN PIN48 DP3
DN3 44 REM_DIODE3_N
+RTC_CELL +3.3V_ALW +3.3V_SUS
470P/50V
1
REM_DIODE5_N H_THERMDA 41 48 REM_DIODE4_P
DP2 DP4
2
H_THERMDC 40 47 REM_DIODE4_N
<3> H_THERMDC DN2 DN4
1
2
1
C553 2 Q38 2 REM_DIODE5_P R435 R439 R440

2200P/50V MMST3904 C573 +3VSUS_THRM DP5 REM_DIODE5_N 10K_NC 10K 10K
35 3V_SUS DN5 1
2200P/50V_NC
2
1
+RTC_CELL 21
1
REM_DIODE5_P RTC_PWR3V
ATF_INT# 20 ATF_INT# <29>
R436 1 2 1K THERM_PWRGO 23 3
<38> SUSPWROK VSUS_PWRGD POWER_SW# POWER_ SW_IN0# <28,31>
Put C553 close to Guardian. R433 1 2 1K +3V_PWROK# 16 4
<38> ICH_PWRGD# 3V_PWROK# ACAVAIL_CLR ACAV_IN <18,28,40>
Put C573 close to Diode THERMTRIP_SIO 25 THERMTRIP_SIO
SYS_SHDN# 24 THERM_STP# <44>
Place under DIMM ( BOT ) THERMATRIP1# 17 R432 7.5K/F
THERMATRIP2# THERMTRIP1# LDO_SHDN#_ADDR
B 18 THERMTRIP2# LDO_SHDN#/ADDR 27 2 1 +3.3V_SUS B
THERMATRIP3# 19 THERMTRIP3#
LDO_POK 33 2.5V_RUN_PWRGD <38>
R420 THERM_VEST 42
49.9/F R434 1 VSET THERM_LDO_SET
2 1K 26 XEN LDO_SET 28
1 2 +3VSUS_THRM +RTC_CELL 34
+3.3V_SUS VSS
LDO_OUT 32 +2.5V_RUN
LDO_OUT 31
1
C571 FAN1_VOUT 7
C551 0.1U/10V FAN_OUT_1 THERM_LDO_IN
8 FAN_OUT_2 LDO_IN 30
0.1U/10V +3.3V_SUS R429 2 1 10K_NC 29
2
R431 2 LDO_IN
1 10K_NC T104 PAD 39 FAN_DAC1
<26> MDC_RST_DIS# 10 GPIO1

<18> SIO_GFX_PWR 13 GPIO2 VDD_3V 9 +3.3V_RUN
5V_CAL_SIO1# 14
5V_CAL_SIO2# GPIO3
15 GPIO4 VDD_5V_1 5 +5V_RUN
<32> AUDIO_AVDD_ON 22 GPIO5 VDD_5V_2 6
+3.3V_SUS 36 GPIO6/FAN_DAC2
EMC4001
1
C569 needs to be placed

near Guardian IC. R437
8.2K
Placement should be near the WWAN minicard

2
THERMATRIP1# connector just under the inserted minicard. +2.5V_RUN

3
R445 2.2K Q37 C569 +5V_SUS +3.3V_SUS 20
1
C C
+1.05V_VCCP 1 2 THERM_B1 2 MMST3904 0.1U/10V
2
2
Thermistor P/N: R427
1
C568 needs to be placed R323 R298 Voltage margining 31.6K/F_NC

<3> H_THERMTRIP#
+3.3V_SUS 2.2K/F TH11-3H103FT 10K
near Guardian IC. circuit for LDO
2
THERM_LDO_SET
+3.3V_RUN R312 10K/F_0603 output.For Vmargin
1
1
1
VCP2 1 2 stuff R592 and
R442 R113=30K. R113=1K for 0603 R430
3
+3.3V_SUS 8.2K 0603 1K
5V_CAL_SIO1# production. package.
47 package. 2
1
C540
2
2
1
C570 needs to be placed R441 R443 THERMATRIP3# 2200P/50V Q32
1
near Guardian IC. R438 8.2K 2.2K 2N7002W-7-F
8.2K
3
Q35 C568
2
THERM_B32 MMST3904 0.1U/10V

2
THERMATRIP2# R428 0/1210

2
1/2 THERM_LDO_IN 1 2 +3.3V_RUN

1
+3.3V_RUN Layout Note:

<18> THERMATRIP_VGA#
3
R444 2.2K Q36 C570 Place those capacitors This Value of

+1.05V_VCCP 1 2 THERM_B2 2 MMST3904 0.1U/10V R428 can be 0.27
close to EMC4001.
1
C566 C565
2
or 0 ohm
1
1 0.1U/10V 1U/10V
1
<6> THERMTRIP_MCH#
C567 C562 and the package
2
0.1U/10V 10U/10V is 1210.
2
10/18 Check POP or Non-pop +3.3V_SUS

D D
R418 332K/F
1 2 THERM_VEST Note: +5V_RUN +2.5V_RUN
VSET = (Tp-70)/21, where
1
Tp = 70 to 101 degrees C. DELL CONFIDENTIAL/PROPRIETARY

1
1
C535 R419 C544 Tp set at 88 degrees C.
0.1U_10V 118K/F 2200P_50V Guardian temp tolerance = C561 C556 C558 C554
2
0.1U/10V 10U/10V 0.1U/10V_NC 10U/4V_NC Title

+-3 degrees C.
2
2
FAN & THERMAL

M-08 0.1

1 2 3 4 5 6 7 8
A B C D E
Refer to M07_LOM4401_X06
schematic.
+3.3V_LAN
38 38 38 38 +1.8V_LOM
38 38 38
+3.3V_LAN
38
+3.3V_SUS +3.3V_LAN
1
1 1
C646 C35 C36 C18 C39 C30 C28 C38 C14 C15 C16 C645 C41 C350 C351 C21 C25 C354 C34 C37 C26 C27 C13
1000P/50V/0402 4.7U/10V/08054.7U/10V/0805 47P/50V/0402 .1U/10V/0402 47P/50V/0402 .1U/10V/0402 1000P/50V/0402 .1U/10V/0402 .1U/10V/0402 47P/50V/0402 47P/50V/0402 .1U/10V/0402 .1U/10V/0402 1000P/50V/0402 1000P/50V/0402 47P/50V/0402 47P/50V/0402 47P/50V/0402 47P/50V/0402 .1U/10V/0402 47P/50V/0402 4.7U/10V/0805 1 2
2
R18 0_0805
Close to power pins Place C1284 close to pin65

Refer to M07_LOM4401_X06 schematic.
Refer to M07_LOM4401_X06 schematic. 0.1U*13 pcs EMI requirement on 0812 '+3VLAN should be sourced from
+3VSUS instead of +3VSRC since WOL
These three pin is not supported on C/G.
LINK_LED10#,
LINK_LED100#,
ACT_LED are
open-drain type.
+3.3V_LAN +1.8V_LOM
+3.3V_LAN
2
114
115
125
106
112
R221 R223 R222
25
56
19
30
40
52
79
94
65
96
97
91
92
17
44
U5
7
10K_NC 10K_NC 10K_NC
Place R219, C640, C347 close to pin69
VDDCORE
VDDCORE
VDDCORE
VESD
VESD
VESD
XTAL_AVDD
REGULATOR_AVDD
REGULATOR_AVDD
VDDIO_PCI
VDDIO_PCI
VDDIO_PCI
VDDIO_PCI
VDDIO_PCI
VDDIO_PCI
VDDIO_PCI
VDDIO
VDDIO
VDDIO
REGULATOR_VOUT1
REGULATOR_VOUT2
1
2 +3.3V_LAN 2
<12,20> PCI_AD[31..0]
PCI_AD31 122 75 1 2
PCI_AD31 LINK_LED10# LINK_LED10# <36>
PCI_AD30 123 76 R219 38
PCI_AD30 LINK_LED100# LINK_LED100# <36>
PCI_AD29 124 77 BK2125LM152
PCI_AD29 ACT_LED# ACTLED# <36>
1
PCI_AD28 126 78
PCI_AD28 COL_LED# T2
PCI_AD27 127 C640 C347 C346
PCI_AD26 PCI_AD27 47P/50V/0402 .1U/10V/0402 .1U/10V/0402
128
2
PCI_AD25 PCI_AD26 +1.8V_LOM
1 PCI_AD25
PCI_AD24 3 69 +3.3V_LAN_BIAS_AVDD
PCI_AD23 PCI_AD24 EPHY_BIAS_AVDD
6 PCI_AD23
PCI_AD22 8 57 +1.8V_LOM_EPHY_AVDD 1 2
PCI_AD21 PCI_AD22 EPHY_AVDD L66
9 PCI_AD21
PCI_AD20 10 64 +1.8V_LOM_PLLVDD L7 +1.8V_LOM BK2125LM152
PCI_AD20 EPHY_PLLVDD
1
PCI_AD19 11 BK2125LM152
PCI_AD18 PCI_AD19 C644 C29 Place L66, C29, C644
14 PCI_AD18
1
PCI_AD17 15 Place R942 47P/50V/0402 .1U/10V/0402 close to pin57.
2
PCI_AD16 PCI_AD17 C23 C22
16 PCI_AD16 EPHY_VREF 71 close to U62
PCI_AD15 33 72 47P/50V/0402 2.2U/6.3V/0603
2
PCI_AD14 PCI_AD15 RDAC R220 1.27K/F_0402 Place L7, C22, C23
34 PCI_AD14 EPHY_TESTMODE 88
PCI_AD13 36 close to pin64.
PCI_AD12 PCI_AD13
37 PCI_AD12 EPHY_TDP 62 LOM_TX+ <36>
PCI_AD11 38 61
PCI_AD11 EPHY_TDN LOM_TX- <36>
PCI_AD10 39 59
PCI_AD10 EPHY_RDP LOM_RX+ <36>
PCI_AD9 41 60
PCI_AD9 EPHY_RDN LOM_RX- <36>
PCI_AD8 42
PCI_AD7 PCI_AD8
45 PCI_AD7 NC 104
PCI_AD6 48 105 Resistors must be rated at least
PCI_AD6 VSS
1
PCI_AD5 49 103 1/16W. Place termination
PCI_AD4 PCI_AD5 NC
50 PCI_AD4 NC 108 resistors close to the ASIC.
PCI_AD3 51 102 R13 R16 R12 R11
PCI_AD2 PCI_AD3 NC 49.9/F_0402 49.9/F_0402 49.9/F_0402 49.9/F_0402
53 PCI_AD2 NC 109
3 PCI_AD1 54 110 +3.3V_LAN 3
2
PCI_AD0 PCI_AD1 NC
55 PCI_AD0 NC 107
1
<12,20> PCI_C_BE3# 4 PCI_CBE_L3 GPIO2/VAUXAVAIL 87 2 1
18 86 R217 1K_0402 C348 C24
<12,20> PCI_C_BE2# PCI_CBE_L2 GPIO1 T3
32 85 .1U/10V/0402 .1U/10V/0402
<12,20> PCI_C_BE1# T1
2
PCI_CBE_L1 GPIO0 Delete R630&R631 +3.3V_LAN
<12,20> PCI_C_BE0# 43 PCI_CBE_L0
20 90 per 4401 ref
<12,20> PCI_FRAME# PCI_FRAME_L BOOTROM_SCL T45 schematic
<12,20> PCI_IRDY# 21 PCI_IRDY_L BOOTROM_SDA 93 T46
23 U2
<12,20> PCI_TRDY# PCI_TRDY_L
26 98 SPROM_CS 1 8
<12,20> PCI_DEVSEL# PCI_DEVSEL_L SPROM_CS CS VCC
1
27 95 SPROM_CLK 2 7 C641
<12,20> PCI_STOP# PCI_STOP_L SPROM_CLK SK NC
28 101 SPROM_DOUT 3 6 C2 47P/50V/0402
<12,20> PCI_PERR# PCI_PERR_L SPROM_DOUT DI ORG
29 99 SPROM_DIN 4 5 .1U/10V/0402 Note: BCM4401 requires
<12,20> PCI_SERR#
2
PCI_SERR_L SPROM_DIN DO GND
<12,20> PCI_PAR 31 PCI_PAR
<12> PCI_PIRQB# 116 M93C46-WDW6TP 16-bit R/W data width
PCI_INT_L
EXT_POR_L 89 LOM_LOW_PWR# <29>
<12,20> PCI_RST# 117 PCI_RST_L
<17> CLK_PCI_LOM 118 PCI_CLK JTAG_TDP 83 T47 Note: The BCM4401 has weak internal pulldown resistors on
<12> PCI_GNT0# 119 80 Note: EXT_POR_L has a internl pull up.
PCI_GNT_L JTAG_TCK the following signals:
<12> PCI_REQ0# 121 PCI_REQ_L JTAG_TDI 82 T54
R17
<20,29> SYS_PME#
PCI_AD16 1 PCI_IDSEL
113 PCI_PME_L JTAG_TRST_L 73 SPROM_CS, SPROM_CLK, SPROM_DOUT, SPROM_DIN.
2 5 PCI_IDSEL JTAG_TMS 81 T57
33 R19 100_0402 22
<13,20,28> CLKRUN# PCI_CLKRUN_L
Place R17, C33
EPHY_BIAS_AVSS
close to U62.118 67 XTAL_IN

1
EPHY_PLLGND
EPHY_AGND
C33 66
XTAL_AVSS
6P/50V XTAL_OUT
2
Refer to M07_LOM4401_X06 schematic.

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
1
R489 and R490 removed from

4 4
schematic because of Bios can
R10 BCM4401KQLG
configure the state of CLKRUN#
12
46
111
100
84
2
24
74
13
47
120
35
68
70
58
63
800_0402
signal. Y1 BCM4401 B0
2
25MHz
XI 2 1 XO QUANTA
COMPUTER
1
C19 C20 Title

27P/50V/0402 27P/50V/0402 LAN (BCM4401)
2

FM1 0.1

A B C D E
A B C D E
4 4
2 1 CON1
<35> LINK_LED10#
R226 150_0402 TYCO_1368458-1
17 GREEN
<35> LINK_LED100# 2 1 15 ORANGE
+3.3V_LAN R225 150_0402
L67
G
O
BK2125LM152 16 COMMON
<35> LOM_TX+ 11 TRD1+/TX

12 TRCT1/TX
<35> LOM_TX- 10 TRD1-/TX
<35> LOM_RX+ 4 TRD2+/RX

3 3
6 TRCT2/RX
<35> LOM_RX- 5 TRD2-/RX
14 LED2_YP
Removed EMI bead(L40-43) 13 LED2_YN Y
and ESD protect IC(U33)
1 1
2 2
38 3 3
7 7
8
MGND
MGND
Place close 8
9 9
to CON1.6 &
Place close CON1.12.
to CON1.6. C364 C366
18
19
.1U/10V/0402 47P/50V/0402
<35> ACTLED# 1 2
R224 150_0402
2 2
1 1
QUANTA
Title
COMPUTER
LAN Jack

FM1 0.1

A B C D E
A B C D E
+3.3V_ALW +5V_SUS +5V_RUN 24

HDD activity LED. Power & Sus
1
R527 R528 +5V_SUS
1
10K 100K Q1
1
R46 DDTA114YUA-7-F
24 100K_NC
21
5
U7 D3
47K
R30 330 19-21/BHC-YL1M1RY/3T R40 0
2
1 3 2 4 BREATH_PWRLED 1 2 RBREATH_PWR_LED 2 1 2 12
1 <28> BREATH_LED# <11> SATA_ACT# 1
Q63 10K
2N7002W-7-F
7SH04 BEBL0031Z11 D4
3
R36 220 19-21/BHC-YL1M1RY/3T
3
10/31 PSL issue 54 LED19-21VGC-TR8 HDD_LED 1 2RHDD_LED 2 1
+5V_RUN
+3.3V_ALW
Battery status. WLAN
2
+3.3V_RUN
1
+3.3V_ALW R64 54
Q4 +3.3V_WLAN 330
1
DDTA114YUA-7-F
47K
R541
2 1
1
1
<28> BAT2_LED# 2 0
Q3 54 10K R553 24
DDTA114YUA-7-F 24 D5 BLUE 47K_0402 D6
2
47K
330 R50 19-21/BHC-YL1M1RY/3T
2 BAT1_LED_R# 3 1 RBAT1_LED 2 1 +5V_ALW R542
BAT1_LED# <28>
1
10K 10K_0402
220 R51 2 1 2 Q5
<24> LED_WLAN_OUT#
3 1
3 4 2 RBAT2_LED 2 1 BAT2_LED MMBT3906_NL
Q67
3
3
DTC144EUA Q65
BAT1_LED 47K 19-22UYOSUBC
2 DTC144EUA
47K
9/20 Change FP 2
47K
47K
2 2
1
1
+3.3V_RUN +5V_RUN +5V_RUN
Media BD
BT
1
R522
1
24 100K_NC
R523 24
47K
1
100K Q7
2
BT_ACTIVE# 2 DTA114YUA +3.3V_RUN +5V_RUN
10K
2
LED_WPAN# 2
<24> LED_WPAN#
Q60
BT_LED
3
2
SI2301BDS
3
2N7002W-7-F
1
BT_ACTIVE 2 R546
Q59 4.7K_0402_NC
3
2
1
47K
1
2 Q61 R521 Q16
1
2N7002W-7-F 100K_NC R75 M_LED_BK# 1 3 2 DTA114YUA
<29> M_LED_BK#
54 330 10K
BT_MASK 1
1
Q76
2
R524 2N7002W-7-F
2BT_LED_R 2
100K
3
M_LED_BK_L
M_LED_BK <31>
R159 0_0805
2
2 R525
3 <11,29> LED_MASK# 3
0_NC D8
Q62 19-21/BHC-YL1M1RY/3T
1
2N7002W-7-F
1
This circuit is only needed if

R526 2 1 0_NC
the platform has the SNIFFER.
+3.3V_RUN 25
R336 10K 19
1 2 BT_ACTIVE
5
19 U35
12/26 COEX1_BT_ACTIVE_DC 2
1
4 COEX1_BT_ACTIVE
COEX1_BT_ACTIVE <24>
Q13 2 LED_MASK# COEX1_BT_ACTIVE_MINI 1
Bluetooth MMBT3906_NL_NC
LED_MASK# <11,29> <24> COEX1_BT_ACTIVE_MINI
+3.3V_RUN 7SH32
3
R559 2 1 0_NC
J1
1 GND Activity LED 2 51
4
3 3.3V(Logic) COEX2 4 COEX2_WLAN_ACTIVE <24> 16 4
5 6 COEX1_BT_ACTIVE_DC
<29> BT_RADIO_DIS_DC# Radio Enable/Disable# COEX1
7 8 USBP7_D-
PAD T28 RSVD USB-
USBP7_D+ 9 10 L40
USB+ GND USBP7_D+ 1 2 ICH_USBP7+ <12>
TYC_1566995-1 USBP7_D- 4 3 ICH_USBP7- <12>
QUANTA
2
2
1
R108 R123 DLW21SN900SQ2B_NC

C190
0.1U/10V
C195
100P/50V
10K 10K C193
33P/50V R512 0
Layout Note:
R512 and R513 COMPUTER
2
1 2 Title
1
close to choke SWITCH & LED

R513 0 as possible to
1 2 Size Document Number Rev
minimize stubs. FM1 0.1

A B C D E
1 2 3 4 5 6 7 8
Non-iAMT
R460 1 2 0
<42> 1.25V_RUN_PWRGD
+3.3V_RUN +3.3V_SUS
1
R462 1 2 0
<43> 1.5V_RUN_PWRGD
2
R461 1 2 0
<43> 1.05V_RUN_PWRGD
R467 1 2 0_NC R148
<34> 2.5V_RUN_PWRGD
R463 1 2 0_NC R154 100K
<18> GFX_PWRGD
9/20 Depop R463 2.2K_NC
2
A A
+5V_RUN +5V_ALW
ICH_PWRGD# <34>
3
D33
SDMK0340L-7-F 2 Q15
1
R471 10K 2N7002W-7-F
2 1 1 2 2 Q49
1
MMBT3906_NL
1
3
1
3
R472 4.7K Q50 U17D
C601 R473 C600 1 2 2 MMST3904 12
<13,28,45> IMVP_PWRGD
0.1U/10V 200K 2200P/50V 11 ICH_PWRGD <6,13>
2
<28> RESET_OUT# 13
2
1
74AHC08PW
+1.8V_RUN +1.8V_SUS
D32 1
SDMK0340L-7-F_NC R468 10K_NC Keep Away from high speed buses
2 1 1 2 2 Q45
MMBT3906_NL_NC
1
+3.3V_SUS +3.3V_ALW +3.3V_ALW +3.3V_ALW

3
1
3
R466 4.7K_NC Q47
C598 R469 C599 1 2 2 MMST3904_NC
1
0.1U/10V_NC 200K_NC 2200P/50V_NC C212 0.1U/10V
2
9/20 Depop Q47 R137 1 2

2
1
20K
5
+3.3V_RUN +3.3V_ALW U18A U18B
2
B C200 0.1U/10V B
1 6 3 4 1 2
D31
1
SDMK0340L-7-F R453 10K
1
Q43 C223 NC7WZ14P6X_NL NC7WZ14P6X_NL
14
2 1 1 2 2
MMBT3906_NL 0.01U/25V U17A
1
1
3
2
1
R464 4.7K Q46 R151 0 3

C590 R454 C589 1 2 2 MMST3904 1 2 2
200K 2200P/50V <18,28,39> RUN_ON
0.1U/10V
2
74AHC08PW
2
U17B
4
5V_3V_1.8V_1.25V_RUN_PWRGD <29> 6 RUNPWROK <18,28,29,45>
5
74AHC08PW
U17C
<28,39> SUS_ON 10
8 SUSPWROK <34>
9
74AHC08PW
13
12
C C
+3.3V_SUS +3.3V_ALW +3.3V_ALW
C293
D17 0.1U/10V
1
SDMK0340L-7-F R183 10K 1 2

2 1 1 2 2 Q22
MMBT3906_NL
1
D16 U20
3
1
SDMK0340L-7-F
1
C291 R182 C292 2 1 2 4

0.1U/10V 200K 2200P/50V
2
1
2
NC7SZ14P5X_NL
R181
200K
2
+5V_SUS +5V_ALW
D14
1
SDMK0340L-7-F R178 10K

2 1 1 2 2 Q21
MMBT3906_NL
1
D15
3
1
SDMK0340L-7-F
1
D C289 R179 C290 2 1 D

0.1U/10V 200K 2200P/50V
2
1
2
R177
200K
R180
200K
QUANTA
COMPUTER
2
Title
System Reset Circuit

M-08 0.1

1 2 3 4 5 6 7 8
1 2 3 4 5
+3.3V_ALW2 +5V_ALW2 +15V_ALW +5V_ALW +5V_RUN

PQ39
SI4800BDY-T1-E3
8 3
1
7 2
PR189 PR184 PR183 6 1
2
100K_0402 100K_0402_NC 100K_0402 5 +3.3V_ALW2 +5V_ALW2 +15V_ALW +3.3V_ALW +3.3V_SUS
1
PC179 PR182 PQ17
10U/25V/1206 20K_0402 SI4800BDY-T1-E3
4
RUN_ENABLE 8 3
1
A A
7 2
1
3
PR193 PR61 PR63 6 1
RUN_ON_5V# 5 100K_0402 100K_0402_NC 100K_0402 5
2
PQ40A PC62
1
2N7002DW PC180 10U/6.3V/1206 PR60
4
2 4700P/50V/0603 SUS_3.3V_ENABLE 20K_0402
<18,28,38> RUN_ON
2
PQ40B
3
2N7002DW
1
SUS_ON_3.3V# 5
PQ18A
1
2N7002DW
1
2 PC63 PR62
<28> 3.3V_SUS_ON
PQ18B 4700P/50V/0603 100K_0402_NC
2N7002DW
2
+3.3V_ALW2 +5V_ALW2 +15V_ALW +1.8V_SUS +1.8V_RUN +5V_ALW +5V_SUS
PQ13 PQ27
SI4800BDY_NC +3.3V_ALW2 +5V_ALW2 +15V_ALW SI4800BDY-T1-E3
8 3 8 3
7 2 7 2
1
1
6 1 6 1
2
PR190 PR55 PR53 5 PR192 PR88 PR87 5
2
100K_0402_NC 100K_0402_NC 100K_0402_NC PC56 PR52 100K_0402 100K_0402_NC 100K_0402
1
PD5 10U/6.3V/0603_NC 20K_0402_NC PC91 PR85
4
CH751H-40HPT_NC 10U/6.3V/1206 20K_0402
2
2
1 2 SUS_5V_ENABLE
1
3
3
B PR54 B
1
5 0_0402_NC SUS_ON_5V# 5
PQ14A 1 2 PC55 PQ26A
6
1
2N7002DW_NC .047U/25V 2N7002DW
4
1
2 2 PC92 PR86
<28> 1.8V_RUN_ON <28,38> SUS_ON
PQ14B PQ26B 4700P/50V/0603 100K_0402_NC
2N7002DW_NC 2N7002DW
1
2
+3.3V_ALW2 +5V_ALW2 +15V_ALW +3.3V_ALW +3.3V_RUN
PQ15
PHK12NQ03LT Reserve discharge path
8 3 +1.8V_SUS +5V_SUS +3.3V_SUS
7 2
1
6 1
1
PR191 PR56 PR59 5
1
100K_0402 100K_0402_NC 100K_0402 PC57 PR57 R172 R176 R175
PD6 10U/6.3V/1206 20K_0402 30/F_0402_NC 1K_0402_NC 1K_0402_NC
CH751H-40HPT_NC 4
2
2
1 2
3 2
3 2
3 2
3
PR58
5 0_0402 1 SUS_ON_5V# 2 2 2
PQ16A 1 2 PC58
6
C C
2N7002DW 30 Q18 Q20 Q19
4
1
2 6800P/50V/0402 2N7002W-7-F_NC 2N7002W-7-F_NC 2N7002W-7-F_NC
<28> 3.3V_RUN_ON
PQ16B
2N7002DW
1
Inrush curreunt : 5.4 A
Reserve discharge path

+5V_RUN +3.3V_RUN +1.8V_RUN +1.5V_RUN +0.9V_DDR_VTT +1.25V_RUN
1
R458 R457 R470 R456 R455 R465

1K_0402_NC 10_0402_NC 1K_0402_NC 1K_0402_NC 1K_0402_NC 1K_0402_NC
3 2
3 2
3 2
3 2
3 2
3 2
RUN_ON_5V# 2 2 2 2 2 2
Q42 Q41 Q44 Q40 Q39 Q48

1
2N7002W-7-F_NC 2N7002W-7-F_NC 2N7002W-7-F_NC 2N7002W-7-F_NC 2N7002W-7-F_NC 2N7002W-7-F_NC

D D
QUANTA
Title
COMPUTER
RUN POWER SW

M-08 0.1

1 2 3 4 5
A B C D E
Id=9.6A@Vgs=10V
+PWR_SRC PQ32
SI4835BDY-T1-E3
1 8
2 7
PQ2 3 6
SI4835BDY-T1-E3 CHGR_IN 5
PR33 FL5
8 1 .01/F_2512 FBMH3225HM202NT
1 4
+DC_IN_SS +DC_IN_SS 7 2 1 2 1 2 +DC_IN_SS
6 3
5 PR117
1
PC29 PC30
1 470K_0402 1
4
PR36 2200P/50V0402 .1U/50V/0603
2
PR40 100K_0402
1 2 2 1
10K_0402
CSSP
3
2
PQ5
1
2N7002W-7-F
CSSN
+DC_IN_SS
Max Charging current setting
LDO 4.7A
2
PD10 +5V_ALW
1
SDM10K45
1
PC28 PC31 PC102 PC32
2
PR123 PC110
1
365K/F_0402 PR119 0_0603 2200P/50V0402 .1U/50V/0603 10U/25V/1206 10U/25V/1206
28
27
2
1
1U/25V/0805 PD11
2
PR122 SDM10K45_NC
CSSP
GND
CSSN
LDO 49.9K/F_0402 22 PC43 1U/10V/0603
1
DCIN LDO
2 1 2 1
1
1
2 1 8731_ACIN 2 25 BST RDS(ON)=30m ohm
ACIN BST
5
6
7
8
2 PR50 PR120 PC100 2
1
10K/F_0402 PC114 .01U/25V/0402 33/F_0603 .1U/50V/0603 PQ3 PR104
21 4 SI4800BDY-T1-E3 1K_0402_NC
2
LDO
<18,28,34> ACAV_IN 13
2
ACOK PC109 PL1 PR32 +VCHGR_1 FL6
VCC 26 2 1
1
+3.3V_ALW 11 3300P/50V/0402 5.8UH 30% 5.5A 24m(SIL104R-5R8PF) .01/F_2512 HI1206T161R-10
1
2
3
VDD DHI PC115 1U/10V/0603
DHI 24 1 2 2 1CHG_CS1 2 1 2 +VCHGR <41>
PR51 1 2
5
6
7
8
1
15.8K/F_0402 MAX8731AETI+LX 23 LX PR121
4
PC137 .1U/50V/0603 1_0603
2
1
10 20 DLO 4 PR110 PC89 PC196 PC195 PC8 PC20 PC17
<28,41> PBAT_SMBCLK SCL DLO
1
3300P/50V/0603
1000P/50V/0402
9 3.8_0805_NC PC187
<28,41> PBAT_SMBDAT SDA
10U/25V/1206/X5R
10U/25V/1206/X5R
10U/25V/1206/X5R
14 19 RDS(ON)=20m
2 2
2
BATSEL PGND
.1U/50V/0603
SMBUS Address 12 GNDA_CHG 2200P/50V0402
1
2
3
2
IINP 8 IINP CSIP 18 ohm PQ4
12H
Adress :
SI4810BDY-T1-E3 PC101
17 1000P/50V/0402_NC
1
CSIN 10/4 EMI request
6 CCV
PR133 PR137 CSIP
2
10K_0402 5 CCI FBSA 15 2 1+VCHGR

CSIN
FBSB 16
2
4 100_0402
CCS PC108
GND
DAC
1
PC139 3 220P/50V/0402
TABLE 1
1
REF
1
1
.1U/10V/0402
PR144 PC45 PC131 PC127

1 7
12
8.45K_0402 8731REF PU7

1
.01U/25V/0402
.01U/25V/0402
.01U/25V/0402
PC126
TRIP CURRENT
2
PC133
ADAPTER(W) PR38 PR35 PR39 **PR34
2
1U/10V/0603
3 .1U/10V/0402 3
(A)
2
PR143 0_0603
65 3.17 57.6K 13K 105 N/A

GNDA_CHG
90 4.43 51.1K 17.8K 348 33.2K
+3.3V_ALW 130 6.43 32.4K 20.5K 100 27.4K

150 7.43 30.9K 24.9K 432 88.7K
1
+5V_ALW
+5V_ALW PR45
200 9.75 19.1K 28K 301 36.5K
1
100K_0402 11.28
PR41 PC50
230 (see note3) 32.4K 6.49K 115 N/A
1
PR38 1M/F_0402 PC53 100P/50V/0402

2
1
51.1K/F_0402 ADAPT_OC <29>

SEE TABLE 1 SEE TABLE 1 .01U/25V/0402 PR49 Note 1: PR34 is popluated if ADAPT_TRIP_SEL is used to program for
2
100K_0402
the next lower adapter.
3
PU4A ADAPT_TRIP_SET is floating for the higher adaptor,

2
8
SEE TABLE 1 LM393DR2G 1

1 2 3 PR43 grounded for the lower adaptor.
<29> ADAPT_TRIP_SEL
PR34 33.2K/F_0402 1 2 PQ6 1K_0402_NC
1 2 2 2N7002W-7-F Note 2: 24.9K at PR34 allows the 65W adaptor seetting to switch
0_0402PR188
0_0402PR188
2
down to 45W.
1
PC25
4
1
.01U/25V/0402
1
4 PR35 PC51 PC44 4

Note 3: PR33 must be 5mOhms instead of 10mOhms for the 230W adaptor.
1
17.8K/F_0402 PC22 100P/50V/0402 .1U/10V/0402_NC

2
SEE TABLE 1 100P/50V/0402

2
QUANTA
1
PC52
.01U/25V/0402
PR39
348/F_0402
SEE TABLE 1 For GPRS immunity place as close to Title
COMPUTER
2
CHARGER
the IC as possible
GNDA_CHG Size Document Number Rev
FM5 0.1

A B C D E
A B C D E
+3.3V_ALW
PD4 PD3 PD2
2
DA204U_NC DA204U_NC DA204U_NC PD1
DA204U_NC
PC7 2200P/50V0402
1 2 +3.3V_ALW
3
1 1
PC11 .1U/50V/0603
1 2 +VCHGR <40>
1
PR8
JABT1 10K_0402
1 RP2 SMBUS Address 16
BATT1+ 4P2R-100
2
Adress : 16H
2
BATT2+
SMB_CLK 3 1 2 PBAT_SMBCLK <28,40>
SMB_DAT 4 3 4 PBAT_SMBDAT <28,40>
BATT_PRES# 5
SYSPRES# 6 1 2 PBAT_PRES# <29>
BAT_ALERT 7 3 4 PBAT_ALARM#
BATT1- 8
9 RP1
BATT2- 4P2R-100
SUY_200185MR009S509ZL +5V_ALW
+3.3V_ALW
2
PD9
DA204U
1
PR92
2.2K_0402
3
PQ28
2
2N7002W-7-F
PR91
DOCK_PSID 3 1 1 2 PS_ID <28>
2 2
100_0402
2
PR90 +5V_ALW +5V_ALW
100K/F_0402
2
2
1
2
D18 PR93 PD8
DA204U
3
SSM24PT_NC 10K_0402
2
3
1 2 PS_ID_DISABLE# <29>
1
1
PQ29
PR89 MMST3904-7-F PR94 100_0402_NC
15K/F_0402
2
PL11
1 2 DOCK_PSID
BLM11B102S
3
Change Value per GG updated 3
EMI requirement on 0812
JDCIN1 PQ1
FOXCONN_JPD113D-509-TR +DC_IN SI4835BDY-T1-E3 +DC_IN_SS
1 FL2
BLM41PG600SN1L 1 8
2 +DCIN_JACK 1 2 2 7
1 2 3 6
1
1
3 BLM41PG600SN1L 5 1 PC3
1
FL1 PC1 +
1
PC4 PR2 PC5 PC2
10U/25V/1206
9
8
7
6
5
4
-DCIN_JACK .1U/50V/0603 PR95 10K/F_0603

2
2
3
240K_0402 .1U/50V/0603 .1U/50V/0603 .1U/50V/0603

1
2
2
RV2 RV1 PC95

1
VZ0603M260AGT_NC VZ0603M260AGT_NC .47U/25V/0805

2
PQ30
<28> AC_OFF
2
IMD2A_NC
PR1
47K_0402
1
4 4
QUANTA
Title
COMPUTER
DCIN,BATT CONNECTOR

FM5 0.1

A B C D E
5 4 3 2 1
+PWR_SRC PJP21 +DC_PWR_SRC

POWER_JP
1 2
1
PC168 PC171 PC70 PC71
1
PC170 PC167 PC76 PC77 + +
1
+ + PR64 PR65
2200P/50V/0402
10U/25V/1206
.1U/50V/0603
10U/25V/1206_NC
0_0805 0_0805
2200P/50V/0402
10U/25V/1206
10U/25V/1206
.1U/50V/0603
2
+5V_VCC3
2
D D
2
PC165 PR66
1
0_0402_NC
.1U/50V/0603
1
PR159
1.8 Volt +/- 5%;f=400kHz
2
0_0402
1 2
Thermal Design current: 5.61A 0_0402_NC PR161
1.25V +/- 5%;f=300kHz
2
Maximum current: 8.015A 2 1
PC166 PR160
2 1 PR158 .1U/25V/0603 Thermal Design Current: 0.924A
OCP: 12.36A 10K_0603
2
PC188 0_0402_NC
1 2 Maximum Current: 1.32A
2 1
+1.8V_SUS .1U/50V/0603
OCP: 1.67A
8
7
6
5
4
3
2
1
PR162 +3.3V_ALW
LDOREFIN
LDO
EN_LDO
VIN
VCC
TON
VREF3
REF
PC182 16.9K_0603
2
.1U/25V/0603_NC +1.25V_RUN
9 32 PR163 PR174
1
BYP REFIN2
1
10 31 100K/F_0402 100K/0603_NC
PJP8 PJP7 OUT1 PU9 ILIM2 1 2
11 FB1 OUT2 30
2
POWER_JP POWER_JP PR73 309K/F_0402 12 29 1 2
1
ILIM1 SKIP#
5
1 2 13 MAX8778ETJ+ 28 0_0402PR186
0_0402PR186 PJP10
POK1 POK2 1.25V_RUN_ON <28> D1 D1
<28> DDR_ON 14 27 PQ23B POWER_JP
2
EN1 EN2 1.25V_DH 4

15 UGATE1 UGATE2 26 FDS8984
8
7
6
5
C 16 25 G1 C
1
PHASE1 PHASE2 PL9
37 PAD S1
LGATE1
LGATE2
PQ19 4 1.8V_DH 36 6.8uH_SIQ74-6R8_2.1A/45mohm
BOOT1
BOOT2
SECFB
3
PAD
PGND
PVCC
FDS8878 1.25V_LX +1.25V_RUN_P
GND
PAD
PAD
PAD
PL8
1
PC67
3
2
1
1.0UH_SIL104_11A/6mohm 2 PC175 D1 D1 + +
35
34
33
17
18
19
20
21
22
23
24
+1.8V_SUSP 2 1 1.8V_LX .1U/25V/0603 1.25V_DL 2 PC65
10U/25V/1206_NC
2
PC173 G1 PQ23A
1
2
1
.1U/25V/0603 PR177 1 PR179 2 PC189 FDS8984
150U/2V/ESR18
S1
9
8
7
6
5
PC64 PQ20 1_0603 1_0603 4700P/50V/0603_NC Rdson=30mOhm
1
1
+ + FDS6680AS 1 2
2
PC66 PC164 Rdson=12.5mOhm 4 1.8V_DL Del PC66
330U/2.5V/ESR15
330U/6.3V/ESR25_NC
+5V_ALW
.1U/25V/0603
+3.3V_ALW PC183
3
2
1
2
1
PC181 .1U/25V/0603_NC
PR168 4700P/50V/0603 +5V_VCC3
PR67
1
27.4K/F_0603
2
2
2 1
PR172 PR170
1
10_0603 100K/F_0402
100K_0402_NC
PC176 PC72
PR169 1U/10V/0603 1U/10V/0603
2
1
17.4K/F_0603
1.25V_RUN_PWRGD <38> Power Sequencing, Vcore Regulator
2
1.8V_SUS_PWRGD <28> Power Sequencing

SJ5
B B
2 2 1 1
Jump20X10
0.9V +/- 5%
Design current 1.05 A
+1.8V_SUSP +5V_ALW V_DDR_MCH_REF +0.9V_P
Peak Current 1.5 A
+0.9V_DDR_VTT
PJP19
U32
10 IN VTT 3 1 2
1 2 2 VLDOIN POWER_JP
PJP20 5
POWER_JP VTTSNS
1 VDDQSNS
VTTREF 6
<28> 0.9V_DDR_VTT_ON 7 S3 (STBY)
2
PC160
4 10U/4V/0603
PGND PC161
9
PAD
<28> DDR_ON
1
S5 (OFF)
1
8 10U/4V/0603
AGND PC159
2
PC163 TPS51100
.1U/25V/0603
A A
11
10U/4V_NC PC162
0.1U/25V
1
QUANTA
Title
COMPUTER
1.25V,1.05V,1.8V,0.9V

FM5 0.1

5 4 3 2 1
5 4 3 2 1
+1.5V_RUN /+1.05V_VCCP /+3.3V_ALW /+3.3_RTC_LDO

+PWR_SRC
PJP3 +DC2_PWR_SRC
POWER_JP
1 2
D D
1
PC144
+ PC146 + PC145 PC143
.1U/50V/0603
PR42 PR44
2200P/50V/0402
2
2
1
1
0_0805 0_0805
10U/25V/1206
10U/25V/1206
2
2
+ PC141 PC54 PC49
2
10U/25V/1206 .1U/50V/0603 2200P/50V/0402
2
2
PC106
2
.1U/50V/0603
1
Note:PC105 use
0.1uFfor Intersil,
+5V_VCC2 +3.3V_RTC_LDO Use 1uF for
1.5V +/- 5% ; f=200kHz MAX8778
Thermal Design Current: 2.3A 1.05V +/- 5%; f=300kHz
Maximum Current: 3.3A Dis. Thermal Design Current: 6.9A
2
2
1
PR113 PR124
OCP: 4.15A PR129 0_0402 0_0402 PC105 Dis. Maximum Current: 9.8A
0_0402 PR125 PR126 1U/10V/0603
Dis. OCP: 12.36A
2
93.1K/F_0402_NC 105K_0402_NC
1
+1.5V_RUN 1 2 1 2
1
+1.05V_VCCP
REF
2
6
1 2
5
6
7
8
C PJP6 PQ11B D1 D1 C
POWER_JP FDS8984 4 1.5V_DH PR118 PC118
1
1G 0_NC .1U/25V/0603 1.05V_DH 4 PQ12
2
8
7
6
5
4
3
2
1
S1 FDS8878 PJP4 PJP5
1
POWER_JP POWER_JP
LDOREFIN
LDO
EN_LDO
VIN
VCC
TON
VREF3
REF
3
5.2UH_SIL104R_5.5A/22mohm PL5
1
2
3
+1.5V_RUN_P 2 1 1.5V_LX
2
PL6 1.0UH_SIL104_11A/6mohm
7
9 32 1.05V_LX 2 1 +1.05V_VCCP_P
D1 D1 BYP REFIN2 PR130 309K/F
10 OUT1 ILIM2 31
2
21.5V_DL 11 FB1
PU8
OUT2 30 1 2
5
6
7
8
9
PR127 PQ11A 1G 1 2 12 29 2 PR154 1 PQ10
ILIM1 SKIP#
1
1
0_0402_NC FDS8984 S1 PC190 PR131 POK1 13 MAX8778 28 0_0402 POK2 FDS6680AS + +
POK1 POK2
1
PC147 + Rdson=30mOhm 4700P/50V/0603_NC 249K_0402 EN1 14 MAX8778 27 EN2 1.05V_DL 4 Rdson=12.5mOhm PC158 PC156 PC155 PC157
1
PC154 PC142 EN1 no QCI P/N EN2

15 26
330U/2.5V/ESR15
330U/2.5V/ESR40_NC
1
2
.1U/25V/0603 UGATE1 UGATE2
.1U/25V/0603
10U/6.3V/1206
16 25
2
PHASE1 PHASE2
10U/6.3V/1206
150U/2V/ESR18
37
1
2
3
PAD
2
LGATE1
LGATE2
36
BOOT1
BOOT2
SECFB
PAD
2
PGND
PVCC
PR128
GND
PAD
PAD
PAD
1
0_0402_NC PC132 PC135
2
.1U/25V/0603 .1U/25V/0603
1
PC121 PR142
1
35
34
33
17
18
19
20
21
22
23
24
2
0.1U/50V/0603_NC PR141 1_0603
1
1_0603 1 2
2
1 2
PC130
0.1U/25V_NC
1
+5V_VCC2 PR111 +5V_ALW
10_0603
B
1 2 B
Notes:
SJ2
2. For Inspirion +3.3V_ALWP becomes +3.3V_SUSP.
1
1
Layout Notes: 2 2 1 1
Place C7 very near U1-pin19 and PU1-pin20. PC112 PC136 3. For Inspirion +5V_ALW2 becomes +5V_ALW
1U/10V/0805 1U/10V/0603
2
Place C8 very near U1-pin3. Jump20X10

Place R19 very near U1-pin21.
Minimize loop including Q4, L2, C11, C12 and R19.
Minimize loop including Q2, L3, C17, C18, C19 and R19.
Route GNDA_DC2 using at least 25 mil trace width. +3.3V_SUS
Minimize GNDA_DC2 trace length.
Place C15 near U1-pin7.
2
Place C20 near U1-pin5.
Place R7 near U1-pin11. PR136 0_0402 PR132 PR140
EN1 1 2 178K_0402 178K_0402
Place R12 near U1-pin31. 1.5V_RUN_ON <28>
Place R3, C10 near U1-pins 24 and 25. PR139 0_0402
1
Place R2, C9 near U1-pins 16 and 17. EN2 1 2 1.05V_RUN_ON <29>
POK2
Route +1.05V_BOOT, +1.05V_BOOST, +1.5V_BOOT, +1.5V_BOOST 1.05V_RUN_PWRGD <38>
using 25mil trace width and minimize lengths. POK1
1.5V_RUN_PWRGD <38>
Connect large copper fill areas to PQ1, PQ2, PQ3 and Q4
signals for thermal improvement.
Minimize length of +1.5V_RUN_PL and +1.05V_VCCP_PL.
A Place C1, C2, C3, C22 very near Q3-pins 5, 6, 7, 8. A
Place C4, C5, C6, C23 very near Q1-pins 5, 6, 7, 8.
Route +DC2_PWR_SRC using 50 mil trace width and minimize
length. QUANTA
Route OUT1 and OUT2 away from inductor and switch-node.
Sense Vout directly at output bulk cap.
Title
COMPUTER
1.5V,1.05V

FM5 1A

5 4 3 2 1
5 4 3 2 1
DC/DC +3V_ALW/+5V_ALW/+5V_ALW2 /+15V_ALW

Ton:OUT1/OUT2 Switching Frequency
VDD 200kHz/300kHz
Place these CAPs
OPEN (REF): 400kHz/300kHz
close to FETs
GND: 400kHz/500kHz
Place these CAPs
+DC1_PWR_SRC No Install PR79 for ISL6236 No Install for ISL6236
PJP11 Install PR79=0Ohm for MAX8778 Install 10 ohm for MAX8778 close to FETs
D D
POWER_JP
1 2
+PWR_SRC 3.3 Volt +/- 5%
2
PC172 PC174 PC177 PC178 PC82 PC85 +5V_ALW2 PR176 +5V_VCC1 PC83 PC79
Design Current:7.18A
1
1
10_0603
1
+ + + + PR180 PR181
2200P/50V/0402
2200P/50V/0402
10U/25V/1206
10U/25V/1206
10U/25V/1206
.1U/50V/0603
.1U/50V/0603
2 1 Maximum current:10.25A
10U/25V/1206_NC
0_0805 0_0805
1
OCP: 12.36A
2
2
2
2
PC81 PR72 PR167
4.7U/10V/1206 0_0402_NC 0_0402
2
5 Volt +/- 5% PC84
+3.3V_ALW2
1
2
2
PR173 PC80 +3.3V_ALW
1U/10V/0603
.1U/50V/0603
Design Current: 7.43 A
1
PR79 0_0402_NC
0_0402_NC PC186 PC78
Maximum current:10.6A
2
1U/10V/0603 .1U/10V/0402 PR68
2
1 2 0_0402_NC
OCP: 12.96A
FBMH4532HM681
FBMH4532HM681
FBMH4532HM681
5
6
7
8
2
2 1
FL10
FL12
FL11
PR171 +3.3V_DH 4 PQ22
0_0402_NC FDS8878
+5V_ALW
8
7
6
5
4
3
2
1
PC88
1
2
3
1
8
7
6
5
LDOREFIN
LDO
EN_LDO
VIN
VCC
TON
VREF3
REF
1
.1U/50V/0603_NC PL7
PJP12 PQ25 4 +5V_DH 1.5uH_SIL1055RC-12.5A/7.6mOhm
1
POWER_JP FDS8878 PR71 +3.3V_LX 1 2 +3.3V_ALWP
C +5V_ALWP 9 32 309K/F_0402 C
PL10 BYP REFIN2
10 31 1 2
2
3
2
1
OUT1 ILIM2
2
2.2uH_SIQH125A-13A/5.5mOhm 11 PU6 30 PC68
+5V_ALWP +5V_LX FB1 OUT2
1 2 1 PR81 2 12 ILIM1 SKIP# 29 2 1 PR164
324K/F_0402 POK1 13 MAX8778ETJ+ POK2 0_0603
.1U/50V/0603
POK1 POK2 28
2
2
PC94 14 MAX8778 27 0_0402 + PC69
EN1 EN2
5
6
7
8
9
PR80 15 26 PR187 PQ21 330U/6.3V/ESR25
1
UGATE1 UGATE2
2
0_0402_NC FDS6680AS
.1U/50V/0603
16 25
1
PHASE1 PHASE2
2
9
8
7
6
5
PC93 + PQ24 37 +3.3V_DL4

PAD
2
LGATE1
LGATE2
PR185 330U/6.3V/ESR25 FDS6680AS PC90 36 PC74 Rdson=12.5mOhm
BOOT1
BOOT2
SECFB
1
PAD
2
PGND
PVCC
240_0805_NC Rdson=12.5mOhm 4+5V_DL .1U/50V/0603 .1U/50V/0603 PR69
GND
PAD
PAD
PAD
1
0_0603_NC
1
1
2
3
1
1
2
PR70
3
2
1
35
34
33
17
18
19
20
21
22
23
24
1
PR84 PR83 1_0603
0_0402 1_0603 1 2
1 2
1
+3.3V_ALWP +3.3V_ALWP
.1U/50V/0603_NC
PD13 SJ4
+5V_ALW2
PC73
1 PC87 2 1
2 1
1
.1U/50V/0603
32 1 PR82 PR166
1
Jump20X10 100K_0402 100K_0402_NC
1
2
PD7
2
2
BAT54S-7-F PC86 SDM10K45
2
PC75 PD12 .1U/50V/0603 POK2

.1U/50V/0603
2
1
B B
3 PR165
0_0402
2
1
BAT54S-7-F POK1
ALW_PWRGD_3V_5V <28>
SJ3
2 1 +15V_ALWP 1 2
+15V_ALW 2 1
2
1
PC169 PR175
Jump20X10 200K/F_0402 PR178
.1U/50V/0603 39K/F_0402
1
2 LDO = 5V (LDOREFIN = GND) or

PR76 LDOREFIN RANGE: 0.3V to 2V
1K/F_0402 LDO = 2x LDOREFIN
<28> ALWON 2 1
1
<34> THERM_STP# 2 1
PR77
PR75 200K_0402
0_0402
REFIN2: DYNAMIC 0 to 2V
2
REFIN2 = RTC: 1.05V Fixed

REFIN2 = VCC: 3.3V Fixed
A A
QUANTA
Title
COMPUTER
3VALW,5V,3V, power on

FM5 1A

5 4 3 2 1
A B C D E F G H
FL3 +PWR_SRC
+CPU_PWR_SRC FBMH3225HM202NT
1 2
FL4
+CPU_PWR_SRC FBMH3225HM202NT
+5V_ALW 1 2
2
5
6
7
8
9
PR109 PQ35 PC41 PC42 PC129 PC128
2
10_0603_NC Intersil Note: PIN 39 is FDS6298 PR135 PC107 PC113 PC192 PC191
10U/25V/1206
10U/25V/1206
10U/25V/1206
10U/25V/1206
1
1
+5V_ALW
2200P/50V0402
2200P/50V0402
PR21 2.2/F/1206_NC
.1U/50V/0603
.1U/50V/0603
+3.3V_RUN. I would like to 4
1
PC103 0_0603
suggest this change to
1
1U/10V/0805 1 2
2
+3.3V_ALW. It will be the same
1
2
3
1
as +5V_ALW sequence which is PU3
1
for ISL6260C and drivers PC23
1 1
PR116 5 1 .22U/10V/0603 PC138
2
VCC BOOT
1
10_0603 PC27 1.5nF/50V/0603_NC
(VDD)
2
.01U/25V/0402_NC 2 8 UG1 PL4
+3.3V_RUN FCCM PWM UGTE 0.45U_ETQP4LR45XFC_25A_20%
6
2
FCCM PH1
(SKIP#) PHSE 7 2 1 +VCC_CORE
3 GND
9 4 LG1
3
PAD LGTE
5
6
7
8
9
2
PC33 MAX8791GTA+ PC48 PR152
1
1
1U/10V/0805 4 1.5nF/50V/0603_NC 0_0402
2
PR23 PR149 PC111
1
1.91K/F_0603 PQ9 2.2K/F_0603 .22U/10V/0603 PC59 PC149
2
1
1
1
SI7336ADP 1 2 1 2 PC152 + +
1
2
3
220U/2V/ESR7
220U/2V/ESR7
2
2
1
PR47
.1U/16V/0603
IMVP_PWRGD <13,28,38>
2
PR115 1 2.2/F/1206_NC PR30
0_0603 PU1 PR146 0_0402
2
PR114 7.68K/F_0805_NC
19
20
18
39
40
13K/F_0402
1
2
(GND)
VSS
3V3
VDD
VIN
PGOOD
(IMVPOK)
(V3P3)
(NC)
(VCC)
PR12 VSUM VO
2
<29> IMVP6_PROCHOT# 1 2 4 VR_TT#

PR13 0_0402
143K/F_0402 (VRHOT#)
2 1 3 24 FCCM
PR11 RBIAS (OSC) FCCM
2 PR4 1 2 1 5 NTC (THRM)
(DRSKP#)
0_0402_NC
470P/50V/0402 100K_0402_NC MAX8786_PWM1 +CPU_PWR_SRC
PWM1 27 RDS(ON)=12.5m ohm
1 2 6 SOFT (CCV)
PC13 +5V_ALW
2 1 23 CSP1
CPU_VID0 ISEN1
28 VID0
2
PC6 <4> VID0 (CSP1) PC116 PC119 PC123 PC122 PC37 PC38
5
6
7
8
9
2
2200P/50V/0402_NC CPU_VID1 PQ34 PR134 PC194 PC193
10U/25V/1206
10U/25V/1206
10U/25V/1206
10U/25V/1206
.1U/50V/0603
<4> VID1 29 VID1
1
2200P/50V0402
2200P/50V0402
PR28 FDS6298 2.2/F/1206_NC
.1U/50V/0603
CPU_VID2 30 PC34 0_0603 4
<4> VID2
1
VID2 1U/10V/0805
2 1 2 2
2
CPU_VID3 31 26 MAX8786_PWM2
<4> VID3 VID3 PWM2
1
2
3
PU2
1
<34> PWR_MON CPU_VID4 32 PC24
<4> VID4 VID4
22 CSP2 5 1 .22U/10V/0603 PC134
2
CPU_VID5 ISEN2 VCC BOOT 1.5nF/50V/0603_NC
<4> VID5 33 (VDD)
2
VID5
2
(CSP2) 2 8 UG2 PL3

PC14 PR14 CPU_VID6 FCCM PWM UGTE 0.45U_ETQP4LR45XFC_25A_20%
<4> VID6 34 VID6 6 FCCM
1U/10V/0603_NC 10K_0402_NC 7 PH2 2 1 +VCC_CORE
1
(SKIP#) PHSE
<3,6,11> H_DPRSTP# 37 DPRSTP# 3 GND
9 4 LG2
2
3
PAD LGTE
5
6
7
8
9
2
2 PR29 1 36 25 MAX8786_ PWM3
<6,13> DPRSLPVR DPRSLPVR PWM3
499/F_0402 MAX8791GTA+ PC46 PR151
<3> H_PSI# 2 PR17 1 1 4 1.5nF/50V/0603_NC 0_0402
1 2
0_0402 PSI# CSP3 PR148 PC36
ISEN3 21
1
2 Intersil Note: PR155 PQ8 2.2K/F_0603 .22U/10V/0603
PWR_MON (PGD_IN)
1
PR18 (CSP3) change to 13.7K for SI7336ADP PR46 1 2 1 2 PC153 + PC60 + PC148
T13
1
2
3
1 2 PR10 2.2/F/1206_NC
60A OCP. We heard
1
PR20 0_0402 CLK_ENABLE# 226K/F_0402
.1U/16V/0603
220U/2V/ESR7
220U/2V/ESR7
38
2
9,38> RUNPWROK CLK_EN# Santa Rosa CPU might
1 2 2 1
2
0_0402_NC PR19 have ~50A peak PR145
<28> IMVP_VR_ON PAD 7.68K/F_0805_NC
1 2 35 VR_ON (SHDN#) current with 10uS
0_0402 PR100 RDS(ON)=4m ohm
duration
1
11.5K/F_0402_NC
<4> VCCSENSE 2 1 12 7 1 2 VSUM PR108 PR31
PR6 VSEN (FBS) OCSET 0_0402 1_0402_NC
1
10_0603 PC16 (ILIMPK)
2
1000P/50V/0402 PR16 4.99K/F_0402 13
2
10K_0603 PR103 RTN (GNDS) VSUM
17
2
VSUM CSN2 VO
B=3435
.33U/16V/0603_NC
.012U/50V/0603_NC
.033U/16V/0402_NC
1 2 11 (PWR) PR112
2
VDIFF (VPS)
2
PR107
PC18 17.8K/F_0402
1000P/50V/0402 PR15
<4> VSSSENSE 2 1 2.43K/F_0402_NC +CPU_PWR_SRC
PR5 10_0603 MAX8786GTL+
1
1
1
PR101 10
4.53K/F_0402_NC
PWR_MON <34>
1
FB (TIME)
2
1 2 1 2 2 1
2
PR106
2
2
2
2
3 +5V_ALW 3
332/F_0402_NC PC97 6.49K/F_0603 PR25 PC124 PC40 PC39 PC125
2
PC19
PC15
PC21
680P/50V/0402_NC PR102 6.8K_0402_NC PC99 PC117 PC120
10U/25V/1206
10U/25V/1206
10U/25V/1206
10U/25V/1206
5
6
7
8
9
PR26 .1U/10V/0402 PQ33 PR138 PC198 PC197
.1U/50V/0603
2.2K/F_0402_NC 9 COMP (REF)
1
1
2200P/50V0402
2200P/50V0402
15K/F_0402_NC FDS6298 2.2/F/1206_NC
.1U/50V/0603
1
1
16 VO 1 PR37 4
1
1
(CSN1) VO PC104 0_0603
1 2 8
2
VW (TRC)
1
DROOP
1U/10V/0805
15 (CSN3)
1 2
(CSN2)
PR9 71.5K/F_0402 PR27

PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
DFB
1
2
3
PU5
1
0_0402_NC
1 2 1 2 5 1 PC26 PC140
VCC BOOT
41
42
43
44
45
46
47
48
49
50
14
PC96 PR97 .22U/10V/0603 1.5nF/50V/0603_NC

2
2
1500P/50V/0402_NC 82.5K/F_0402_NC PR99 (VDD) UG3 PL2
2 PWM UGTE 8
2
1K/F_0402 CSN2 FCCM 6 0.45U_ETQP4LR45XFC_25A_20%

FCCM
1
2 1 2 1 PC185 7 PH3 2 1
(SKIP#) PHSE +VCC_CORE
1
PC10 PR105 3
PR24 .1U/16V/0603 22.1K/F_0402 GND LG3
9 4
2
3
.01U/25V/0402 PAD LGTE
5
6
7
8
9
2
PC12 0_0402_NC
CSN3
1
1
1
1000P/50V/0402_NC MAX8791GTA+ PR153
PR3 2 1 PC9 4 PC47 0_0402
2
0_0402 330P/50V/0603_NC 1.5nF/50V/0603_NC 2.2K/F_0603 PC35
1
2 1 PQ7 PR150 .22U/10V/0603
1
SI7336ADP 1 2 1 2 PC151 + PC61 + PC150
2
1
2
3
1
1
PC184 PC98 PR48
.1U/16V/0603
220U/2V/ESR7_NC
220U/2V/ESR7_NC
2
2
2.2/F/1206_NC PR147
.1U/16V/0603 .1U/16V/0603 7.68K/F_0805_NC
2
2
VSUM
1
PR98 PR22
0_0402
1_0402_NC
2
VO
CSN3
4 4
PHASE 3 populate QUANTA

Title
COMPUTER
CPU POWER

FM5 1A

A B C D E F G H
5 4 3 2 1
POWER STATES
Signal SLP SLP SLP S4 SLP ALWAYS M SUS RUN CLOCKS
State S3# S4# S5# STATE# M# PLANE PLANE PLANE PLANE USB PORT# DESTINATION
S0 (Full ON) / M0 HIGH HIGH HIGH HIGH HIGH ON ON ON ON ON 0 Right Top

D D
S3 (Suspend to RAM) / M1 LOW HIGH HIGH HIGH HIGH ON ON ON OFF ON 1 Right Bottom
S4 (Suspend to DISK) / M1 LOW HIGH HIGH LOW HIGH ON ON ON OFF ON 2 Side TOP
S5 (SOFT OFF) / M1 ON ON ON OFF ON 3 LOW HIGH SideLOW

LOW Bottom
HIGH
ICH8-M 4 Ext. USB TOP
S3 (Suspend to RAM) / M-OFF LOW HIGH HIGH HIGH LOW ON OFF ON OFF OFF
S4 (Suspend to DISK) / M-OFF LOW LOW HIGH LOW LOW ON OFF OFF OFF OFF 5 DIgital Camera
S5 (SOFT OFF) / M-OFF LOW LOW LOW LOW LOW ON OFF OFF OFF OFF 6 Express Card
7 WPAN/Bluetooth
PM TABLE
C 8 Ext. USB Bottom C
+3.3V_ALW +1.8V_SUS +0.9V_DDR_VTT +3.3V_RUN_CARD +DC_IN
+3.3V_RTC_LDO +1.8V_LOM +1.05V_VCCP +2.5V_RUN +DC_IN_SS 9 WWAN
power +3.3V_WLAN +3.3V_LAN +1.25V_RUN +5V_MOD +PWR_SRC
plane +5V_ALW +3.3V_SUS +1.5V_CARD +5V_RUN +RTC_CELL 1 None
+15V_ALW +5V_SUS +1.5V_RUN +5V_SPK_AMP
+3.3V_CARD +CPU_PWR_SRC 2 None
+3.3V_CARDAUX +VCC_CORE ECE 5011
+3.3V_R5C832 +VDDA 3 None
State
+3.3V_RUN
S0 ON ON ON ON 4 None
S3 ON ON OFF ON
PCI EXPRESS DESTINATION
S5 S4/AC ON OFF OFF ON
B
Lane 1 MINI CARD-1 WWAN B
S5 S4/AC don't exist OFF OFF OFF ON

Lane 2 MINI CARD-2 WLAN
Lane 3 MINI CARD-3 WPAN

PCI TABLE Lane 4 Express Card
PCI DEVICE IDSEL REQ#/GNT# PIRQ Lane 5 None
Lane 6 None
BCM4401B AD16 REQ#0 / GNT#0 PIRQB
R5C833 AD17 REQ#1 / GNT#1 PIRQC: Card reader

A
PIEQD: 1394 A
QUANTA
Title
COMPUTER
Schematic Block Diagram1

C & G UMA 1A

5 4 3 2 1
1 2 3 4 5 6 7 8
+3.3V_SUS +3.3V_RUN +3.3V_RUN

197
Express Card WLAN WWAN WPAN 2N7002 DIMM 0 0A0h

2.2K 2.2K 2.2K 2.2K 195
7 8 30 32 30 32 30 32
G
AJ26 ICH_SMBCLK D S MEM_SCLK 197
A
ICH8-M G DIMM 1 0A4h A
AD19 ICH_SMBDATA D S MEM_SDATA 195

AC17
AE19
+3.3V_SUS
10K 10K
AMT_SMBDAT
+3.3V_ALW +3.3V_RUN +3.3V_RUN

AMT_SMBCLK
2N7002
2.2K 2.2K 2.2K 2.2K
B B
G
13 CKG_SMBCLK D S CLK_SCLK 16
G CLK GEN 0D2h

12 CKG_SMBDAT D S CLK_SDATA 17
+3.3V_ALW
4.7K 4.7K
100 THRM_SMBCLK 12
99 THRM_SMBDAT 11 GUARDIAN 05Eh
C C
+3.3V_ALW
8.2K 8.2K
SIO
8 LCD_SMBCLK S39
MEC5025 Inverter A9H:Contrast
7 LCD_SMBDAT S40
AAH:Backlight
+3.3V_ALW
+5V_ALW
D 10 D
8.2K 8.2K 9 012h

CHARGER
8 PBAT_SMBCLK
100
3 QUANTA
7 PBAT_SMBDAT 4 Primary 016h
Title
COMPUTER
BATTERY Schematic Block Diagram1
100 Size Document Number Rev
C & G UMA 1A

1 2 3 4 5 6 7 8
5 4 3 2 1
Model Item Page Date ECN Number Item Id Rev. Issue Description Solution Description
1 39-45 7/13/2006 Update PWR schematics

C/G
DISCRETE 2 Move PLTRST_DELAY# from EC to ICH8 S
3 11 9/20/2006 2nd SATA HDD can't recognize Move 2nd SATA from port 1 to port 2
D 4 38 Disconnect GFX_PWRGD to system ( Delete R463 ) 9/20/2006 D Gfx card tim
5 38 9/20/2006 Gfx card timing error Disconnect +1.8V_RUN detect circuit to system ( Delete Q47 )
Update PWR schematics 6 39-45 9/21/2006
7 23 9/21/2006 Add +1.8V_RUN for SATA buffer test (CON4.20-21-22-42-43-44)
Update WLAN LED implementation.With the current implementation, there is Please change the WLAN LED implementation to advice from Dell.
8 37 10/2/2006 a possibility for backdrive from the WLAN LED control signal to +3.3V_RUN
while in S3 / S4 / S5. With the voltage rail being +3.3V_WLAN, there is a
high probability that the LED will be illuminated while in S3 / S4 / S5.
9 13 10/2/2006 Intel has advised that the pull-up on LINKALERT# be depopulated and that Depop R247 & change R227 from 10K ohm to 8.2K ohm
the pull-up on GPIO14 be 8.2k. Please update.
10 28,33 10/11/2006 In order to leverage the M07 implementation, the sniffer LED circuit needs Change back VC08 design, rename SNIFFER_YELLOW to SNIFFER_YELLOW#,
to be modified. The MEC5025 pins are being changed from active high to SNIFFER_GREEN to SNIFFER_GREEN# and remove R507 and R510.
active low.
C 11 28,29 10/11/2006 Move DOCK_SMB_PME from MEC5025 SGPIO37 to ECE5018/5011 DOCK_SMB_PME# should be pulled up to +3.3V_ALW C
GPIOC0.Move DOCK_SMB_ALERT# from ECE5018/5011 GPIOC0 to DOCK_SMB_ALERT# should be pulled up to +5V_ALW
MEC5025 SGPIO37
Remove 3.3V_LAN_PWRGD circuit from page 38
12 28,38 10/11/2006 Add ATI_Intel to MEC5025 pin 14 and tie to GND.This connection Delete 3.3V_LAN_PWRGD from MEC5025 pin 14
should be labeled ATI_Intel. Add a connection from the MEC5025 pin 14 and tie to GND.
Move ALW_PWRGD_3V_5V from MEC5025 pin 18 to pin 29
14 13 10/11/2006 1) Move SIO_EXT_SCI# from ICH pin AG22 to ICH pin AC19
2) Delete R242 ( delete DOCKED# signal )
15 13 10/11/2006
Reserve LOM_SMBALERT# (ICH8 AG22) & PU resister
Change WPAN USB port from USBP7 to USBP4
17 23,29 10/18/2006 Modify

To resolve HDDC_EN
this and MODC_EN
issue, please Circuits to
use the HDDC_EN andResolve
MODC_ENGlitch Issue. that are
circuits
unintentionally for a brief moment.With the current Dawson design, it has attached below. These new circuits resemble closely our other load switch
been shown that the +15V_ALW rail comes up before the +3V_ALW rail on circuits, but require an additional FET and changes the sense of the HDDC_EN
B the original HDDC_EN and MODC_EN circuits. This can cause a and MODC_EN signals to active high. Please note the use of +5V_ALW2 on these B
momentary glitch at the gate of the power FET, which may cause the FET circuits. The +5V_ALW2 voltage comes directly from the LDO output on the
to turn on unintentionally for a brief moment. 3V/5V switcher in your M08 design.
18 12,14 10/18/2006 WWAN Noise - ICH improvements. Add C871~C878 for USB OC.
Add one .1 uF cap on each USB OC (over current) trace near the ICH. Add C867~C870 in parellel to C825.
Add four .1uF caps in parellel to C813 close to the ICH pins. Add C748,C864~C866 in parellel to C813.
Add four .1uF caps in parellel to C825 close to the ICH pins.
10/23/2006
19 37 Use LED_MASK# to control BT LED to prevent leakage Add R336 & change Q13 to BJT
Pullup is at reference designator R298. Cha

20 34 10/23/2006 Feedback from SMSC has indicated that the pull-up rail on 5V_CAL_SIO1#
needs to change from +5V_SUS to +3.3V_SUS.This is necessary because the
GPIO on the EMC4001 is 3V tolerant, not 5V.
Due to the power on defaults of the MEC5025, the pull-downs on the KSI
21 28 10/23/2006 lines of the MEC5025 need to be stronger, to avoid pulses from powering on
certain power rails. Please do the following:
1. Change pull-down on SUS_ON to 2.7k Change R355,R358 to 2.7K
A 2. Change pull-down on RUN_ON to 2.7k A
22 24 10/23/2006 Add SMBus isolation circuitry for WLAN.Add isolation circuitry for SMBus on
WLAN. QUANTA
Title
COMPUTER
Change List

JM7B 1A

5 4 3 2 1
5 4 3 2 1
Model Item Page Date ECN Number Item Id Rev. Issue Description Solution Description
Chipset side spec. Differetial CLK raise/fall slew rate is 2.5~8 V/ns, only Change serial resistors ( PR4,PR5,PR10,PR12,PR13 ) to meet the CLK SPEC
23 17 10/26/2006
C/G express card and mini card is 0.6~4V/ns. BITCLK rise/fall slew rate in 1-3
V/ns &
DISCRETE
24 37 10/26/2006 Change LED control method
25 37 10/26/2006 Add OR gate for BT_ACTIVE
M08 GPIO A14 update. Original EC5011 pin66 CCD_VDD_ON move to IC8 Move CCD_VDD_ON from EC5011 pin66to IC8
D 26 13 10/26/2006 pinAD10 GPIO48 and add 100K ohm pull down. pin AD10 GPIO48 and add 100K ohm pull down.
D
27 25 10/26/2006 For Comm team suggestion ( GG list ), pop C217 for WWAN
28 39 - 45 10/31/2006 PWR team updat schemtics - 10/23
C C
B B
A A
QUANTA
Title
COMPUTER
Change List

JM7B 1A

5 4 3 2 1
6 5 4 3 2 1
Model Item Page Date ECN Number Item Id Rev. Issue Description
29 For EMI request, add RC circuit for Mini card clk request 24 - 25 11/1/2006
C/G
F
DISCRETE 30 39 11/1/2006 For +3.3V_RUN inrush current, it may over OCP ( 12.36 A ) Change PC58 from 470 pF to 6800 pF F
For AP - THN+D fail, change C306, 307 to 0.033uF/16V/X7R/1206 & C326, C329 Change C306, 307 to 0.033uF/16V/X7R/1206 & C326, C329 to 1uF/16V/X7R/1207
31 32 11/3/2006 to 1uF/16V/X7R/1206
32 32 11/3/2006 'PO' noise in resume from S3,S4,S5 Reserved the AUD_AMP_MUTE# for 'PO' noise
34 17 11/09/2006 Change R44 to 2.2K per Intel recommend value.

Move PCIE_MCARD2_DET# from GPIO20 to ICH8 GPIO5/PIRQH# pin B3.
35 12 - 13 11/21/2006 Due to Intel-ICH8 uses GPIO20 pin AE11 as an Internal Strapping at power up
36 13 11/21/2006 GPIO18 is default as an output at power up, it will drive 1Hz output at Add 4.7K series - R547 resistor to separate it
E
power up. Per Intel this GPIO could not be connected to GND E
37 32 11/22/2006 There is potential back

adddrive
100kohm
from the
resistor
codec (R253)
DVddbetween
back to the
pin AVdd
40 andsupply
+3.3V_RUN and a 1000pF cap
due to an internal ESD diode (C643 below) from Pin 40 to ground
1.Change capacitor for U5 pin 79, 94,106 (VDDIO) (C18, C16, C25) to 47pF.
38 35 - 36 11/28/2006 GG list -- COMM team request
2.Change those three capacitors (C27, C37,C34) to 47pF
3.Add C644 - 47pF capacitor by the pin 57 of U5
4.Change L7 to 0805 package -BK2125LM152. & C23 to 47 pF
5.Add Ferrite Bead BK1608LM152 on 1.8V to EPHY_AVDD pin 57
39 28-29 11/28/2006 Move DOCK_SMB_PME from MEC5025 SGPIO37 to ECE5018/5011 DOCK_SMB_PME# should be pulled up to +5V_ALW
GPIOC0.Move DOCK_SMB_ALERT# from ECE5018/5011 GPIOC0 to DOCK_SMB_ALERT# should be pulled up to +3.3V_ALW
D D
MEC5025 SGPIO37
40 24 12/01/2006 GG list -- Seperate debug port with MINI-PCI if not necessary Add 4 0ohm resistors for these pins
41 24 - 25 12/01/2006 GG list -- Delete decoupling cap Delete C222 & C424
43 32 12/08/2006 GG List -- Change audio AMP to TI solution 1.Change codec to TPA9040A4

2.Pop R505, C619 & C614; depop R506, R504 & R497
C
44 31 12/13/2006 GG List -- Change power source for LED of dash board Change JTP1.9 from +3.3V_RUN to +5V_ALW C
46 28 12/25/2006 GG List -- Remove EC5025 pin15 GPIO4 AUD_AMP_MUTE# circuit. NC R538
47 34 12/25/2006 GG List -- Add THERMATRIP_VGA# function Pop R441,442,443 and Q35, C568 for THERMATRIP_VGA# trip.
48 33 12/28/2006 Modify CCD power control soft start function Change C403 , R284 connect method
B B
A QUANTA A
Title
COMPUTER
EMI & Screw hole

C & G UMA 2A

6 5 4 3 2 1
6 5 4 3 2 1
Model Item Page Date ECN Number Item Id Rev. Issue Description
49 22 1/11/2006 XD card detect function error

C/G
F
DISCRETE 50 29 1/11/2006 Base on A16 GPIO : Change net name from BID2 to CHIPSET_ID1 F
51 37 Add 0ohm_NC(R571) resistor pad connected from Coex1_BT_Active_MINI to

1/24/2007 Coex1_BT_Active
52 32 1/24/2007 Audio solution for pass EMI 225MHz and 451MHz radiation emission test. Added R560, R561, R562 and R563 on AUD_SPK_L1, AUD_SPK_L2, AUD_SPK_R1,
AUD_SPK_R2 trace
52 33 1/24/2007 Audio solution for pass EMI 225MHz and 451MHz radiation emission test. Added R564, R565, R566 and R567 on AUD_LINE_OUT,AUD_HP_OUT
53 GG List -- CCD_ON pull down R258 100K NC. 13 1/24/2007
E E
54 37 2/5/2007 Blue LED brightness is too high Change R30,R50,R75,R64 & R36 from 220 ohm to 330 ohm
55 30 2/12/2007 Prevent SPI CLK overshoot/undershoot issue Add C896 for RC circuit but not pop it
57 29 2/12/2007 GG List -- CIR function intermidiate issue ECE5021 pin7 PWRGD need to pull-down to GND with 0 ohm - Add R568 PD resistor
& R569 series resistor ( NC )
58 44 3/1/2007 PWR team updat schemtics - 3/1
D D
59 17 3/2/2007 Per TDC COMM team request - Change L65 to Fine tune 14M CLK - Change R57 from 33 to 15 ohm & L65 to BLM18SG260
60 04 3/2/2007 Per reliability issue - Move C98 to C249 De-pop C98 & pop C249
C C
B B
A QUANTA A
Title
COMPUTER
EMI & Screw hole

C & G UMA 2A
Date: Wednesday, March 07, 2007 Sheet 51 of 51

6 5 4 3 2 1

Dell Inspiron

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1 2 3 4 5 6 7 8

Crestline PCI EXPRESS GFX TVOUT S-Video

INDEX Power & Ground

2 Front Page PBATT+ MAIN BATTERY + (10~17V)

3-4 Merom PBATT+ SECOND BATTERY + (10~17V)

5-10 Crestline PWR_SRC MAIN POWER (10~19V)

11-14 ICH8M RTC_PWR3_3V RTC & +3.3V_RTC_LDO(3.3V)

15-16 DDRII SO-DIMM(200P) +VCC_CORE CPU CORE POWER (1.5V) RUNPWROK

17 Clock Generator +15V_ALW LARGE POWER (15V) SUS_ON

18-21 VGA +3.3V_RUN SLP_S3# CTRLD POWER RUN_ON

22 LCD Conn. & SSP +3.3V_SUS SLP_S5# CTRLD POWER SUS_ENABLE

23 CRT Conn +3.3V_ALW 8051 POWER (3.3V) ALWON/THERM_STP#

24 SATA & IDE Conn +5V_RUN SLP_S3# CTRLD POWER RUN_ON

25 PCCARD/Conn & 1394 +5V_SUS SLP_S5# CTRLD POWER SUS_ON

27 Mini Card +5V_MOD MODULE POWER (5V) HDDC_EN

28 MDC Conn. +5V_ALW LCD/CHARGE POWER (5V)

29 SIO (MEC5004) +VDDA AUDIO ANALOG POWER (5V) AUDIO_AVDD_ON

30 SIO (MEC5018) +1.5V_RUN CALISTOGA/ICH7 POWER RUN_ON

31 SERIAL PORT & USB +1.05V_VCCP CPU/CALISTOGA/ICH7 POWER RUN_ON

32 Flash ROM +1_8V_SUS SODIMM POWER SUSPWROK_5V

33 TP,BT & FIR +1.8V_RUN SDVO POWER RUN_ON

34 Switch,Keyboard & LED +0.9V_DDR_VTT SODIMM POWER RUN_ON

35 FAN & Thermal +3.3V_LAN LAN POWER AUX_EN

C 36-37 Audio CODEC(STAC9200)/Phone Jack C

38-39 LOM (BCM5752)/Switch

42 System Reset Circuit AGND_ISL6260 CPU GND

43-44 Battery Selector & Charger DC/DC POWER GND

45 DDR2_1.8VSUS, 0.9V AGND1 VTT POWER GND

46 1.5VSUS,1.05V(VTT) AGND2 VTT POWER GND

47 1.25V,1.05VM 8731AGND CHARGER GND

51 VGA DC/DC QUANTA

H_A#[3..16] U15A H_D#[0..63] U15B H_D#[0..63]

C4 R330 56 R404 CPU_TEST4 AF26

54.9/F 27.4/F 54.9/F 27.4/F

ITP_TDI 1 27 connect with Zo=55ohm, make those traces

Date: Monday, March 05, 2007 Sheet 3 of 51

AA15 AF5 0.01U/25V 10U/4V G26 AD5

VCC[058] VID[3] VSS[058] VSS[139]

+VCC_CORE VSS[071] VSS[152]

100U/25V 100U/25V 100U/25V_NC 100U/25V

0.1U/10V 0.1U/10V 0.1U/10V 0.1U/10V 0.1U/10V 0.1U/10V

Route VCCSENSE and VSSSENSE

Size Document Number Rev

Date: Monday, March 05, 2007 Sheet 4 of 51

H_D#17 W10 H20 H_A#21

H_SWING H_D#22 H_D#_21 H_A#_25 H_A#26

H_D#24 W6 E19 H_A#28

R368 H_D#25 W9 B17 H_A#29

H_D#28 H_D#_27 H_A#_31 H_A#32

H_D#29 H_D#_28 H_A#_32 H_A#33

H_D#42 AB1 AM7

H_SCOMP H_D#47 H_D#_46 H_HITM#

H_D#57 H_D#_56 H_DINV#_3

Size Document Number Rev

Date: Tuesday, March 06, 2007 Sheet 5 of 51

U19B U19C +VCC_PEG

1K/F SM_CS#_2 LVDSA_DATA#_1 PEG_RX#_13 PCIE_MRX_GTX_N14

PAD T26 CFG_4 DMI_TXN_0 DMI_MTX_IRX_N0 <12> CRT_BLUE# PEG_TX_1

R366 2 1 4.02K/F_NC CFG9 C20 AJ47 W42 PCIE_MTX_GRX_P6

PAD T92 CFG17 M24 AE50 PCIE_MTX_GRX_P14

GFX_VID_0 E35 T83 PAD Low=DMIx2

TP_NC2 NC_1 CL_PWROK

PAD T36 TP_NC8 BK1 (default)

PLTRST#_R 2 1 1 2 Size Document Number Rev