IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 32, NO.

2, FEBRUARY 2017 931

Assembly HVDC Breaker for HVDC Grids With

Modular Multilevel Converters
Gaoren Liu, Student Member, IEEE, Feng Xu, Student Member, IEEE, Zheng Xu, Senior Member, IEEE,
Zheren Zhang, Student Member, IEEE, and Geng Tang, Student Member, IEEE

AbstractThe modular multilevel converter (MMC) with half-

bridge submodules (SMs) is the most promising technology for
high-voltage direct current (HVDC) grids, but it lacks dc fault
clearance capability. There are two main methods to handle the
dc-side short-circuit fault. One is to employ the SMs that have
dc fault clearance capability, but the power losses are high and
the converter has to be blocked during the clearance. The other
is to employ the hybrid HVDC breakers. The breaker is capable
of interrupting fault current within 5 ms, but this technology is
not cost effective, especially in meshed HVDC grids. In this pa-
per, an assembly HVDC breaker and the corresponding control
strategy are proposed to overcome these drawbacks. The assembly
HVDC breaker consists of an active short-circuit breaker (ASCB),
a main mechanical disconnector, a main breaker, and an accessory
discharging switch (ADS). When a dc-side short-circuit fault oc-
curs, the ASCB and the ADS close immediately to shunt the fault
current. The main breaker opens after a short delay to isolate the
faulted line from the system and then the mechanical disconnector
opens. With the disconnector in open position, the ASCB opens
and breaks the current. The proposed breaker can handle the dc-
side fault with competitively low cost, and the operating speed is
fast enough. A model of a four-terminal monopolar HVDC grid is
developed in Power Systems Computer Aided Design / Electromag- Fig. 1. Circuit configuration of a three-phase MMC.
netic Transients including DC, and the simulation result proves the
validity and the feasibility of the proposed solution.
Index TermsAssembly high-voltage direct current (HVDC) The modular multilevel converter (MMC), which was first
breaker, dc fault clearance solution, half-bridge modular multi-
level converter (MMC), HVDC grid with overhead lines, MMC. introduced in 2001, is considered to be the most promising
VSC topology [4][6]. Fig. 1 shows the basic structure of a
I. INTRODUCTION three-phase MMC. The converter consists of six symmetrical
arms, and each arm has a series connection of N nominally
ITH the development of power electronic technology,
W the high-voltage direct current (HVDC) system based
on voltage-source converter (VSC) has attracted widespread
identical submodules (SMs) and one inductor. Because of the
modular construction, the series connection of power electronic
devices is avoided and the difficulty in manufacturing is reduced
attention. Compared with the HVDC system based on line-
[7][9]. The MMC-based HVDC system can provide excellent
commutated converter (LCC), VSC-HVDC can operate more
output voltage waveforms [10][12] and has been widely used
flexibly. In the VSC-HVDC system, the active and reactive
in commercial projects.
power of each terminal can be controlled separately, and the
In contrast to the ac system, the impedance of dc system is
converter is fit to constitute HVDC grids [1][3]. All these char-
much lower. Once a dc-side fault occurs, the malfunction will
acters make it a feasible solution to manage the future power
spread rapidly [13]. Therefore, the fault protection of dc lines
system in a secure and cost-effective manner.
should be enhanced. In practical projects, the converter is usu-
ally composed of half-bridge SMs. However, the MMC-HVDC
Manuscript received July 8, 2015; revised September 14, 2015 and November system with conventional half-bridge SMs lacks the capability
15, 2015; accepted March 7, 2016. Date of publication March 10, 2016; date of
current version November 11, 2016. This work was supported by the Headquar-
of dc fault clearance [14]. In order to guarantee the operating
ters Research Projects of State Grid Corporation of China (SGCC-HRP031- security of the system, underground or subsea cables should
2015). Recommended for publication by Associate Editor M. A. Perez. be employed. If this kind of topology is adopted to constitute
G. Liu, Z. Xu, Z. Zhang, and G. Tang are with the Department of Electri- HVDC grids, the dc transmission system will be a big spending.
cal Engineering, Zhejiang University, Hangzhou 310027, China (e-mail: liu-
gaoren@zju.edu.cn; xuzheng007@zju.edu.cn; 3071001296zhang@zju.edu.cn; Hence, it is necessary to enhance the HVDC system to make it
tanggeng7@zju.edu.cn). not only have the dc fault-handling capability but also suitable
F. Xu is with the State Grid Zhejiang Electric Power Research Institute, for overhead lines.
Hangzhou 310027, China (e-mail: xuf_1988@163.com).
Generally, there are two main methods to handle the dc-
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org. side short-circuit faults. The first one is to replace half-bridge
Digital Object Identifier 10.1109/TPEL.2016.2540808 SMs with full-bridge SMs or clamp-double SMs which have

0885-8993 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications standards/publications/rights/index.html for more information.
932 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 32, NO. 2, FEBRUARY 2017

the capability of dc fault clearance [15][17]. However, more

power electronic devices are needed and the device cost and
power losses increase accordingly. Under the same conditions,
the converter based on full-bridge SMs needs twice Insulated
Gate Bipolar Transistor (IGBT) modules and the power losses
increase by about 100%; the converter based on clamp-double
SMs needs 1.25 times the previous amount of IGBT modules
and the power losses increase by about 35% [18]. The drawbacks
mentioned above increase the cost of the system, especially in
long-term operation.
The other solution is to employ the HVDC circuit breaker
[19][21]. In November 2012, a hybrid HVDC breaker for
HVDC applications was released [22]. Because of the hybrid
design, the breaker has negligible conduction losses, while pre-
serving ultra-fast current interruption capability. However, the
breaker is not cost effective. In order to maintain the reliability
of HVDC grids, the circuit breaker should be placed at each end
of the transmission lines. As for the HVDC grid, which may
be the main form of the HVDC system in the future [23], [24],
the number of transmission lines will increase. Accordingly,
more circuit breakers will be required and this will lead to a
huge cost.
The feasibility of future HVDC grids depends largely on their
capabilities to withstand dc-side faults. In order to overcome
the obstacles mentioned above, an assembly HVDC breaker
and the corresponding control strategy are proposed in this pa-
per. The assembly HVDC breaker uses the design of the hybrid
HVDC breaker for reference. It can isolate the dc-side short-
circuit fault with competitively low cost and the operating speed
is satisfying. Compared with the existing two solutions, the so- Fig. 2. SM topologies. (a) Half-bridge SMs. (b) Full-bridge SMs. (c) Clamp-
lution based on assembly HVDC breakers is more suitable for double SMs.
the HVDC grid with overhead lines. The rest of this paper is
organized as follows. The two solutions based on SMs that have
dc fault clearance capabilities and hybrid HVDC breakers are Hence, full-bridge SMs and clamp-double SMs, which have
introduced in Section II and Section III, respectively. Section IV dc fault clearance capabilities, can be employed. The topologies
introduces the basic structure of the assembly HVDC breaker of the two kinds of SMs are shown in Fig. 2(b) and (c). When a
and the corresponding control strategy. The comparative analy- short-circuit fault occurs at the dc side, all of the IGBTs will be
sis of the three solutions is also detailed in this section. To verify blocked and reverse voltages will be generated [27]. The fault
the validity and the feasibility of the proposed method, the sim- current will be suppressed to zero in a very short time. This
ulation studies in PSCAD/EMTDC are presented in Section V. kind of solution embeds the dc fault clearance capability into
The conclusions are given in Section VI. the converter; thus, the overhead lines can be adopted.
The main constraint of the full-bridge SM is that the de-
vice cost and power losses are extraordinarily high. Under the
II. SOLUTION BASED ON SMS THAT HAVE DC FAULT same conditions, the converter based on full-bridge SMs needs
CLEARANCE CAPABILITIES twice IGBT modules and the power losses increase accordingly.
Hence, the clamp-double SM is a better alternative. Compared
The SM is the heart of the converter. In applications, the to the half-bridge MMC with the same number of voltage levels,
converter is usually composed of half-bridge SMs. As shown its device cost and power losses increase, but are far lower than
in Fig. 2(a), the half-bridge SM is composed of two IGBT those of the full-bridge MMC. The clamp-double MMC guaran-
switches, two antiparallel diodes, and a capacitor. Although this tees the security with competitively low cost and is a promising
kind of construction can effectively reduce the device cost and alternative to the traditional MMC with half-bridge SMs.
power losses, it cannot block the dc fault current. When a short-
circuit fault occurs at the dc side, the fault current will flow
from the ac side toward the dc side through the antiparallel III. SOLUTION BASED ON HYBRID HVDC CIRCUIT BREAKERS
diodes [25]. In order to reduce the probability of dc-side short- Unlike in traditional ac systems, the dc-side fault current
circuit fault, underground or subsea cables which have high of the HVDC system does not have the natural zero crossing
reliability are often adopted. Although cables are seldom short point and the arc is harder to be extinguished. Although existing
circuited in comparison to overhead lines [26], the cost of the mechanical HVDC breakers are capable of interrupting fault
dc transmission system will remarkably increase, especially in currents, they are too slow to fulfill the security requirements of
meshed HVDC grids. the HVDC grid [28]. The semiconductor-based circuit breaker
LIU et al.: ASSEMBLY HVDC BREAKER FOR HVDC GRIDS WITH MODULAR MULTILEVEL CONVERTERS
Fig. 3. Structure of the hybrid HVDC breaker.
can satisfy the requirement of operational speed, but the transfer
losses are unacceptable. In order to interrupt the dc-side fault
rapidly with competitively low cost, the hybrid HVDC breaker
is developed [22], [29].
The hybrid HVDC breaker has the advantages of both two
kinds of breakers, and the basic structure is shown in Fig. 3. The
hybrid HVDC breaker consists of a main semiconductor-based
circuit breaker (MB) and a bypass formed by a semiconductor-
based load commutation switch (LCS) in series with an ultra-
fast disconnector (UFD). It has been verified that the maximum
breaking current is over 9 kA and a typical short-circuit fault
can be isolated within 5 ms.
In normal operation, the current will only pass through the
LCS and the UFD. When a dc-side fault is detected, the LCS
will open immediately and the current will be commutated to the
MB. Then the UFD will open within 2 ms and isolate the LCS
from the faulted line. With the UFD in open position, the MB
will break the current. Finally, the disconnecting circuit breaker
will open and isolate the faulted line from the HVDC grid.
In the aspect of power losses, the breaker performs well. The
required voltage rating of the LCS is low and the maximum
voltage that the LCS bears is typically in the kilovolt range for
a 320 kV HVDC breaker. Thus, the required number of inserted
IGBT modules is significantly reduced. Since there is no cur-
rent passing through the MB in normal operation, the power
losses are fairly low. However, in the aspect of device cost, the
breaker is not good enough. The MB will be exposed to the
maximum pole-to-ground voltage during the current breaking
and the current flowing through the breaker can reach as high as
9 kA. To maintain the full-voltage and current-breaking capa-
bility, a large number of IGBT modules are required.
It should be noticed that the required number of hybrid HVDC
breakers is not determined by the number of converters but by
the number of dc lines. In the future, a typical HVDC grid will
consist of several converters and the dc lines will be meshed.
From the point of view of the reliability, the breaker should be
configured at both ends of each dc line. Therefore, more circuit
breakers will be required and the cost will increase drastically.
IV. SOLUTION BASED ON ASSEMBLY HVDC
CIRCUIT BREAKERS
A. Basic Structure of Assembly HVDC Breakers
In order to overcome the drawbacks noted earlier, an assembly
HVDC breaker with the dc fault clearance capability is proposed
here. The assembly HVDC breaker uses the design of the hy-
brid HVDC breaker for reference, and it is more suitable for
HVDC grids with half-bridge MMCs and overhead lines. Take
a monopolar HVDC system as an example, the basic structure
933
Fig. 4. Structure of the assembly HVDC breaker. (a) General configuration.
(b) Structure of part B.
of the assembly HVDC breaker is illustrated in Fig. 4. The main
components are as follows:
1) Active short-circuit breaker (ASCB): The ASCB is the
core component and determines the current breaking ca-
pability of the assembly breaker. Similar to the MB of
the hybrid HVDC breaker, the ASCB needs to withstand
the maximum pole-to-ground voltage. The ASCB consists
of several breaker cells with individual arrester banks. In
order to fulfill the requirement of the voltage rating, a se-
ries connection of IGBT modules are configured in each
breaker cell. Parallel connection of IGBT modules in-
creases the rated current of the ASCB, so the maximum
current breaking capability is enhanced. Due to the large
di/dt stress during the current breaking, the mechanical
design with low stray inductance is required [22]. Con-
necting point A, the point where the ASCB is connected
to the system, is illustrated in Fig. 4(a). The ASCB will
close immediately when a dc-side short-circuit fault is
detected, so the connecting point A can be considered as
a new short-circuit point. Since the short-circuit point is
created, the fault current that flows from the converter will
be shunted into the ASCB and then interrupted through a
series of operations.
2) Main mechanical disconnector: The mechanical discon-
nector here should also have the full voltage withstanding
capability. The mechanical disconnector opens at zero
current with low voltage stress and is used to isolate the
faulted line from the HVDC grid.
3) Main breaker: The structure of the main breaker is simi-
lar to the ASCB, but with less power electronic devices.
The main breaker contains two breaker cells and each
cell is required to break the current in either direction.
The function of the main breaker is to isolate the fault
934 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 32, NO. 2, FEBRUARY 2017

point from the system and commutate the current into

the ASCB. The main breaker is closed during normal op-
eration. Since it does not need to have the capability of
withstanding high voltage, only a small quantity of IGBT
modules is required. Hence, the transfer losses are reduced
significantly.
4) Accessory discharging switch (ADS): The ADS consists
of a semiconductor-based switch in series with a resis-
tance. The point where the ADS is connected to the system
is illustrated in Fig. 4(b) and can be defined as connect-
ing point B. The ADS needs to withstand high voltage
and the operational speed has to be guaranteed. Since the
switch does not need to have the current breaking capa-
bility, the thyristors which are durable and economical
are employed. Similar to the ASCB, the ADS will also
close immediately when a dc-side short-circuit fault is
detected, and the connecting point B can be considered
Fig. 5. DC fault isolation process.
as another short-circuit point. The resistance is used to
limit the maximum current that flows through the main
breaker, and dissipate the energy stored in the faulted line
faster. The main function of the ADS is to reduce the Step 3: After a short delay, the mechanical disconnector opens
voltage across the main breaker before the main breaker at t3. The physical isolation between the converter and the
opens, and provide an accessory discharging circuit after faulted line is realized and the dc fault current flowing from
the main breaker is opened. the ac side is blocked.
The ASCB is the part A of the breaker and placed between
Step 4: The ASCB opens at t4 . The remaining energy will be re-
the converter and the dc bus. The components left are the part
leased through the arrester banks. The current flowing through
B and configured at each end of the dc lines. The number of
the ASCB decreases to 0 at t5 and the dc fault is isolated
required ASCBs is determined by the number of converters.
completely.
Since there is one converter in Fig. 4, only one ASCB is needed.
The number of part B is determined by the number of the dc
The whole process is shown in Fig. 5. Generally speaking,
lines. If there are m lines connected to the dc bus, m part Bs are
for a HVDC grid, the process of fault clearing has to be within
required.
5 ms. If the speed of fault isolation is not fast enough, the healthy
station will be disturbed and the voltage collapse will probably
B. Strategy for DC Fault Isolation happen. Hence, the requirement of 5 ms for the fault clearing
Take a monopolar HVDC grid as an example. The dc fault- time is a typical guideline in the design of HVDC breakers [22].
handling strategy based on assembly HVDC breakers is as As for the assembly HVDC breaker, the interval between t1 and
follows: t2 is 250 s, t2 and t3 is 2 ms, t3 and t4 is 50 s, and t4 and t5 is
12 ms. The entire time of the proposed method is within 5 ms.
Step 1: The dc-side short-circuit fault happens at t0 . After the The proposed dc fault-handling strategy is fast enough to fulfill
fault is detected at t1 , the ASCB and the ADS close immedi- the requirements of a reliable HVDC grid.
ately. The dc-current flowing from the converter injects into It should be noticed that the voltage at the connecting point
the ASCB, the ADS and the fault point at the same time. A can be considered as the dc-bus voltage. The dc-bus voltage
The current flowing through the main breaker is mainly de- will drop to nearly zero after the ACSB is closed. The pro-
termined by the resistance of the ADS and the resistance posed solution will create a transitory short-circuit fault at the
between the fault point and the ground, and can be limited dc bus. If the original short-circuit fault occurring in the dc line
at a relatively low level. Considering the on-state voltage of is a metallic ground fault, the dc-bus voltage will have dropped
semiconductor devices and the resistance of the ADS, the to a relatively low level before the ACSB is closed. On this
voltages at the connecting points A and B are not same and occasion, there is no obvious difference in the system perfor-
both slightly larger than zero. Hence, the voltage across the mance whether the ACSB is closed or not. If the resistance be-
main breaker is not zero, but can be guaranteed under a fairly tween the fault point and the ground is quite large, the proposed
low level. solution will aggravate the influence of the fault to some extent.
However, the duration of the active short-circuit operation is
Step 2: The main breaker opens at t2 and the current flowing
only around 2 ms, which is acceptable for the HVDC system,
through it decreases to zero sharply. The energy stored in the
even if the dc buses are weak. Because of the reactor, the energy
dc line is released through the ADS and the fault point. Since
stored in the SMs will not be released that soon. The dc-voltage
the ADS contains a resistance, the voltage at the connecting
at point C, which is illustrated in Fig. 4(a), will be maintained
point B will not be zero. By now, the converter has been
at a relatively high level. The dc-bus voltage will recover to the
isolated from the faulted line preliminarily, and the dc-current
rated level rapidly after the ASCB opens, and the stability of the
flowing from the converter only injects into the ASCB.
entire HVDC grid will not be compromised notably.
LIU et al.: ASSEMBLY HVDC BREAKER FOR HVDC GRIDS WITH MODULAR MULTILEVEL CONVERTERS 935

TABLE I TABLE III

COMPARISON OF MMC WITH DIFFERENT SMS COMPARISON OF THREE DIFFERENT SOLUTIONS

Original Condition Solution I Solution I Solution II Solution III

MMC configuration Half-bridge SM Clamp-double SM
3 kA 9 kA 3 kA 9 kA
Number of SMs per arm 236 118
Extra power 708 2 472 m 1416 m 236 IGBTs 708 IGBTs
Number of IGBTs per SM 2 4+ 1 electronic devices IGBTs IGBTs IGBTs + 100 m + 100 m
Number of IGBTs per arm 472 472 + 118 2 thyristors thyristors
Number of extra IGBTs per station 0 708 2 Extra Power loss Around Negligible Negligible
35%
Converter Need be Need not be blocked Need not be blocked
performance during blocked
TABLE II the clearance
COMPARISON OF SOLUTIONS II AND III

Solution II Solution III

series index of IGBT modules is 236. Since the breaker is
Current breaking 3 kA 9 kA 3 kA 9 kA 3 kA 9 kA
capability
designed to break the current in either current direction, the
Main investment MB ASCB ADS
direction index is 2. The peak current of the IGBT module is 3
kA; however, the required breaking capability is usually larger
Required m 1 m
number than that (e.g., a typical HVDC system is introduced in [22] and
Series index 236 236 100 the minimum required breaking capability is 9 kA) (see Table
Direction index 2 1 1 II). If the required breaking capability is 3 kA, the parallel
Parallel index 1 3 1 3 1 connection of IGBT modules is not required and the parallel
Number of 472 m 1416 m 236 708 100 m thyristors index is 1. However, if the required breaking capability is 9 kA,
required IGBTs IGBTs IGBTs IGBTs
IGBTs/thyristors
the parallel connection is required and the parallel index is 3.
Hence, 472 and 1416 IGBT modules per breaker are needed,
respectively, under the two conditions. In normal operation,
there is no current passing through the MB. Therefore, the
C. Comparison of the Three Solutions power losses are much lower than that of solution I and can
As shown in Fig. 4, take a monopolar HVDC converter con- be ignored.
nected to m dc lines as an example. Assume that the dc-bus volt- In solution III, the converter consists of half-bridge SMs,
age is 400 kV, and the HiPak 5SNA 1500E330305 is adopted and assembly HVDC breakers are employed. Unlike the hybrid
as the IGBT module. The device costs and power losses of the HVDC breaker, the components of the assembly HVDC breaker
three different solutions are compared as follows. can be configured separately. Since there are one converter and
Under the original condition, the converter employs half- m dc lines, the required number of part-A and part B is one
bridge SMs only. Since the rated collector-emitter voltage of and m, respectively. The ASCB is the main investment in this
the IGBT module is 3.3 kV, the rated capacitor voltage is set as solution. Similar to the MB of the hybrid HVDC breaker, in
1.7 kV. Therefore, the required number of half-bridge SMs per order to possess the full voltage and current breaking capabil-
arm is 236. Since each SM contains two IGBT modules, 472 ity, the series index is 236 and the parallel index is 1 if the
IGBT modules are required per arm. required breaking capability is 3 kA and 3 if the required break-
In solution I, the converter employs clamp-double SMs, and ing capability is 9 kA. During the current breaking, the ASCB
the hybrid HVDC breaker or the assembly HVDC breaker is not does not need to break the current in either direction. Hence,
needed. The comparison of the original half-bridge MMC and the direction index is 1. The ADS also needs to withstand the
the clamp-double MMC is shown in Table I. It can be seen that maximum pole-to-ground voltage. Assuming the thyristor 5STP
118 clamp-double SMs are required per arm in this solution. 37Y8500 with 8.0 kV voltage rating is employed, the voltage
Since the middle switching pair is continuously on in normal that a single thyristor bears should be 4.0 kV. Hence, the series
operation, the average current that passes through it is doubled. index is 100. The rated current of the thyristor is high enough,
The needed IGBT per middle switching pair can be considered so there is no need to connect the thyristors in parallel even if
as two, and consequently, 236 more IGBT modules are needed the required breaking capability is 9 kA. The cost of the main
per arm and 1416 more per station. Since the clamp-double SMs breaker of the assembly HVDC breaker is much lower. Since
are employed, the power losses in normal operation will increase the main breaker does not need to withstand high voltage during
accordingly. It should also be noticed that all the converters will the current breaking, only a small quantity of IGBT modules
be blocked when the fault occurs, and the effect caused by the is required. The current only pass through the main breaker in
fault will be expanded. normal operation, so the power losses in solution III are as low
In solution II, the converter consists of half-bridge SMs, and as that in solution II.
hybrid HVDC breakers are employed. Since the converter is The comparison of the three solutions is shown in Table III.
connected to m dc lines, m circuit breakers should be configured. In the aspect of device cost, it can be seen that if m is small or the
The MB is the main investment in this solution and it needs to required breaking capability is low, the two solutions based on
withstand the maximum pole-to-ground voltage. If the voltage HVDC breakers need less electronic devices. As the number of
that a single IGBT module bears continues to be 1.7 kV, the connected dc lines rises, the device costs of solutions II and III
936 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 32, NO. 2, FEBRUARY 2017

Fig. 6. Four-terminal monopolar HVDC grid.

increase accordingly while that of solution I remains unchanged. TABLE IV

MAIN CIRCUIT PARAMETERS OF THE TEST SYSTEM
In HVDC grids, one converter is usually connected to more than
two dc lines. At this time, the device cost of solution I is lower.
However, solution I does not performs well in the aspect of Items Values
power losses. Compared to the half-bridge MMC with the same DC side DC-bus voltage 400 kV
number of voltage levels, the power losses increase by about Length of dc line 12 100 km
35%. In addition, all the converters have to be blocked when Length of dc line 13 100 km
Length of dc line 24 100 km
fault occurs, and this will impair the stability of the connected
Length of dc line 34 150 km
ac system.
AC side Active power of MMC-1 400 MW
The system performance of solutions II and III in long-term Active power of MMC-2 80 MW
operation is better than that of solution I. The converter need Active power of MMC-3 240 MW
not be blocked during the fault clearance process and the extra AC system voltage (L-L, RMS) 115 kV
power loss is negligible. The advantage will be more conspicu- AC system inductance 10 mH
Transformer capacity 1.2 p.u.
ous if the required breaking capability is low. Even though the Transformer ratio 110 kV/200 kV
manufacturing is difficult, the two solutions based on HVDC Transformer leakage inductance 19.2 mH
breakers are more suitable for the future HVDC system. Be- Converter Number of SMs per arm 236
tween the two solutions, the device cost of solution III is SM capacitance 8000 F
much lower. The proposed assembly HVDC breaker can han- Capacitor voltage 1.7 kV
Arm inductance 76 mH
dle the dc-side fault with competitively low cost. Hence, it is
Transmission line + ve Sequence R 9.32e-3 s/km
more suitable for HVDC system with overhead lines, especially
+ ve Sequence L 8.50e4 H/km
the meshed HVDC grid. + ve Sequence C 1.36e8 F/km

V. CASE STUDY
A. Study System
To verify whether the proposed method is valid and feasi-
ble, a four-terminal monopolar HVDC grid, which is shown
in Fig. 6, is established with the time-domain simulation tool
PSCAD/EMTDC.
The main circuit parameters are listed in Table IV. MMC-
4 controls the dc-side voltage and the reactive power and is
rated at 600 MVA. MMC-1, MMC-2, and MMC-3 regulate
the active and reactive power and are all rated at 400 MVA.
All the converters are connected by overhead lines. The active
power delivered to the dc-network by MMC-1 and MMC-2 is
400 and 80 MW, respectively, whereas MMC-3 delivers 240
MW to the ac grid. A smoothing reactor of 200 mH is used
between the converter and the dc bus to limit the derivative of
the fault current. The Bergeron model is adopted for describing
the transmission line.
The parameters of the assembly HVDC breaker are listed in
Table V. 5SNA 1500E330305 and 5 STP 37Y8500 are chosen as
the IGBT module and the thyristor, respectively. The principle
for configuration is in accordance with the analysis in the third
part of Section IV.
B. Performance of the Assembly HVDC Breaker
A positive pole-to-ground fault is applied at t = 2.0 s at the
middle of dc line 12 and the resistances between the fault point
and ground are 0.01, 50, and 200 , respectively. In solution III,
the assembly HVDC breakers are used to handle the dc fault.
The dynamic response of the assembly HVDC breaker is shown
in Fig. 7.
The currents flowing through the ASCB and the arrester,
the main breaker and the arrester, and the ADS are shown in
Fig. 7(a), (b), (c), (d), and (e), respectively. The current that
LIU et al.: ASSEMBLY HVDC BREAKER FOR HVDC GRIDS WITH MODULAR MULTILEVEL CONVERTERS 937

TABLE V
PARAMETERS OF THE ASSEMBLY HVDC BREAKER

Items Values

ASCB Number of IGBT modules 708

Arrester protective voltage rating 440 kV
Mechanical disconnector Close resistance 0.005
Main breaker Number of IGBT modules 18
Arrester protective voltage rating 15 kV
ADS Number of thyristors and antiparallel diodes 100
Arrester protective voltage rating 440 kV
Resistance 5

injects into the fault point is shown in Fig. 7(f). Fig. 7(g) and (h)
shows the voltages at the connecting points A and B. Fig. 7(i)
shows the voltage across the main breaker. Fig. 7(j) shows the
voltage at point C.
As can be seen from Fig. 7, the fault current increases sharply
after the fault occurred. The distance between the fault point
and MMC-1 is 50 km; hence, the assembly HVDC breaker
is affected at about t = 2.00017 s. The voltages at the connecting
points A and B drop at the same time. The smaller the fault
resistance is, the larger the voltage drops are. On this occasion,
the ASCB and the ADS are open and the current only pass
through the main breaker.
The fault is detected at t = 2.001 s, and the ASCB and the
ADS close at the same time. The current injecting into the
fault point decreases after a short delay and part of the current
is shunted into the ASCB and the ADS. Since the equivalent
resistance of the ADS is much larger than that of the ASCB, the
current flowing into the ADS is below 60 A. The voltages at the
connecting points A and B drop to almost zero at this time, and
the voltage across the main breaker is around 0.15 kV. Because
of the smoothing reactor, the voltage at point C drops slightly
and is still maintained above 310 kV.
The main breaker opens at t = 2.00125 s. The current flowing
through the main breaker becomes zero and the current inject-
ing into the fault point decreases obviously. Because of the
line inductance, the current flowing through the ADS reverses
and increases to as high as 3 kA when the fault resistance is
0.01 . Consequently, the voltage that the main breaker bears
rises, but is limited to 15 kV because of the arrester. The
mechanical disconnector opens after a delay of 2 ms. By now,
the faulted line has been isolated from the converter physically.
The dc-current flowing from MMC-1 only injects into the ASCB
and the energy stored in the faulted line dissipates through the
Fig. 7. Dynamic performance of the assembly HVDC breaker. (a) Cur-
ADS and the fault point. The time of fault energy dissipating is rents of ASCB. (b) Currents of ASCB arrester. (c) Currents of main breaker.
determined by the equivalent resistance of the discharge circuit. (d) Currents of main breaker arrester. (e) Current of ADS. (f) Current of fault
When the fault resistance is 0.01 , the time that the fault energy point. (g) Voltages at connecting point A. (h) Voltages at connecting point B.
takes to dissipate is the longest, which is about 30 ms. (i) Voltage across main breaker. (j) Voltage at point C.
At about t = 2.0033 s, the ASCB opens with the mechan-
ical disconnector in open position. The current injecting into fault is isolated completely. During the fault isolation, the max-
the ASCB becomes zero and the voltage that the ASCB bears imum current flowing through the ASCB is about 9 kA.
rises sharply. The maximum voltage is limited to 625.2 kV be- It can be seen that the fault with the lowest fault resistance
cause of the arresters and the energy dissipates in the next 2 ms. is the most serious one. The maximum current that injects into
The voltage at point C recovers to the rated level rapidly, and the fault point, the maximum current that flows through the
the maximum voltage is around 420 kV. At about t = 2.005 s, main breaker and the maximum current that flows through the
the current passing through the arresters becomes zero and the ADS are higher than those in the other two situations. Hence,
938
TABLE VI
PARAMETERS OF THE HYBRID HVDC BREAKER
Items
MB Number of IGBT modules
Arrester protective voltage rating
Mechanical disconnector Close resistance
LCS Number of IGBT modules
Arrester protective voltage rating
Fig. 8. Dynamic performance of the hybrid HVDC breaker.
the current breaking capability of the main breaker and the
ADS should be designed under this situation. The maximum
current that flows through the ASCB is also affected by the
fault resistance, but the effect is not that obvious. The factor
that matters most is the value of the smoothing reactor. Hence,
the smoothing reactor should not be too small, or the required
current breaking capability will increase.
C. Performance of the Test Systems With Two Kinds
of Breakers
Consider the most serious fault. Assume that a positive pole-
to-ground fault is applied at t = 2.0 s at the middle of dc line 12
and the resistance between the fault point and ground is 0.01 .
In solution II, the hybrid HVDC breakers are used to handle the
dc fault. The principle for configuration is in accordance with
the analysis in Section III. The parameters of the breaker are
listed in Table VI. The dynamic response of the hybrid breaker
in the faulted line is shown in Fig. 8.
As can be seen from Fig. 8, the current flowing through
the LCD increases sharply after the fault occurs. The fault is
detected at t = 2.001 s and the LCD opens after a delay of
250 s. The current is commutated to the MB immediately.
After a delay of 2 ms, the MB breaks the fault current with the
UFD in open position, and the energy dissipates in the next 2 ms
through the arrester. The fault isolation can be achieved within
5 ms, and the maximum current flowing through the breaker is
about 9 kA.
The comparison of the dc-bus voltages in different solutions
is shown in Fig. 9. Since the fault resistance is small, the voltages
at dc bus 1 and dc bus 2 drop sharply after the fault occurs. At t =
2.001 s, the time when the ASCB is about to close, the voltages
are only around 100 kV. Hence, the close of ASCB will not
cause much influence in the system performance compared with
solution II. During the fault isolation, the maximum voltages at
dc bus 1 and 2 in solution II are 604.6 and 602.6 kV, respectively,
which are 20.6 and 18.3 kV lower than those in solution III.
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 32, NO. 2, FEBRUARY 2017
Values
1416
440 kV
0.005
6
5 kV
Fig. 9. Comparison of the dc-bus voltages. (a) Voltages at dc bus 1.
(b) Voltages at dc bus 2. (c) Voltages at dc bus 3. (d) Voltages at dc bus 4.
However, the maximum voltages at dc bus 3 and dc bus 4 in
solution II are 626.6 and 626.8 kV, respectively, which are 35.0
and 35.7 kV higher than those in solution III. All the dc-bus
voltages will recover to the normal value in both solutions after
the breaker breaks the fault current, and the voltage collapse
will not happen.
The comparison of the dc-voltages at point C in different
solutions is shown in Fig. 10. It can be seen that at t = 2.001 s,
the dc voltages at point C drop by around 15 kV in solution
III after the ASCB is closed and then decrease smoothly. The
minimum voltages during the fault isolation in four stations are
316.2, 310.5, 324.9, and 330.7 kV, respectively. In solution II,
the fluctuations of the voltages are larger than those in solution
II. During the fault isolation, the minimum voltages in four
stations are 292.9, 288.5, 278.1, and 286.9 kV, respectively.
Similar to the dc-bus voltages, the voltages at point C can also
recover to the normal value in both solutions.
The comparison of the active power flow in the dc side is
shown in Fig. 11. P12 denotes the active power flowing from
MMC-1 to MMC-2 through the dc line 12, and P21 denotes the
active power flowing from MMC-2 to MMC-1 through the same
line. P13 , P24 , and P34 are defined in the same manner. It can be
seen that the active power through the faulted line becomes zero
in both solutions, and the power redistributes among the other
lines. The redistribution is smoother in solution III, especially in
the faulted line. There is no terrible fluctuation during the fault
clearance.
The comparison of the capacitor voltage in MMC-1 is also
demonstrated. As can be seen from Fig. 12, the capacitor volt-
ages in solutions II and III are almost the same. During the fault
LIU et al.: ASSEMBLY HVDC BREAKER FOR HVDC GRIDS WITH MODULAR MULTILEVEL CONVERTERS
Fig. 10. Comparison of the dc-voltages at point C. (a) In MMC-1. (b) In
MMC-2. (c) In MMC-3. (d) In MMC-4.
Fig. 11. Comparison of the power flow. (a) In solution II. (b) In solution III.
Fig. 12. Comparison of the SM capacitor voltage in MMC-1.
isolation, the capacitor voltages drop slightly and then recover
to the rated level.
Assuming the same fault is applied at t = 2.0 s at the middle
of dc line 12 and the fault resistance is 200 . The comparisons
of system performances in solutions II and III, including the
dc-bus voltages, the voltages at point C, the capacitor voltage in
939
Fig. 13. Comparison of the dc-bus voltages. (a) Voltages at dc bus 1.
(b) Voltages at dc bus 2. (c) Voltages at dc bus 3. (d) Voltages at dc bus 4.
MMC-1, and the active power flow in the dc side, are shown in
Figs. 13, 14, 15, and 16, respectively.
It can be seen that the system performances in solution III are
better than those in solution II. During the nonmetallic ground
fault, the fluctuations of the dc-bus voltages and the voltages
at point C are smaller, and the redistribution of active power
flow is smoother. Though the system performances are not as
good as those in solution II, the system can also ride through the
fault stably with the proposed assembly HVDC breakers. The
dc voltages at point C drop to around 340 kV after the ASCB is
closed, and the minimum voltages during the fault isolation in
four stations are 323.3, 317.8, 332.0, and 334.7 kV, respectively.
During the isolation, the capacitor voltage drops slightly and the
minimum value is around 1.53 kV. All these indices will recover
to the normal level after the breaker breaks the fault current.
From the comparisons shown above, it can be seen that
the proposed solution will not impair the stability of the en-
tire HVDC grid compared with the existing solution. Though
the close of ACSB will create a new short-circuit point at the dc
bus, the duration is short and the energy stored in the SMs will
not be released notably. The system can ride through the fault
stably, even if the dc bus is weak.
D. Parameter Selection of the ADS and the Main Breaker
The resistance of the ADS affects the maximum current that
flows through the main breaker and the maximum voltage that
the main breaker bears after it is just opened, and this is a
tradeoff.
Assuming the fault resistance is set as 0.01 and the
resistance of the ADS varies from 0 to 10 , the maximum
current that flows through the main breaker and the maximum
940
Fig. 14. Comparison of the dc-voltages at point C. (a) In MMC-1. (b) In
MMC-2. (c) In MMC-3. (d) In MMC-4.
Fig. 15. Comparison of the SM capacitor voltage in MMC-1.
Fig. 16. Comparison of the power flow. (a) In solution II. (b) In solution III.
voltage that the main breaker bears are shown in Fig. 17(a) and
(b). It can be seen that if the resistance is relatively small, the
maximum current flowing through the main breaker will be very
large and the parallel connection of IGBT modules will be re-
quired. However, if the resistance is relatively big, the maximum
voltage that the main breaker bears will be quite high and the
number of required IGBT modules will increase. Therefore, the
resistance of the ADS should not be too large or too small. When
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 32, NO. 2, FEBRUARY 2017
Fig. 17. Relationship between the resistance of the ADS and the dynamic
response of the system. (a) Maximum current flowing through the main breaker.
(b) Maximum voltage that the main breaker bears.
the resistance is larger than 5 , the decrease of the maximum
current is not obvious but the maximum voltage increases lin-
early. Hence, the resistance can be set as 5 . On this occasion,
the voltage that the main breaker bears is less than 16 kV. Since
the main breaker opens within 1 ms after a fault occurs, the fault
current flowing through the main breaker will not damage the
device in general. Therefore, the IGBT modules need not be
connected in parallel.
VI. CONCLUSION
In this paper, two existing methods to clear the dc-side fault,
employing SMs with dc fault-handling capabilities and employ-
ing hybrid HVDC breakers are discussed. On this basis, an
assembly HVDC breaker with dc fault clearance capability is
proposed as well as the corresponding control strategy. The as-
sembly HVDC breaker consists of an ASCB, a main mechanical
disconnector, a main breaker and an ADS. It can interrupt the
dc-side short-circuit fault with competitively low cost, and the
operating speed is fast enough.
A four-terminal monopolar HVDC grid with assembly HVDC
breakers and overhead lines is developed in PSCAD/EMTDC,
and the simulation result proves the validity and the feasibility.
In this method, the fault ride-through capability of the system
can be enhanced. Compared with the two existing solutions, the
proposed solution is more suitable for the meshed HVDC grid
with overhead lines.
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