RSM2011 Proc.

, 2011, Kota Kinabalu, Malaysia

Investigation of Effects of Nanowires Numbers in N-channel and

P-channel Nanowire Transistors on Nanowire-CMOS
Characteristics
Yasir Hashim, and Othman Sidek

Collaborative Microelectronic Design Excellence Centre(CEDEC), Engineering Campus, University

Science,Malaysia,14300, Nibong Tebal, Penang, Malaysia

Abstract This paper is to study the characteristics of

nanowire-CMOS and effect of increasing of numbers of II. SIMULATION
nanowires in transistors on the nanowire-CMOS characteristics.
This study used MuGFET simulation tool to produce the
characteristics of nanowire transistors and used as input to Table I
MATLAB software to produce the characteristics of Parameter Name N-nanowire P-nanowire
nanowire-CMOS. Increasing channel nanowires in P-channel Channel length(L) 30nm 30nm
transistor tends to improve the transfer characteristics of Source length 10nm 10nm
CMOS. Increasing channel nanowires in N-channel transistor Drain length 10nm 10nm
tends to poorer transfer characteristics of CMOS. Channel diameter(D) 20nm 20nm
Oxide thinness (SiO2) 2nm 2nm
Keywords: nanowire, CMOS, transistor, simulation, transfer Channel concentration 1*1010/cm3 1*1010/cm3
characteristics Source and drain 1*1020/cm3 1*1020/cm3
concentration (n-type) (p-type)
I. INTRODUCTION

A s the conventional silicon (MOSFET) approaches its

scaling limits. Many novel device structures are being
extensively explored, one of them. The silicon nanowire
transistor (SiNWT) has attracted broad attention from both the
semiconductor industry and academia [1-2].
Silicon nanowires are attracting significant attention from
the electronics industry due to the drive for ever smaller
electronic devices like transistors, diodes, resistors, and
capacitors. The operation of these future devices, and a wide
array of additional applications, will depend on the properties
of these nanowires [1-2]. A new generation of ultra small
transistors and more powerful computer chips using tiny
structures called semiconducting nanowires will be more
applicable in the future after more discoveries by researchers.
The fabrication of nanowire FETs is still a technology under
development that requires further innovations before
challenging state-of-the-art MOSFETs.
To understand device physics in depth and to assess the
performance limits of SiNWTs, simulation is becoming
increasingly important. Simulation tools can support the Fig.1 Schematic of a nanowire-CMOS circuit.
experimental work to accelerate the development of NW
FETs[3], reduce their cost, identify their strength and
weakness, and demonstrate their scalability down to the III. RESULTS
nanometers range[1,2,4] In Figs (2) and (3), it can be noting the drain current (Id)
drain voltage (Vd) characteristics for both types of transistors
P and N channel with single nanowire as the parameters in
Table I, MATLAB software designed to calculate output
(Vout-Vin) and (Iout-Vin) characteristics depending on Id-Vd

978-1-61284-846-4/11/$26.00 2011 IEEE 45

 RSM2011 Proc., 2011, Kota Kinabalu, Malaysia
characteristics of SiNWTs and results illustrates in Figs (1-7),
in Fig (4) shows it can be noting variation of output current
characteristics with single nanowire transistor's CMOS. Fig
(5) illustrates the shift of inflection point to the right with
increasing numbers of nanowires at P-channel transistor from
1 to 10 because of increasing in Id in P-channel transistor
tends to compensate lower mobility of carriers (holes) in
P-channel nanowires. While the characteristics shifted lift if
the nanowires increased at N-channel transistor as shown in
Fig (6). Fig (7) shows that if we increased nanowires in both
transistors, the current will be increased with no effect on
voltage characteristics.
Fig.2 Output characteristics of N-channel nanowire transistor
with Vd=0 to 1V step 0.5V.
Fig.3 Output characteristics of P-channel nanowire transistor.
46
Fig.4 Transfer and current characteristics with single nanowire for
two transistor on nanowire CMOS.
IV. CONCLUSIONS
We used (MuGFET) simulation tool to calculate the N and
P-channel nanowire transistor and enter it to MATLAB
software to study the effect of increased numbers of nanowires
in transistors of nanowire-CMOS, the best transfer
characteristics for inflection voltage (near to half input
voltage) was done by increasing nanowires of P-channel
transistor as possible because of lower mobility of carriers
(holes) in P-channel nanowires compared to the carriers
(electrons) in N-channel nanowire transistor.
REFERENCES
[1] K. Nehari, N. Cavassilas, J.L. Autran, M. Bescond, D. Munteanu, M.
Lannoo, Influence of band-structure on electron ballistic transport in
Silicon nanowire MOSFETs: an atomistic study, Proc. ESSDERC
2005, p. 229, 2005.
[2] J. Wang, E. Polizzi, M.S. Lundstrom, A three-dimensional quantum
simulation of silicon nanowire transistors with the effective-mass
approximation, J. Appl. Phys., vol. 96, p.2192, 2004.
[3] M. Bescond, K. Nehari, J.L. Autran, N. Cavassilas, D. Munteanu, M.
Lannoo, 3D quantum modeling and simulation of multiple-gate
nanowire MOSFETs, IEDM Tech. Dig., p.617, 2004.
[4] Ramses V Martnez , Javier Martnez and Ricardo Garcia, Silicon
nanowire circuits fabricated by AFM oxidation nanolithography,
Nanotechnolog Vol. 21, No. 24 ,2009.
[5] https://nanohub.org
[6] SungGeun Kim; Gerhard Klimeck; Sriraman Damodaran; Benjamin P
Haley (2011), "MuGFET," DOI: 10254/nanohub-r3843.5. (DOI:
10254/nanohub-r3843.5).
 RSM2011 Proc., 2011, Kota Kinabalu, Malaysia

Fig.5 Transfer and current characteristics with 1 to 10 nanowires for P-channel transistor in nanowire-CMOS.

Fig.6 Transfer and current characteristics with 1 to 10 nanowires for N-channel transistor in nanowire-CMOS.

Fig.7 Transfer and current characteristics with 1 to 10 nanowires for boath transistors in nanowire-CMOS.

47