DEPARTMENT OF ELECTRONICS ENGINEERING,

TEZPUR UNIVERSITY
DESIGN OF HIGH GAIN OPERATIONAL AMPLIFIER

A Project Report Submitted in Partial Fulfillment of

the Requirements for the Degree of

Bachelor of Technology
in
Electronics and Communication Engineering
by

Anupam Boro (Roll No. ELB10028)

Uttam Chetri(Roll No.ELB10059)
Chunchu Kartik(Roll No.ELB)

DEPARTMENT OF ELECTRONICS AND

COMMUNICATION ENGINEERING
SCHOOL OF ENGINEERING
 TEZPUR UNIVERSITY
TEZPUR NOVEMBER 2013

Department of Electronics and Communication Engineering

Tezpur University
Tezpur, November 2013

Certificate

This is to certify that this thesis entitled Design of Hgh gain Operational amplifier by
Anupam Boro (Roll No. ELB10028),Uttam Chetri(Roll No. ELB10059) and Chunchu
Kartik(Roll No. ) submitted in partial fulfillment of the requirements for the degree of Bachelor
of Technology in Department of Electronics and Communication Engineering at Tezpur
University, Tezpur, during the academic year 2013-14, is carried out under our guidance and
supervision. The work contained in this report has not been submitted elsewhere for a degree.

(Project Supervisor) Miss. Priyanka Kakoty

Assistant Professor
 TEZPUR UNIVERSITY
(A CENTRAL UNIVERSITY)
SCHOOL OF ENGINEERING
DEPARTMENT OF MECHANICAL ENGINEERING
NAPAAM, DIST: SONITPUR, PIN:784028
ASSAM, INDIA

CERTIFICATE
This is to certify that we have examined this report on DESIGN OF OPERATIONAL
AMPLIFIERS and here by accord or approve of it as a study carried out and presented in a
manner required for its acceptance and fulfillment for the Bachelor Degree (Electronics and
Communication Engineering) for which it has been submitted by

Anupam Boro (ELB10028)

Uttam Chetri (ELB10059)
Chunchu Kartik(ELB )

This approval does not necessarily accept every statement made, opinion expressed or
conclusion drawn as recorded in this thesis. It only signifies the acceptance of this thesis for
which it has been submitted.

The Viva-Voce examination of above candidates of 7th semester B.Tech (Mechanical

Engineering) of their project has been held on .. and found satisfactory.

.
Signature of Head of Department Signature of Examiner
 ACKNOWLEDGMENT

We extend our sincere thanks to Miss Priyanka Kakoty, Assistant Prof. Dept. of Electronics and
communication Engineering, Tezpur University for her guidance. We would also like to sincerely thank
Prof. J. C. Dutta (HOD Dept. of ECE) for his constant support and guidance.
 Abstract

In linear integrated circuit design, design of a high gain (open loop) operational amplifier
by using less possible passive component is a important step so that op-amp can be designed in
less area and closed loop gain become nearly insensitive to its varying parameters like
temperature, frequency, mass production technique etc.

In our project entitled Design of High gain Operational Amplifier we have designed a
multistage BJT operational amplifier having 3 stages namely- Differential stage, Level Shifter
and the Output stage with less possible passive components. We have theoretically calculated
the various parameters of an operational amplifier as Gain, CMRR, Bandwidth etc .For
Simulation of our Circuit we used MULTISIM 12.0(student version) software.
We have also practically calculated various parameters of an operational amplifier and found
that they are almost matched with the theoretically calculated values. For proper functioning of
the operational amplifier we have ensured that each transistor used does not enter saturation
level.
 Chapter 1
INTRODUCTION

1.1 Background
The operational amplifier is a versatile device that can be used to amplify both dc as well as
ac input signals and was originally designed for performing mathematical operations such as
addition, subtraction, multiplication and integration. Thus the name operational amplifier
abbreviated to op-amp.

Since op-amp is a multistage amplifier, it can be represented by a block diagram as shown in

fig.1.The input stage is generally a dual input balanced output differential amplifier. This stage
generally provides most of the voltage gain of the amplifier and also establishes the input
resistance of the op-amp. The intermediate stage is usually another differential amplifier, which
is driven by output of the first stage. Because direct coupling is used, the dc voltage at the output
of the intermediate stage is well above ground potential. Therefore, generally the level shifting
circuit is used after the intermediate stage to shift the output of the intermediate stage down to
zero. The final stage is generally a push pull complimentary amplifier output stage.

Fig:1 block diagram of a typical opamp.

Op-amps can be used two ways: 1) in the so-called open-loop mode, which is useful for
comparators and triggers, and 2) with feedback, which is how nearly all amplifiers, filters and
oscillators using op-amps are designed. One of the key characteristics of op-amp is its open loop
gain. The open-loop gain is the gain of the amplifier without the Feedback loop being closed,
hence the name open-loop. For a precision op amp this gain can be very high, on the order of
160 dB or more.
1.2 Need for a high open loop gain.

For an ideal op-amp open loop gain is infinity, practically this gain is some large value of
few hundreds of tens. Besides not being infinity open loop voltage gain of the op-amp is not
constant. This voltage gain varies with temperature, power supply, passive components and
mass production technique. This gain needs to be controlled in such a way that the op-amp does
not go into saturation. This can be done by use of feedback; that is a portion of the output is fed
back to the input. This feedback process is more accurate when the open loop gain tends to
infinity. Closed loop gain of an op-amp can be written as,

AOL
ACL = (1)
1 AOL
Where, ACL is the closed loop gain, AOL is open loop gain and is the feedback factor. Now if
the open loop gain is infinity then equation one can be written as,

1
ACL (2)

So, if open loop gain becomes infinity then closed loop gain becomes insensitive to the forward
transfer block of the op-amp. being the feedback factor can now be completely designed by the
user or in a sense we can say that gain of the op-amp becomes less sensitive to the parameters
like temperature, power supply, passive components and mass production technique etc.

Therefore, design for an op-amp with a very high open loop gain is a necessary for the gain
stability.
 Chapter 2
Design of the circuit.

2.1 Transistor specification

To design the high gain bipolar junction transistor op-amp we use cascading structure, where
first and the intermediate stages are cascaded to get very high gain. We use PNP transistor of
model 2N3906 and NPN transistor of model 2N2222A, which are general purpose low power
transistors. Following are few parameters of the above two transistor.

For 2N2222A,
Symbol Parameter Value Unit
VCBO Collector-Base Voltage (IE = 0) 75 V
VCEO Collector-Emitter Voltage (IB = 0) 40 V
VA Forward early voltage 140 V
IC Collector Current 0.6 A
Ideal forward 220

For 2N3906,
Symbol Parameter Value Unit
VCBO Collector-Base Voltage (IE = 0) 40 V
VCEO Collector-Emitter Voltage (IB = 0) 40 V
VA Forward early voltage 140 V
IC Collector Current 0.5 A
Ideal forward 180

Table 1: transistor parameters

2.2 Arrangement of the circuit.

Following is the circuit diagram of the designed op-amp and used for simulation.

Fig.2: circuit diagram of the op-amp.

2.2a. first stage

First stage is a differential stage, which gives most of the gain, input impedance and the
common mode rejection ratio (CMRR). We use the following active load differential stage in
fig:2 with current source. Active load will give us a good common mode swing and high gain.
Whereas current source will give a high CMRR.

2.2b. second stage

For the second stage we have choice for a NPN and PNP common emitter. However
because of biasing convenience we use a PNP common emitter stage as intermediate stage. As
shown in the figure2.
2.2c. Level shifter

For zero input, the output voltage of the circuit was 1.14V, so the level shifter stage was
designed such that it gives a zero voltage at the output.
i.e.

Fig.3. level shifter circuit.

Where, 0.7V is required for the VBE drop of the output stage amplifier.

2.3 AC and DC analysis of the circuit.

2.3a. DC analysis.

We are performing following analysis by neglecting the base current and assuming VBE
= 0.7V.We bias all the transistor at collector current IC=0.5mA, and we make sure that with this
value of bias current none of the transistor go to saturation or cutoff.

Reference current, I0=10-0.7-(-10)/19.3k =1mA

Bias current, Iq = 1mA

Collector current, Ic1 = Ic2 = Iq/2 =0.5mA

DC voltage at collector of Q4, Vq4 :

Vq4= Vcc -0.7 =9.3V (3)

Maximum of Vq4 can be 9.3V,without Q4 going into saturation.

DC voltage of collector of Q6,Vq6 (with Q6 not going to saturation)

Vin-0.7 = -VEE 0.7 (at the edge of saturation Vc = VB)

Vin = -VEE + 1.4

Vin = -10 + 1.4 = -8.6 (4)

Now if the input signal is common mode input then the common mode range will be

(5)
-8.6V VCM 9.3V
Where VCM is the common mode signal. Then we bias Q7 and Q9 at 1mA.

Limit on input signal Vin:

Voltage of collector of Q3, VQ3=Vcc - V

Where V is cut in voltage of Q1.

So if Vin increases above VQ3,

Q3 goes into saturation

Vin max = VQ3=Vcc - V (6)
Also Q6 goes into saturation. If VQ6 drops below -VEE + 1.4V(At edge of saturation VQ6 =
VC=VB where Vc =Vin- V and VB = -VEE + V ).

Vin min = -VEE + 2V (7)

-8.6V Vin 9.3V (8)

Which is same as the common mode range.

Maximum limit on output signal:

Maximum of VQ7 before Q7 goes into saturation,

VQ7 max =Vcc - 0.7 (9)

Also, VQ7 max =Voutmax + 0.7 (10)

Eqn. (9) and (10) gives

Voutmax = Vcc 1.4 V =8.6V VOUTMAX= 8.6V (11)

Minimum of output signal cannot fall below the base voltage of Q10, otherwise Q10 will go to
saturation.

Voutmin = -VEE + 0.7 (12)

Voutmin = -10 + 0.7 =-9.3V (13)

Equation (12) and (13) gives,

-9.3V Vout 8.6V
(14)

2.3b ac analysis

For ac analysis we draw the AC equivalent circuit of the differential stage as in fig.3.
where Rceff is the resistance offered by the subsequent stage.
 Fig.4. AC equivalent circuit of the differential stage.
Applying KCL at node 1:

-Vd/re + gmVd + Vd/re - gmVd = 0.

gm (Vd - Vx) + gm (-Vd - Vx) = 0.

-gm Vx - gm Vx = 0., -2gmVx=0.

Vx =0 (Base current is zero) (15)

KCL at 2:

2Vy /re + gmVy + Vy/r0 = -gmVd

Vy (2/re + gm + 1/r0) = -gmVd

Vy(2r0 + gmrer0 + re/rer0)=-gmVd

Vy(2r0 + gmre(g mr0 + 1)/rer0)=-gmVd

Vy(2r0 + reg mr0 /rer0)=-gmVd (gmr0 >>1)

Vy reg mr0 /rer0=-gmVd (regmr0 >>2r0)

Vy = -gmVd/gm , Vy =-Vd (16)

KCL at 3:

g mVy gmVd + Vout/r0 = 0.

Vout/r0 = 2gmVd (Vy = -Vd)

Vout = 2gmVdr0 (17)

Equation (17) is true when +Vd and Vd is applied.

When only Vd is applied,

Small signal gain A is = gmr0

Gain Calculation:

1st stage gain: (AV1)

1st stage gain is loaded by the 2nd stage (Rceff). Therefore 1st stage gain can be written as-

If Rc is the load resistance of the 1st stage

Then, RC =r0(Q2)|| r0(Q4) ||[r0(Q7) + r0(Q8) + (re(Q9) + r0(Q10)]

=r02 ||[2r0 + (re(Q9) + r0(Q10))] (r0(Q2) = r0(Q4))

Rc r02 (R >> r0)

Av1 = gm2r02

Where re = Emitter resistance, r 0 = Dynamic resistance of the transistor.

2nd stage gain: Av2

2nd stage gain is loaded by me output stage. i.e. loaded resistance of 2nd stage Rc2 is-

Rc2 = r0(Q7) || r0(Q8) || input impedance of output stage(Riop)

= r0 || Riop
Where , Riop = (re(Q9) || r0(Q10))

Rc2 r07 ((re + r0)>>r0)

Av2 = gm7r07

Output stage gain:

Since output stage is a voltage follower, so it has unity gain.

Total Gain:(AVT)

AVT = AV1 * AVT , AVT = gm2r02 gm7r07

2.3c Calculating the op-amp parameters theoretically:

Load resistance RC1 at the o/p of first stage is,

1st stage gain.(=220)

r02 = VA/I02 , VA is Early Voltage(140V)

r02=140/0.5mA=280*103 .

RC1= 280k||280k||220[280k + 280k + 220(25 + 280)]

=280k || 220[360k + 220(280.025k)]

=273.54k

Gain Av1 = gm1Rc1 and gm= Ic1/VT = 0.5mA/25mV =0.02s

=5470.86

Similarly for 2nd stage gain.

gm7 = I07/VT = 1mA/25mA = 0.04s

r07 = 140k
RC2= 280k||280k * 220(25+280k) , where Rc7 is load resistance at the o/p of second stage.

=280k/2 * 220 * 280.025k

=139.68k

Gain Av2 = gm7Rc7 and gm2= Ic1/VT = 1mA/25mV =0.04s

=5587.2

Total gain, AVT = AV1 * AV2 *1

=5470.86*5587.2*1

AVT =30.9 * 106 = 143.3dB

CMRR is given by,

=gm4r06

=(0.5/25)(140/1)*103

=2800

CMRR(in dB)=20log2800

=68.5dB

With zero input voltage output voltage is of about 1.41V.

We use the level shifting circuit in fig.3. Writing KVL equation-

1.41V = 0.7 + IcR1 + 0.7 , IcR1 = 0.01V

R1 = 10

Gain of the 2nd stage after connecting the level shifter:

Load resistance RC2 of 2nd stage after connecting the level shifter can be written as:

RC2=r0(Q7)||r0(Q8)||[re(Q9)+10+(re(Q11)+r0(Q12)]
 =140k*140k/2*140k * 220[35+220(140.025k)]

=139.99k

AV2=5599.6 (gm=0.04)

Total gain after connecting the level shifter stage:

=AV1 * AV2 *1

=5470.86 * 5599.6

=30.63 * 106 , AVT(dB)=149.72dB

Input Impedance ( differential input):

Rip = 2(+1)re1

=2*221*25mV/0.5mA

=22k

Output Impedance:

AC equivalent circuit of output stage can be drawn as below:

Fig.5.AC equivalent circuit for the output stage.

Where Rt is the resistance offered by the current source;

Setting Vi = 0 , Z0 = Rt || re

=re(Rt>>re)

=25

Theoretically obtained values can be tabulated as below:

Gain(dB) CMRR(dB) i/p o/p impedance Power

impedance consumed
149.9 68.5 22k 25 80 mW
Table2: calculated parameters

2.3c. simulation result

Simulation of above designed op-amp was performed on NIMULTISIM.12(student version)
and simulation result for a DIFFERENTIAL input voltage of 1V are as shown below.

Fig.6. differential o/p waveform

Measurement of slew rate:
We have measured the Slew rate by applying a step input of 1V peak, and following is the
output waveform of the same.

Fig.6. measurement of slew rate

From the above plot slope of the o/p waveform will give us the slew rate.

Frequency and phase response for the op-amp for a 500Hz 1v sinusoidal waveform is plotted
below.

Fig.6: frequency response of the op-amp.

Observation from frequency response can be tabulated as below.

Gain(dB) CMRR(dB) 3dB cut-off Slew Gain

frequency(kHz) rate(V/sec) Bandwidth
Product(MHz)
107.85 57.68 12 0.95 120
Table.3. observation from frequency response.

If we compare the theoretical and practical results it can be seen that there is deviation in
simulation result from the calculated result, this deviation is inevitable because of the mismatch
of the values of the practical NPN and PNP transistor, due to which the transistor bias current
are not exactly same. However, for theoretical calculation we assumed the transistor currents to
be same.
 Chapter 3
Optimization and further increase in gain.

Drop at collector of transistor Q3 is given as:

VC1 = Vcc -V

So to increase gain, supply voltage can be increased. But , if we assume both the supply voltage
and current fixed we can increase the gain by increasing the Early voltage.

i.e. Gain = gm2r01

gain = Ic1/rc1 * VA/Ic2

So, gain =kVA (k=Ic1/rc1*1/Ic2)

i.e. gain VA

However ,VA is Early voltage which is device parameter. So given A fixed Early voltage we can
increase the gain by only cascading another stage. But if we connect another stage to increase the
gain then our op-amp will become a four stage system with minimum four pole system. So, our
system will definitely become unstable at some frequency in closed loop operation.

So only way to increase the gain without introducing another stage and hence another pole is
to increase the Early voltage. Changing the Early voltage from 140V to 500V, gain changes from
107dB to 113dB, this is a small increase in gain. However gain can be increased by cascading
another stage with external compensation circuits.
 BIBLIOGRAPHY
[1].D. Roy Choudhury Linear integrated circuits.(fourth edition) .
[2].Bruce Carter and Thomas R. Brown Handbook of operational amplifier and its application.
[3].Ron mancini Op-amps for everyone, Texas instruments.
[4].Ramakant A Gayakwad, Op-amps and linear integrated circuits.