SiC Bipolar Integrated Circuits on Semi-Insulating Substrates

S. Singh and J. A. Cooper

School of Electrical and Computer Engineering and Birck Nanotechnology Center
Purdue University, 1205 West State Street, West Lafayette, IN 47907-2057
cooperj@purdue.edu, TEL: 765-494-3514, FAX: 765-496-6443

Because of its wide bandgap, silicon carbide is attractive for applications in harsh environments, especially
high temperature applications. The intrinsic carrier concentration in 4H-SiC is about 10-8 cm-3 at room temperature,
and only 2x1011 cm-3 at 600 C. Thermal generation currents are negligible in SiC, even at high temperatures, and
the intrinsic temperature of SiC is above 900 C. As a result, the upper temperature of SiC devices is limited by the
stability of the associated metallurgy or dielectrics, rather than by the semiconductor. One of the most severe
limitations is imposed by the SiO2 gate insulator in MOS devices, which limits their maximum operating
temperature to about 200 C. For applications above 200 C, bipolar devices are required. In this work we report
the performance of second-generation bipolar integrated circuits in 4H-SiC. These circuits are suitable for small-
scale integration applications in smart power, aerospace, automotive, and well logging applications.
Historically, bipolar circuits were the first integrated circuits developed in silicon, and were used for both
digital and linear applications. Digital integrated circuit families include transistor-transistor logic (TTL), emitter-
coupled logic (ECL), and integrated injection logic (I2L). The first bipolar integrated circuits in 4H-SiC were simple
TTL gates operating on a 15 V supply voltage with propagation delays around 100 ns at room temperature [1]. In
this paper, we report an improved design that exhibits propagation delays of only 10 ns at room temperature.
To achieve the improved performance, we optimized parameter values for various resistors and transistors in
the basic TTL gate, based on careful circuit simulations. The initial design [1] focused on achieving adequate static
noise margins over a range of supply voltages, while the new design pays special attention to reducing switching
delay. The changes include reducing the size of most transistors in the basic gate and fabricating the structure on a
semi-insulating substrate to reduce parasitics.
All active layers in our npn BJTs are formed by epitaxy rather than implantation, to avoid the low current
gains of implanted structures. Beginning with a semi-insulating substrate, we form a 1 m n+ sub-collector doped
1x1019 cm-3, followed by a 0.54 m n- collector doped 8x1015 cm-3, a 1.1 m p-type base layer doped 1x1017 cm-3,
and a 0.65 m n+ emitter doped 1.2x1019 cm-3. The emitter, base, and sub-collector are patterned by reactive ion
etching in SF6, and a p+ region for the base ohmic contact is formed by Al implantation and annealed at 1600 C
under a graphite cap. A first-layer dielectric is grown by thermal oxidation, and ohmic contact metals (Ni for n-
type, Ti/Al for p-type) are deposited and annealed at 950 C in vacuum. A first intermediate dielectric is deposited
at low temperature (LTO), Ti/Al top-metal 1 is sputtered and defined by liftoff, the second intermediate dielectric is
deposited by LTO, and Ti/Au top-metal 2 is sputtered and patterned, completing the device.
The fabricated circuits include basic logic gates with fan-outs of one and ten, 11-stage ring oscillators, D flip-
flops, and half-adders. All circuits are fully functional. With a fan-out of ten at room temperature, (VOH / VOL /
VOUT) increases from (8.2 / 0.95 / 7.25 V) to (12.8 / 1.73 / 11.1 V) as VCC goes from 15 to 20 V. At VCC = 20 V,
the output levels, logic swing, and noise margins for a fan-out of ten are given in the table below. We note that SiC
TTL circuits require higher VCC than silicon (~15 V compared to 5 V) because of the higher forward diode drop in
wide bandgap material [1].
The 11-stage ring oscillator exhibits high VOH VOL VOUT NMH NML
and low logic levels of 13.0 and 0.4 V (12.6 V 23 C 12.8 V 1.73 V 11.1 V 6.04 V 1.27 V
logic swing) at VCC = 20 V, with a stage delay of 150 C 12.0 V 1.72 V 10.3 V 5.80 V 1.18 V
9.8 ns at 23 C, increasing to 11.7 ns at 355 C. 355 C 11.8 V 1.72 V 10.1 V 5.40 V 0.58 V
This is an order-of magnitude lower stage delay
than our first circuits [1], and is comparable to those of standard silicon TTL logic families. These results
demonstrate the potential of bipolar integrated circuits in SiC for small-scale digital logic applications at elevated
temperatures.

This work is supported by the DARPA RIPE program under grant. no. FA8650-05-1-7203, administered by
Mr. George High of AFRL. The authors thank Dr. Kevin Matocha of GE Global Research for LTO depositions.

[1] J-Y. Lee, S. Singh and J. A. Cooper, IEEE Trans. on Electron Devices, 55, 1946 1953 (2008).

978-1-4244-3527-2/09/$25.00 2009 IEEE 273

 V CC VIN VCC VOUT

RB RCP
QI
RB RC R CP QP

QP QS
QI
RC
V IN QS DL
V OUT DL
DC
QO
RD
RD
DC
Q0
Totem -Pole O utput
Input stage D river stage
stage

GND
Figure 1. Circuit diagram of the basic logic inverter. Figure 2. Top view of the inverter of Fig.1.

Figure. 3 Cross section of the basic epitaxial npn BJT on a semi- Figure 4. Voltage transfer characteristics of a fan-out of
insulating substrate, showing the epilayer structure. Lateral one inverter at 23 C as a function of supply voltage. The
dimensions are in microns. Two-level interconnect metal is inset shows noise margins for a fan-out of ten inverter as a
employed to provide cross-overs. function of supply voltage at 23 and 355 C.

C
A
D
B
Q
S
Q
C

Figure 5. Logic waveforms of the half-adder (left) and D flip-flop Figure 6. Waveform of an 11-stage ring oscillator with
(right). For the half-adder, A and B are inputs, while Sum and VCC = 20 V. Dividing the period by 22 (the round-trip for
Carry are outputs. For the D flip-flop, Clock and Data are inputs, a logic one) yields a stage delay of 9.8 ns at 23 C and
while Q and NOT-Q are outputs. 11.7 ns at 355 C.

978-1-4244-3527-2/09/$25.00 2009 IEEE 274