Hin202 06 07 08 11 13

DATASHEET
HIN202, HIN206, HIN207, HIN208, HIN211, HIN213 FN3980

+5V Powered RS-232 Transmitters/Receivers with 0.1Microfarad External Rev 19.00
Capacitors August 6, 2015
The HIN202, HIN206, HIN207, HIN208, HIN211, HIN213 Features

family of RS-232 transmitters/receivers interface circuits
meet all ElA RS-232E and V.28 specifications, and are Pb-Free Plus Anneal Available (RoHS Compliant)
(See Ordering Info)
particularly suited for those applications where 12V is not
available. They require a single +5V power supply and Meets All RS-232E and V.28 Specifications
feature onboard charge pump voltage converters which
Requires Only 0.1F or Greater External Capacitors
generate +10V and -10V supplies from the 5V supply. The
family of devices offers a wide variety of RS-232 High Data Rate. . . . . . . . . . . . . . . . . . . . . . . . . . .120kbit/s
transmitter/receiver combinations to accommodate various Two Receivers Active in Shutdown Mode (HIN213)
applications (see Selection Table).
Requires Only Single +5V Power Supply
The HIN206, HIN211 and HIN213 feature a low power
Onboard Voltage Doubler/Inverter
shutdown mode to conserve energy in battery powered
applications. In addition, the HIN213 provides two active Low Power Consumption (Typ) . . . . . . . . . . . . . . . . . 5mA
receivers in shutdown mode allowing for easy wakeup
Low Power Shutdown Function (Typ) . . . . . . . . . . . . .1A
capability.
Three-State TTL/CMOS Receiver Outputs
The drivers feature true TTL/CMOS input compatibility, slew
rate-limited output, and 300 power-off source impedance. Multiple Drivers
The receivers can handle up to 30V input, and have a 3k - 10V Output Swing for +5V lnput
to 7k input impedance. The receivers also feature - 300 Power-Off Source Impedance
hysteresis to greatly improve noise rejection. - Output Current Limiting
- TTL/CMOS Compatible
Applications - 30V/s Maximum Slew Rate
Any System Requiring RS-232 Communications Port Multiple Receivers
- Computer - Portable, Mainframe, Laptop - 30V Input Voltage Range
- Peripheral - Printers and Terminals - 3k to 7k Input Impedance
- Instrumentation - 0.5V Hysteresis to Improve Noise Rejection
- Modems
Selection Table
NUMBER OF NUMBER OF
NUMBER OF NUMBER OF 0.1F LOW POWER RECEIVERS
PART POWER SUPPLY RS-232 RS-232 EXTERNAL SHUTDOWN/TTL ACTIVE IN
NUMBER VOLTAGE DRIVERS RECEIVERS CAPACITORS THREE-STATE SHUTDOWN
HIN202 +5V 2 2 4 Capacitors No/No 0
HIN206 +5V 4 3 4 Capacitors Yes/Yes 0

FN3980 Rev 19.00 Page 1 of 20

August 6, 2015
HIN202, HIN206, HIN207, HIN208, HIN211, HIN213
Ordering Information Ordering Information (Continued)

TEMP. PKG. TEMP. PKG.
PART NO. RANGE (C) PACKAGE DWG. # PART NO. RANGE (C) PACKAGE DWG. #
HIN202CBZ 0 to 70 16 Ld SOIC (W) M16.3 HIN208CBZ 0 to 70 24 Ld SOIC M24.3

(See Note) (Pb-free) (See Note) (Pb-free)
(No longer
HIN202CBZ-T (See 0 to 70 16 Ld SOIC (W) M16.3 available,
Note) Tape and Reel recommended
(Pb-free) replacement:
HIN208ECBZ-T)
HIN202CBNZ (See 0 to 70 16 Ld SOIC (N) M16.15
Note) (Pb-free)
HIN202CBNZ-T 0 to 70 16 Ld SOIC (N) M16.15 HIN208CBZ-T 0 to 70 24 Ld SOIC M24.3

(See Note) Tape and Reel
(No longer (Pb-free)
(Pb-free)
available,
HIN202CPZ 0 to 70 16 Ld PDIP E16.3 recommended
(See Note) replacement:
HIN208ECBZ-T)
HIN202IBZ -40 to 85 16 Ld SOIC (W) M16.3
(See Note) (Pb-free) HIN211CAZ 0 to 70 28 Ld SSOP M28.209
(See Note) (Pb-free)
HIN202IBNZ -40 to 85 16 Ld SOIC (N) M16.15
(See Note) (Pb-free) HIN211CAZ-T 0 to 70 28 Ld SSOP M28.209
HIN202IBNZ-T -40 to 85 16 Ld SOIC (N) M16.15
(Pb-free)
(Pb-free) HIN211CBZ 0 to 70 28 Ld SOIC M28.3
HIN207CAZ 0 to 70 24 Ld SSOP M24.209
(See Note) (Pb-free) HIN211CBZ-T 0 to 70 28 Ld SOIC M28.3
(No longer (See Note) Tape and Reel
available, (Pb-free)
recommended
HIN213CAZ 0 to 70 28 Ld SSOP M28.209
replacement:
HIN207ECAZ)
HIN207CAZ-T 0 to 70 24 Ld SSOP M24.209 HIN213CAZ-T 0 to 70 28 Ld SSOP M28.209

(Pb-free)
(No longer (Pb-free)
available, NOTE: Intersil Pb-free plus anneal products employ special Pb-free
recommended material sets; molding compounds/die attach materials and 100%
replacement: matte tin plate termination finish, which are RoHS compliant and
HIN207ECAZ-T) compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
FN3980 Rev 19.00 Page 2 of 20

August 6, 2015
Pin Descriptions
PIN FUNCTION
VCC Power Supply Input 5V 10%, (5V 5% HIN207).
V+ Internally generated positive supply (+10V nominal).
V- Internally generated negative supply (-10V nominal).
GND Ground Lead. Connect to 0V.
C1+ External capacitor (+ terminal) is connected to this lead.
C1- External capacitor (- terminal) is connected to this lead.
C2+ External capacitor (+ terminal) is connected to this lead.
C2- External capacitor (- terminal) is connected to this lead.

TIN Transmitter Inputs. These leads accept TTL/CMOS levels. An internal 400kpull-up resistor to VCC is connected to each lead.
TOUT Transmitter Outputs. These are RS-232 levels (nominally 10V).
RIN Receiver Inputs. These inputs accept RS-232 input levels. An internal 5kpull-down resistor to GND is connected to each input.
ROUT Receiver Outputs. These are TTL/CMOS levels.
EN, EN Receiver enable Input. With EN = 5V (HIN213 EN = 0V), the receiver outputs are placed in a high impedance state.
SD, SD Shutdown Input. With SD = 5V (HIN213 SD = 0V), the charge pump is disabled, the receiver outputs are in a high impedance state
(except R4 and R5 of HIN213) and the transmitters are shut off.
NC No Connect. No connections are made to these leads.
FN3980 Rev 19.00 Page 3 of 20

August 6, 2015
Pinouts
HIN202 (PDIP, SOIC) HIN206 (SOIC)
TOP VIEW TOP VIEW
T3OUT 1 24 T4OUT
C1+ 1 16 VCC
T1OUT 2 23 R2IN
V+ 2 15 GND
T2OUT 3 22 R2OUT
C1- 3 14 T1OUT
R1IN 4 21 SD
C2+ 4 13 R1IN
R1OUT 5 20 EN
C2- 5 12 R1OUT 19 T4IN
T2IN 6
V- 6 11 T1IN T1IN 7 18 T3IN
T2OUT 7 10 T2IN GND 8 17 R3OUT
R2IN 8 9 R2OUT VCC 9 16 R3IN

C1+ 10 15 V-
V+ 11 14 C2-
C1- 12 13 C2+
+5V +5V
9
10 0.1F
C1+ VCC +
16 + 11
0.1F +5V TO 10V V+
12
C1- VOLTAGE DOUBLER
VCC 13
1 C2+
0.1F + +10V TO -10V
+
C1+
2 + 0.1F
14 V- 15
0.1F +5V TO 10V VOLTAGE INVERTER
C2-
3 VOLTAGE INVERTER V+ +
0.1F
C1-
+5V T1
4 7 400k 2
C2+ T1IN T1OUT
+ +10V TO -10V
0.1F
5 V- 6
VOLTAGE INVERTER +5V T2
C2- 0.1F
+ 6 400k 3
T2IN T2OUT
+5V T1
11 400k 14 +5V T3
T1IN T1OUT 18 400k 1
T3IN T3OUT
+5V T2 +5V T4
10 400k 7 19 400k 24
T2IN T2OUT T4IN T4OUT
5 4
12 13 R1OUT R1IN
R1OUT R1IN 5k
R1
R1 5k
22 23
R2OUT R2IN
9 8 5k
R2OUT R2IN R2
R2 5k
17 16
R3OUT R3IN
GND
R3 5k 21
20
15 EN SD
GND
FN3980 Rev 19.00 Page 4 of 20

August 6, 2015
Pinouts (Continued)
HIN207 (SOIC, SSOP) HIN208 (SOIC)
TOP VIEW TOP VIEW
T3OUT 1 24 T4OUT T2OUT 1 24 T3OUT

T1OUT 2 23 R2IN T1OUT 2 23 R3IN
T2OUT 3 22 R2OUT R2IN 3 22 R3OUT
R1IN 4 21 T5IN R2OUT 21 T4IN
4
R1OUT 5 20 T5OUT T1IN 20 T4OUT
5
T2IN 6 19 T4IN R1OUT 6 19 T3IN
T1IN 7 18 T3IN R1IN 7 18 T2IN
GND 8 17 R3OUT GND 8 17 R4OUT
VCC 9 16 R3IN VCC 9 16 R4IN
C1+ 10 15 V- C1+ 10 15 V-
V+ 11 14 C2- V+ 11 14 C2-
C1- 12 13 C2+ C1- 12 13 C2+
+5V +5V
9 9
10 0.1F 10 0.1F
C1+ VCC + C1+ VCC +
+ 11 + 11
0.1F V+ 0.1F +5V TO 10V V+
12 +5V TO 10V 12
C1- VOLTAGE DOUBLER C1- VOLTAGE DOUBLER
13 13
C2+ C2+
+ +10V TO -10V + +10V TO -10V
0.1F
14 V- 15 0.1F
14 V- 15
VOLTAGE INVERTER VOLTAGE INVERTER
C2- 0.1F C2- 0.1F
+ +
+5V T1 +5V T1
7 400k 2 5 400k 2
+5V T2 +5V T2
6 400k 3 18 400k 1
+5V T3 +5V T3
18 400k 1 19 400k 24
+5V T4 +5V T4
19 400k 24 21 400k 20
+5V T5 6 7
400k R1OUT R1IN
21 20
T5IN T5OUT
R1 5k
5 4
R1OUT R1IN 4 3
5k R2OUT R2IN
R1
R2 5k
22 23
R2OUT R2IN 22 23
5k R3OUT R3IN
R2
R3 5k
17 16
R3OUT R3IN 17 16
R4OUT R4IN
R3 5k
R4 5k
GND
GND
8
8
FN3980 Rev 19.00 Page 5 of 20

August 6, 2015
Pinouts (Continued)
HIN211 (SOIC, SSOP) HIN213 (SSOP)
TOP VIEW TOP VIEW
T3OUT 1 28 T4OUT T3OUT 1 28 T4OUT
T1OUT 2 27 R3IN T1OUT 2 27 R3IN
T2OUT 3 26 R3OUT T2OUT 3 26 R3OUT
R2IN 4 25 SD R2IN 4 25 SD
R2OUT 5 24 EN R2OUT 5 24 EN
T2IN 6 23 R4IN T2IN 6 23 R4IN
T1IN 7 22 R4OUT T1IN 7 22 R4OUT
R1OUT 8 21 T4IN R1OUT 8 21 T4IN
R1IN 9 20 T3IN R1IN 9 20 T3IN
GND 10 19 R5OUT GND 10 19 R5OUT
VCC 11 18 R5IN VCC 11 18 R5IN
C1+ 12 17 V- C1+ 12 17 V-
V+ 13 16 C2- V+ 13 16 C2-
C1- 14 15 C2+ C1- 14 15 C2+
NOTE: R4 and R5 active in shutdown.
+5V +5V
11 11
12 0.1F 12 0.1F
C1+ VCC + C1+ VCC +
+ 13 + 13
0.1F +5V TO 10V V+ 0.1F +5V TO 10V V+
14 14
C1- VOLTAGE DOUBLER C1- VOLTAGE DOUBLER
15 15
C2+ C2+
+ +10V TO -10V + +10V TO -10V
0.1F
16 V- 17 0.1F
16 V- 17
VOLTAGE INVERTER VOLTAGE INVERTER
C2- 0.1F C2- 0.1F
+ +
+5V T1 +5V T1
7 400k 2 7 400k 2
+5V T2 +5V T2
6 400k 3 6 400k 3
+5V T3 +5V T3
20 400k 1 20 400k 1
+5V T4 +5V T4
21 400k 28 21 400k 28
8 9 8 9
R1OUT R1IN R1OUT R1IN
R1 5k R1 5k
5 4 5 4
R2 5k R2 5k
26 27 26 27
R3 5k R3 5k
22 23 22 23
R4 5k R4 5k
19 18 19 18
R5 5k R5 5k
24 25 24 25
EN SD EN SD
GND GND
10 10
FN3980 Rev 19.00 Page 6 of 20

August 6, 2015
Absolute Maximum Ratings Thermal Information

VCC to Ground. . . . . . . . . . . . . . . . . . . . . . (GND -0.3V) <VCC < 6V Thermal Resistance (Typical, Note 1) JA (C/W)
V+ to Ground . . . . . . . . . . . . . . . . . . . . . . . . (VCC -0.3V) <V+ < 12V 16 Ld PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . 90
V- to Ground . . . . . . . . . . . . . . . . . . . . . . .-12V < V- < (GND +0.3V) 16 Ld SOIC (N) Package . . . . . . . . . . . . . . . . . . . . . 110
Input Voltages 16 Ld SOIC (W) Package. . . . . . . . . . . . . . . . . . . . . 100
TIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V < VIN < (V+ +0.3V) 24 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . 75
RIN 30V 24 Ld SSOP Package . . . . . . . . . . . . . . . . . . . . . . . 135
Output Voltages 28 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . 70
TOUT . . . . . . . . . . . . . . . . . . . .(V- -0.3V) < VTXOUT < (V+ +0.3V) 28 Ld SSOP Package . . . . . . . . . . . . . . . . . . . . . . . 100
ROUT . . . . . . . . . . . . . . . . . (GND -0.3V) < VRXOUT < (V+ +0.3V) Maximum Junction Temperature (Plastic Package) . . . . . . . . 150C
Short Circuit Duration Maximum Storage Temperature Range . . . . . . . . . . -65C to 150C
TOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300C
ROUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous (SOIC and SSOP - Lead Tips Only)
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Operating Conditions
Temperature Range
HIN2XXCX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C
HIN2XXIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40C to 85C
CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications Test Conditions: VCC = +5V 10%, (VCC = +5V 5%, HIN207); C1-C4 = 0.1F;
TA = Operating Temperature Range
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
SUPPLY CURRENTS
Power Supply Current, ICC No Load, HIN202 - 8 15 mA
TA = 25C
HIN206, HIN207, HIN208, - 11 20 mA
HIN211, HIN213
Shutdown Supply Current, ICC(SD) TA = 25C HIN206, HIN211 - 1 10 A
HIN213 - 15 50 A
LOGIC AND TRANSMITTER INPUTS, RECEIVER OUTPUTS
Input Logic Low, VlL TIN , EN, SD, EN, SD - - 0.8 V
Input Logic High, VlH TIN 2.0 - - V
EN, SD, EN, SD 2.4 - - V
Transmitter Input Pullup Current, IP TIN = 0V - 15 200 A
TTL/CMOS Receiver Output Voltage Low, VOL IOUT = 1.6mA - 0.1 0.4 V
(HIN202, IOUT = 3.2mA)
TTL/CMOS Receiver Output Voltage High, VOH IOUT = -1mA 3.5 4.6 - V
TTL/CMOS Receiver Output Leakage EN = VCC , EN = 0, 0V < ROUT < VCC - 0.05 10 A
RECEIVER INPUTS
RS-232 Input Voltage Range, VIN -30 - +30 V
Receiver Input Impedance, RIN TA = 25C, VIN = 3V 3.0 5.0 7.0 k
Receiver Input Low Threshold, VIN (H-L) VCC = 5V, Active Mode 0.8 1.2 - V
TA = 25C
Shutdown Mode 0.6 1.5 - V
HIN213 R4 and R5
Receiver Input High Threshold, VIN (L-H) VCC = 5V, Active Mode - 1.7 2.4 V
TA = 25C
Shutdown Mode - 1.5 2.4 V
HIN213 R4 and R5
Receiver Input Hysteresis, VHYST VCC = 5V 0.2 0.5 1.0 V
No Hysteresis in Shutdown Mode
FN3980 Rev 19.00 Page 7 of 20

August 6, 2015
Electrical Specifications Test Conditions: VCC = +5V 10%, (VCC = +5V 5%, HIN207); C1-C4 = 0.1F;
TA = Operating Temperature Range (Continued)
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
TIMING CHARACTERISTICS
Baud Rate 1 Transmitter RL = 3k 120 - - kbps
Switching
Output Enable Time, tEN HIN206, HIN211, HIN213 - 400 - ns
Output Disable Time, tDIS HIN206, HIN211, HIN213 - 200 - ns
Transmitter, Receiver Propagation Delay, tPD HIN213 SD = 0V, R4, R5 - 0.5 40 s
HIN213 SD = VCC , R1 - R5 - 0.5 10 s
HIN202, HIN206, HIN207, HIN208, HIN211 - 0.5 10 s
Transition Region Slew Rate, SRT RL = 3k, CL = 2500pF Measured from 3 - 30 V/s
+3V to -3V or -3V to +3V, 1 Transmitter
Switching (Note 2)
TRANSMITTER OUTPUTS
Output Voltage Swing, TOUT Transmitter Outputs, 3k to Ground 5 9 10 V
Output Resistance, TOUT VCC = V+ = V- = 0V, VOUT = 2V 300 - -
RS-232 Output Short Circuit Current, ISC TOUT Shorted to GND - 10 - mA
NOTE:
2. Guaranteed by design.
VOLTAGE DOUBLER VOLTAGE INVERTER
S1 C1+ S2 V+ = 2VCC S5 C2+ S6

VCC GND
+ + + +
C1 C3 C2 C4
- - - -
GND VCC GND V- = - (V+)
S3 C1- S4 S7 C2- S8
RC
OSCILLATOR
FIGURE 1. CHARGE PUMP
FN3980 Rev 19.00 Page 8 of 20

August 6, 2015
Detailed Description Receivers

The HIN202, HIN206, HIN207, HIN208, HIN211, HIN213 The receiver inputs accept up to 30V while presenting the
family of RS-232 transmitters/receivers are powered by a required 3k to 7k input impedance even if the power is off
single +5V power supply feature low power consumption, and (VCC = 0V). The receivers have a typical input threshold of
meet all ElA RS232C and V.28 specifications. The circuit is 1.3V which is within the 3V limits, known as the transition
divided into three sections: The charge pump, transmitter, and region, of the RS-232 specifications. The receiver output is 0V
receiver. to VCC . The output will be low whenever the input is greater
than 2.4V and high whenever the input is floating or driven
Charge Pump between +0.8V and -30V. The receivers feature 0.5V
An equivalent circuit of the charge pump is illustrated in Figure hysteresis (except during shutdown) to improve noise
1. The charge pump contains two sections: the voltage doubler rejection. The receiver Enable line (EN on HIN206 and
and the voltage inverter. Each section is driven by a two HIN211, EN on HIN213) when unasserted, disables the
phase, internally generated clock to generate +10V and -10V. receiver outputs, placing them in the high impedance mode.
The nominal clock frequency is 125kHz. During phase one of The receiver outputs are also placed in the high impedance
the clock, capacitor C1 is charged to VCC . During phase two, state when in shutdown mode (except HIN213 R4 and R5).
the voltage on C1 is added to VCC , producing a signal across
V+
C3 equal to twice VCC . During phase two, C2 is also charged
to 2VCC , and then during phase one, it is inverted with respect VCC
400k
to ground to produce a signal across C4 equal to -2VCC . The 300
TXIN TOUT
charge pump accepts input voltages up to 5.5V. The output
GND < TXIN < VCC V- < VTOUT < V+
impedance of the voltage doubler section (V+) is
approximately 200, and the output impedance of the voltage V-
inverter section (V-) is approximately 450. A typical FIGURE 2. TRANSMITTER
application uses 0.1F capacitors for C1-C4, however, the
value is not critical. Increasing the values of C1 and C2 will
lower the output impedance of the voltage doubler and
VCC
inverter, increasing the values of the reservoir capacitors, C3
and C4, lowers the ripple on the V+ and V- supplies. RXIN ROUT
During shutdown mode (HIN206 and HIN211, SD = VCC , -30V < RXIN < +30V 5k GND < VROUT < VCC
HIN213, SD = 0V) the charge pump is turned off, V+ is pulled GND
down to VCC , V- is pulled up to GND, and the supply current is FIGURE 3. RECEIVER
reduced to less than 10A. The transmitter outputs are
disabled and the receiver outputs (except for HIN213, R4 and
R5) are placed in the high impedance state.
TIN
Transmitters OR
The transmitters are TTL/CMOS compatible inverters which RIN
translate the inputs to RS-232 outputs. The input logic TOUT VOL
threshold is about 26% of VCC , or 1.3V for VCC = 5V. A logic 1 OR
VOL
ROUT
at the input results in a voltage of between -5V and V- at the tPHL tPLH
output, and a logic 0 results in a voltage between +5V and (V+
- 0.6V). Each transmitter input has an internal 400k pullup tPHL + tPLH
resistor so any unused input can be left unconnected and its AVERAGE PROPAGATION DELAY =
2
output remains in its low state. The output voltage swing meets FIGURE 4. PROPAGATION DELAY DEFINITION
the RS-232C specifications of 5V minimum with the worst
case conditions of: all transmitters driving 3k minimum load
HIN213 Operation in Shutdown
impedance,
VCC = 4.5V, and maximum allowable operating temperature. The HIN213 features two receivers, R4 and R5, which remain
The transmitters have an internally limited output slew rate active in shutdown mode. During normal operation the
which is less than 30V/s. The outputs are short circuit receivers propagation delay is typically 0.5s. This propagation
protected and can be shorted to ground indefinitely. The delay may increase slightly during shutdown. When entering
powered down output impedance is a minimum of 300 with shut down mode, receivers R4 and R5 are not valid for 80s
2V applied to the outputs and VCC = 0V. after SD = VIL. When exiting shutdown mode, all receiver
outputs will be invalid until the charge pump circuitry reaches
normal operating voltage. This is typically less than 2ms when
using 0.1F capacitors.
FN3980 Rev 19.00 Page 9 of 20

August 6, 2015
Typical Performance Curves
12 12
0.1F
V- SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (|V|)

10 10
8 8 V+ (VCC = 5V)
6 6
V+ (VCC = 4V)
V- (VCC = 4V)
4 4
TA = 25C
2 2 V- (VCC = 5V)
TRANSMITTER OUTPUTS
OPEN CIRCUIT
0 0
3.0 3.5 4.0 4.5 5.0 5.5 6.0 0 5 10 15 20 25 30 35
VCC |ILOAD| (mA)
FIGURE 5. V- SUPPLY VOLTAGE vs VCC FIGURE 6. V+, V- OUTPUT VOLTAGE vs LOAD
Test Circuits (HIN202)

+4.5V TO
+5.5V INPUT
1 C1+ VCC 16
0.1F -
C3 + 2 V+ GND 15
1 C1+ VCC 16 3 C1- T1OUT 14
0.1F + 3k
2 V+ GND 15 4 C2+ R1IN 13
C1 -
3 C1- T1OUT 14 T1 OUTPUT 5 C2- R1OUT 12
4 C2+ R1IN 13 RS-232 30V INPUT
0.1F + 6 V- T1IN 11
C2 - 5 C2- R1OUT 12 TTL/CMOS OUTPUT
+ - 7 T2OUT T2IN 10
6 V- T1IN 11 TTL/CMOS INPUT 8 R2IN R2OUT 9
0.1F C4
3k 7 T2OUT T2IN 10 TTL/CMOS INPUT
8 R2IN R2OUT 9 TTL/CMOS OUTPUT

ROUT = VIN /I T2OUT
T2
OUTPUT T1OUT
RS-232 VIN = 2V A
30V INPUT
FIGURE 7. GENERAL TEST CIRCUIT FIGURE 8. POWER-OFF SOURCE RESISTANCE

CONFIGURATION
Application Information
The HIN2XX may be used for all RS-232 data terminal and In applications requiring four RS-232 inputs and outputs
communication links. It is particularly useful in applications (Figure 10), note that each circuit requires two charge pump
where 12V power supplies are not available for conventional capacitors (C1 and C2) but can share common reservoir
RS-232 interface circuits. The applications presented capacitors (C3 and C4). The benefit of sharing common
represent typical interface configurations. reservoir capacitors is the elimination of two capacitors and the
reduction of the charge pump source impedance which
A simple duplex RS-232 port with CTS/RTS handshaking is
effectively increases the output swing of the transmitters.
illustrated in Figure 9. Fixed output signals such as DTR (data
terminal ready) and DSRS (data signaling rate select) is
generated by driving them through a 5kW resistor connected to
V+.
FN3980 Rev 19.00 Page 10 of 20

August 6, 2015
+5V
-
+
16 CTR (20) DATA
1
C1 + TERMINAL READY
0.1F - 3 DSRS (24) DATA
HIN202 SIGNALING RATE
4 6 SELECT
C2 + -
0.1F - 5 + RS-232
INPUTS AND OUTPUTS
11 T1 14
TD TD (2) TRANSMIT DATA
T2
10 7
INPUTS RTS RTS (4) REQUEST TO SEND
OUTPUTS 12 13
TTL/CMOS RD RD (3) RECEIVE DATA
R2 R1
9 8
CTS CTS (5) CLEAR TO SEND
15 SIGNAL GROUND (7)
FIGURE 9. SIMPLE DUPLEX RS-232 PORT WITH CTS/RTS HANDSHAKING
1 4
C1 + + C2
HIN202
0.1F - 3 5 - 0.1F
11 T1 14
TD TD (2) TRANSMIT DATA
T2
10 7
INPUTS RTS RTS (4) REQUEST TO SEND
OUTPUTS 12 13
TTL/CMOS RD RD (3) RECEIVE DATA
R2 R1
9 8
CTS CTS (5) CLEAR TO SEND
15
16 VCC
6 2
C4 C3 +5V
- -
+
V- V+
0.2F 0.2F RS-232
6 2 INPUTS AND OUTPUTS
16 VCC
HIN202
1 4
C1 + + C2
0.1F - 3 5 - 0.1F
11 T1 14
DTR DTR (20) DATA TERMINAL READY
T2
INPUTS 10 7
DSRS DSRS (24) DATA SIGNALING RATE SELECT
OUTPUTS 12 13
TTL/CMOS DCD DCD (8) DATA CARRIER DETECT
R2 R1
9 8
R1 R1 (22) RING INDICATOR
15 SIGNAL GROUND (7)
FIGURE 10. COMBINING TWO HIN202s FOR 4 PAIRS OF RS-232 INPUTS AND OUTPUTS
FN3980 Rev 19.00 Page 11 of 20

August 6, 2015
Die Characteristics
DIE DIMENSIONS: PASSIVATION:
160 mils x 140 mils Type: Nitride over Silox
Nitride Thickness: 8k
METALLIZATION:
Silox Thickness: 7k
Type: Al
Thickness: 10k 1k TRANSISTOR COUNT:
SUBSTRATE POTENTIAL 238
V+
PROCESS:
CMOS Metal Gate
Metallization Mask Layout

HIN211
SHD EN R4IN R4OUT T4IN T3IN R5OUT R5IN
R3OUT
V-
C2-
R3IN
T4OUT
C2+
T3OUT
C1-
T1OUT
T2OUT V+
C1+
R2IN
VCC
R2OUT T2IN T1IN R1OUT R1IN GND
FN3980 Rev 19.00 Page 12 of 20

August 6, 2015
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make
sure that you have the latest revision.
DATE REVISION CHANGE

August 6, 2015 FN3980.19 Updated Ordering Information table on page 2.
Added Revision History and About Intersil sections.
Updated package outline drawings to the latest revision. Changes are listed as follows:
M24.3
-Revision 0 to Revision 1, Removed symbol which is overlapping the alpha symbol in the diagram.
-Revision 1 to Revision 2, Updated to new POD standard by removing table listing dimensions and
putting dimensions on drawing. Added Land Pattern.
M28.3
-Revision 0 to Revision 1, Added land pattern
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support
FN3980 Rev 19.00 Page 13 of 20

August 6, 2015
Dual-In-Line Plastic Packages (PDIP)

E16.3 (JEDEC MS-001-BB ISSUE D)
N
16 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INDEX INCHES MILLIMETERS
AREA 1 2 3 N/2
SYMBOL MIN MAX MIN MAX NOTES
-B-
A - 0.210 - 5.33 4
-A-
D E A1 0.015 - 0.39 - 4
BASE A2 0.115 0.195 2.93 4.95 -
PLANE A2
-C- A
B 0.014 0.022 0.356 0.558 -
SEATING
PLANE L C
L B1 0.045 0.070 1.15 1.77 8, 10
D1 A1 eA C 0.008 0.014 0.204 0.355 -
D1
B1 e D 0.735 0.775 18.66 19.68 5
eC C
B
eB D1 0.005 - 0.13 - 5
0.010 (0.25) M C A B S
E 0.300 0.325 7.62 8.25 6
NOTES:
E1 0.240 0.280 6.10 7.11 5
1. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control. e 0.100 BSC 2.54 BSC -
2. Dimensioning and tolerancing per ANSI Y14.5M-1982. eA 0.300 BSC 7.62 BSC 6
3. Symbols are defined in the MO Series Symbol List in Section 2.2 of eB - 0.430 - 10.92 7
Publication No. 95.
L 0.115 0.150 2.93 3.81 4
4. Dimensions A, A1 and L are measured with the package seated in JE-
DEC seating plane gauge GS-3. N 16 16 9
5. D, D1, and E1 dimensions do not include mold flash or protrusions. Rev. 0 12/93
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and eA are measured with the leads constrained to be perpendic-
ular to datum -C- .
7. eB and eC are measured at the lead tips with the leads unconstrained.
eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
FN3980 Rev 19.00 Page 14 of 20

August 6, 2015
Small Outline Plastic Packages (SOIC)
N M16.15 (JEDEC MS-012-AC ISSUE C)

INDEX 16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
AREA H 0.25(0.010) M B M
E INCHES MILLIMETERS
-B-
A 0.0532 0.0688 1.35 1.75 -
1 2 3 A1 0.0040 0.0098 0.10 0.25 -
L
B 0.013 0.020 0.33 0.51 9
SEATING PLANE
C 0.0075 0.0098 0.19 0.25 -
-A-
D A h x 45 D 0.3859 0.3937 9.80 10.00 3
E 0.1497 0.1574 3.80 4.00 4
-C- e 0.050 BSC 1.27 BSC -

e H 0.2284 0.2440 5.80 6.20 -
A1
C
h 0.0099 0.0196 0.25 0.50 5
B 0.10(0.004)
L 0.016 0.050 0.40 1.27 6
0.25(0.010) M C A M B S
N 16 16 7
NOTES: 0 8 0 8 -
1. Symbols are defined in the MO Series Symbol List in Section 2.2 of Rev. 1 6/05
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension D does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension E does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. L is the length of terminal for soldering to a substrate.
7. N is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width B, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm
(0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
FN3980 Rev 19.00 Page 15 of 20

August 6, 2015
N M16.3 (JEDEC MS-013-AA ISSUE C)

16 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA H 0.25(0.010) M B M
INCHES MILLIMETERS
E
-B-
A 0.0926 0.1043 2.35 2.65 -
1 2 3 A1 0.0040 0.0118 0.10 0.30 -
L
B 0.013 0.0200 0.33 0.51 9
SEATING PLANE C 0.0091 0.0125 0.23 0.32 -
-A- D 0.3977 0.4133 10.10 10.50 3
D A h x 45
E 0.2914 0.2992 7.40 7.60 4
-C- e 0.050 BSC 1.27 BSC -

e H 0.394 0.419 10.00 10.65 -
A1
C h 0.010 0.029 0.25 0.75 5
B 0.10(0.004)
L 0.016 0.050 0.40 1.27 6
0.25(0.010) M C A M B S
N 16 16 7
NOTES: 0 8 0 8 -
1. Symbols are defined in the MO Series Symbol List in Section 2.2 of Rev. 1 6/05
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension E does not include interlead flash or protrusions. Interlead
the seating plane, shall not exceed a maximum value of 0.61mm (0.024
inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
FN3980 Rev 19.00 Page 16 of 20

August 6, 2015
Package Outline Drawing

M24.3
24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE (SOIC)
Rev 2, 3/11
24
INDEX
AREA
7.60 (0.299)
7.40 (0.291) 10.65 (0.419)
10.00 (0.394)
DETAIL "A"
1 2 3
TOP VIEW
1.27 (0.050)
SEATING PLANE 0.40 (0.016)
15.60 (0.614) 2.65 (0.104)

15.20 (0.598) 2.35 (0.093)
0.75 (0.029)
x 45
0.25 (0.010)
1.27 (0.050) 0.30 (0.012) 8

0.10 (0.004) 0
0.51 (0.020)
0.33 (0.013) 0.32 (0.012)
0.23 (0.009)
SIDE VIEW A SIDE VIEW B
1.981 (0.078)
NOTES:
2. Package length does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
3. Package width does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm
(0.010 inch) per side.
4. The chamfer on the body is optional. If it is not present, a visual
9.373 (0.369) index feature must be located within the crosshatched area.
6. The lead width as measured 0.36mm (0.014 inch) or greater above
(0.024 inch).
7. Controlling dimension: MILLIMETER. Converted inch dimensions in
( ) are not necessarily exact.
8. This outline conforms to JEDEC publication MS-013-AD ISSUE C.
1.27 (0.050) 0.533 (0.021)
TYPICAL RECOMMENDED LAND PATTERN
FN3980 Rev 19.00 Page 17 of 20

August 6, 2015
Shrink Small Outline Plastic Packages (SSOP)
N M24.209 (JEDEC MO-150-AG ISSUE B)

24 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA H 0.25(0.010) M B M
INCHES MILLIMETERS
E
GAUGE SYMBOL MIN MAX MIN MAX NOTES
-B- PLANE
A - 0.078 - 2.00 -
1 2 3 A1 0.002 - 0.05 - -
L A2 0.065 0.072 1.65 1.85 -

SEATING PLANE 0.25
B 0.009 0.014 0.22 0.38 9
0.010
-A- C 0.004 0.009 0.09 0.25 -
D A
D 0.312 0.334 7.90 8.50 3
-C- E 0.197 0.220 5.00 5.60 4

e A2 e 0.026 BSC 0.65 BSC -
A1
C H 0.292 0.322 7.40 8.20 -
B 0.10(0.004)
L 0.022 0.037 0.55 0.95 6
0.25(0.010) M C A M B S
N 24 24 7
0o 8o 0o 8o -
NOTES:
Rev. 1 3/95
1. Symbols are defined in the MO Series Symbol List in Section 2.2 of
Mold flash, protrusion and gate burrs shall not exceed 0.20mm
(0.0078 inch) per side.
4. Dimension E does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.20mm (0.0078 inch) per
side.
9. Dimension B does not include dambar protrusion. Allowable dambar
protrusion shall be 0.13mm (0.005 inch) total in excess of B dimen-
sion at maximum material condition.
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
FN3980 Rev 19.00 Page 18 of 20

August 6, 2015
N
M28.3 (JEDEC MS-013-AE ISSUE C)
28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
H 0.25(0.010) M B M
AREA INCHES MILLIMETERS
E
-B-
A 0.0926 0.1043 2.35 2.65 -
1 2 3
A1 0.0040 0.0118 0.10 0.30 -
L
B 0.013 0.0200 0.33 0.51 9
SEATING PLANE C 0.0091 0.0125 0.23 0.32 -
-A- D 0.6969 0.7125 17.70 18.10 3
D A h x 45o
E 0.2914 0.2992 7.40 7.60 4
-C- e 0.05 BSC 1.27 BSC -
a
H 0.394 0.419 10.00 10.65 -
e A1
C h 0.01 0.029 0.25 0.75 5
B 0.10(0.004)
L 0.016 0.050 0.40 1.27 6
0.25(0.010) M C A M B S
N 28 28 7
0o 8o 0o 8o -
Rev. 1, 1/13
NOTES:
1. Symbols are defined in the MO Series Symbol List in Section 2.2 of
TYPICAL RECOMMENDED LAND PATTERN Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
(1.50mm) 4. Dimension E does not include interlead flash or protrusions. Interlead
(9.38mm)
(0.024 inch)
(1.27mm TYP) (0.51mm TYP) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are
FN3980 Rev 19.00 Page 19 of 20

August 6, 2015
Shrink Small Outline Plastic Packages (SSOP)
N M28.209 (JEDEC MO-150-AH ISSUE B)

28 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA H 0.25(0.010) M B M
INCHES MILLIMETERS
E
GAUGE SYMBOL MIN MAX MIN MAX NOTES
-B- PLANE
A - 0.078 - 2.00 -
1 2 3 A1 0.002 - 0.05 - -
L A2 0.065 0.072 1.65 1.85 -

SEATING PLANE 0.25
B 0.009 0.014 0.22 0.38 9
0.010
-A- C 0.004 0.009 0.09 0.25 -
D A
D 0.390 0.413 9.90 10.50 3
-C- E 0.197 0.220 5.00 5.60 4

e A2 e 0.026 BSC 0.65 BSC -
A1
C H 0.292 0.322 7.40 8.20 -
B 0.10(0.004)
L 0.022 0.037 0.55 0.95 6
0.25(0.010) M C A M B S
N 28 28 7
NOTES: 0 8 0 8 -
1. Symbols are defined in the MO Series Symbol List in Section 2.2 Rev. 2 6/05
of Publication Number 95.
3. Dimension D does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.20mm (0.0078 inch) per side.
4. Dimension E does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.20mm (0.0078
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
9. Dimension B does not include dambar protrusion. Allowable
dambar protrusion shall be 0.13mm (0.005 inch) total in excess of
B dimension at maximum material condition.
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
Copyright Intersil Americas LLC 2001-2015. All Rights Reserved.

All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html

Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN3980 Rev 19.00 Page 20 of 20

August 6, 2015

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DATASHEET

HIN202, HIN206, HIN207, HIN208, HIN211, HIN213 FN3980

The HIN202, HIN206, HIN207, HIN208, HIN211, HIN213 Features

HIN202 +5V 2 2 4 Capacitors No/No 0

HIN206 +5V 4 3 4 Capacitors Yes/Yes 0

HIN208 +5V 4 4 4 Capacitors No/No 0

HIN211 +5V 4 5 4 Capacitors Yes/Yes 0

HIN213 +5V 4 5 4 Capacitors Yes/Yes 2

FN3980 Rev 19.00 Page 1 of 20

Ordering Information Ordering Information (Continued)

HIN202CBZ 0 to 70 16 Ld SOIC (W) M16.3 HIN208CBZ 0 to 70 24 Ld SOIC M24.3

HIN202CBNZ-T 0 to 70 16 Ld SOIC (N) M16.15 HIN208CBZ-T 0 to 70 24 Ld SOIC M24.3

HIN207CAZ-T 0 to 70 24 Ld SSOP M24.209 HIN213CAZ-T 0 to 70 28 Ld SSOP M28.209

FN3980 Rev 19.00 Page 2 of 20

VCC Power Supply Input 5V 10%, (5V 5% HIN207).

V+ Internally generated positive supply (+10V nominal).

V- Internally generated negative supply (-10V nominal).

GND Ground Lead. Connect to 0V.

C1+ External capacitor (+ terminal) is connected to this lead.

C1- External capacitor (- terminal) is connected to this lead.

C2+ External capacitor (+ terminal) is connected to this lead.

C2- External capacitor (- terminal) is connected to this lead.

TOUT Transmitter Outputs. These are RS-232 levels (nominally 10V).

NC No Connect. No connections are made to these leads.

FN3980 Rev 19.00 Page 3 of 20

R2IN 8 9 R2OUT VCC 9 16 R3IN

FN3980 Rev 19.00 Page 4 of 20

T3OUT 1 24 T4OUT T2OUT 1 24 T3OUT

FN3980 Rev 19.00 Page 5 of 20

NOTE: R4 and R5 active in shutdown.

FN3980 Rev 19.00 Page 6 of 20

Absolute Maximum Ratings Thermal Information

FN3980 Rev 19.00 Page 7 of 20

VOLTAGE DOUBLER VOLTAGE INVERTER

S1 C1+ S2 V+ = 2VCC S5 C2+ S6

FIGURE 1. CHARGE PUMP

FN3980 Rev 19.00 Page 8 of 20

Detailed Description Receivers

FN3980 Rev 19.00 Page 9 of 20

Typical Performance Curves

SUPPLY VOLTAGE (|V|)

FIGURE 5. V- SUPPLY VOLTAGE vs VCC FIGURE 6. V+, V- OUTPUT VOLTAGE vs LOAD

Test Circuits (HIN202)

8 R2IN R2OUT 9 TTL/CMOS OUTPUT

FIGURE 7. GENERAL TEST CIRCUIT FIGURE 8. POWER-OFF SOURCE RESISTANCE

FN3980 Rev 19.00 Page 10 of 20

15 SIGNAL GROUND (7)

FIGURE 9. SIMPLE DUPLEX RS-232 PORT WITH CTS/RTS HANDSHAKING

15 SIGNAL GROUND (7)

FN3980 Rev 19.00 Page 11 of 20

Metallization Mask Layout

SHD EN R4IN R4OUT T4IN T3IN R5OUT R5IN

R2OUT T2IN T1IN R1OUT R1IN GND

FN3980 Rev 19.00 Page 12 of 20

DATE REVISION CHANGE

Reliability reports are also available from our website at www.intersil.com/support

FN3980 Rev 19.00 Page 13 of 20

Dual-In-Line Plastic Packages (PDIP)

FN3980 Rev 19.00 Page 14 of 20

Small Outline Plastic Packages (SOIC)

N M16.15 (JEDEC MS-012-AC ISSUE C)

FN3980 Rev 19.00 Page 15 of 20

Small Outline Plastic Packages (SOIC)