2.

Analog layout design

Kanazawa University
Microelectronics Research Lab.
Akio Kitagawa
 Well structures
n-well n-well process
p substrate

p-well p-well process

n substrate

n-well p-well Twin-well process

(The impurity concentration is
p- or n- substrate optimized.)

n-well p-well Triple-well process

n-well (The wells can be electrically
p- substrate isolated each other.)
2
 Deep n-well (Triple-well process)
Triple well process Twin-well process
active
(MOSFET) active
n-well (MOSFET)
deep n-well

retrograde p-well n-well

active active
FOX FOX FOX FOX
p n-well p n-well
n-well
deep n-well
p-substrate p-substrate

3
 Shallow trench isolation (STI)
Field Active Field Active Field
isolation MOSFET isolation MOSFET isolation

SiO2 FOX GOX FOX GOX FOX

VDD cannot invert the MOS interface. Si

FOX: Field Oxide (Thickness = 100nm)

GOX: Gate Oxide (Thickness = several nm)

4
 Layout and cross section (Twin
well)
poly (G) poly (G)
contact S D Contact S D

B
Wn Wp
B
p-active n-active
n-active p-active n-well
Ln Lp
B S G D contact B S G D
D D
Field Oxide
FOX p+ n+ n+ FOX n+ p+ p+ FOX
n-well
p-substrate
n-ch MOSFET p-ch MOSFET
5
Layout and cross section (Triple well)

contact poly (G) Contact poly (G)

S D S D

B
Wn Wp
B

p-active n-active n-active p-active n-well

Ln Lp
B S G D contact B S G D
D D
Field Oxide
FOX p+ n+ n+ FOX n+ p+ p+ FOX
n-well
deep n-well
p-substrate
n-ch MOSFET p-ch MOSFET
6
 Layers Legend of layers
n-well
Layer numbers are assigned to Well, n-active (n+)
Active, Poly, Contact, Metal, Via, Silicide p-active (p+)
Protect, and Dummy, respectively. poly
contact
Some layer is automatically generated
from the pattern on the drawn layer. metal-1
via-1
ex. FOX and GOX is generated from the
pattern on the active layer. metal-2

poly layer metal-2 layer

via layer
metal-1layer
poly contact layer
n+ p+ p+ FOX
p-active layer
p-sub n-well
n-well layer
Layout n-active layer Cross section 7
 Design Rules
Semiconductor foundry allows the designers to design only the layout
pattern on the top view.
The thickness of layers are fixed by the semiconductor foundry.
The designers have to design the layout according to design rules which
is fixed for each technology. The purpose of design rule is as follows.
Warranty of dimensional precision in micro fabrication
Warranty of precision on electrical characteristics
Prevention of latch-up(NOTE) triggered by parasitic bipolar-transistors
Design rule violation is automatically detected and reported in DRC
(Design Rule Check).
A semiconductor company accepts only the design that is passed the
specified design rules.
NOTE: Latch-up
The inadvertent creation of a low-impedance path between the power supply rails
of a CMOS circuit, triggering a parasitic pnpn or npnp structure.
8
 Example of design rules (1)
Geometry Rules
n-well

p-active contact
1
Metal-1
poly-1 2 2
2 2
2
2
2
1

2 2
1
1
Via-1
2

poly rule active (p+, n+) rule metal-1 rule

min. width = 2 min. width = 2 min. width = 2
min. spacing 2 min. spacing to well = 2 (inside) min. spacing = 2
min. spacing to well = 1 (outside) min. extension beyond contact = 1
min. spacing to poly = 1 min. extension beyond via-1 = 1

9
 Example of design rules (2)
Minimum Density Rules Antenna Rules
(Process-Induced Damage Rules)
Fine featured processes utilize The "Antenna Rules" deal with process
CMP (Chemical-Mechanical induced gate oxide damage caused when
Polishing) to achieve planarity. exposed poly-silicon and metal structures,
Effective CMP requires that the connected to a thin oxide transistor, collect
variations in feature density on charge from the processing environment (e.g.,
a layer be restricted. reactive ion etch) and develop potentials
sufficiently large to cause Fowler Nordheim
SF(poly) current to flow through the thin oxide. The
rules require that the area of the polysilicon
SF(M1) and metal over field oxide divided by the area
of the transistor gate (thin oxide area) must be
less than Np (where Np is a limit that depends

on the process and on design targets).
SG 10
 Verifications of the layout design
DRC (Design Rule Check)
Detection of the design rule violation
ERC (Electrical Rule Check)
Detection of the open/short error
LVS (Layout VS Schematic)
Equivalence checking between layout and
schematic
The layout design checker has a batch processing mode and
interactive mode.
11
 Influence on circuit performance of
the layout
Frequency response in high-frequency region
The parasitic resistance and the parasitic capacitance raise an
unintended pole and zero.
The long interconnect acts as a parasitic inductor or LC resonator.
Precision of the circuit operation
Common centroid layout of MOSFET, C, and R can improve the
production tolerance and mismatch.
Symmetric layout of interconnect can improves the production
tolerance and skew of the digital signal (delay) and analog signal
(phase lag).
Noise and jitter characteristics
The parasitic resistance, especially poly-Si, act as a thermal noise
source.
The parallel placement of interconnect raise a crosstalk of signals. 12
(1) Layout of the MOSFET

13
 Layout sample of MOSFET
n-well
n-ch p-ch n-active (n+)
p-active (p+)
poly
contact
G G metal-1
via-1
metal-2

S D D S

B B

14
 Parasitic of MOSFET
Parasitic Drain junction
D capacitance
Long W
LD D
C j W LD
L G G B
W
LS S RG R C j W LS
L CgsWL
B
Gate resistance
(R: sheet S
resistance) Gate-Source capacitance
Long W: large time constant of gate poly-Si
Long W: large thermal noise of gate poly-Si
Long LD, LS: large parasitic capacitance and resistance of drain/source area
Few number of contact: Shift or fluctuation of substrate potential
How can you design the MOSFET with larger W? 15
 Fingered MOSFET
MOFET should be W/4
sectioned to reduce High-performance MOSFET array
the gate resistance.
W 1
R
L gm
Finger
gm: trans-conductance
Abutment
dI ds
g m y21 G S
dVgs
D
This condition is
often met in the case
of W/L < 20.
W/L < 10 is B
recommended.
Multiply = 4 (W/4 4) 16
Reduction of the drain junction
capacitance (single MOSFET)
S
D Abutment
G LD D
LD S
W S
W/2

W
C DB C jWLD > C DB C j LD
2
Cj = Capacitance of drain bottom pn junction per area (F/m2)

17
Reduction of the drain junction
capacitance (series MOSFET)
D
LD Abutment
D
S
SLGmin D/S
LD D
S
S W

W
C p 2C jWLD > C p C jWSLG min
Cj = Capacitance of drain bottom pn junction per area (F/m2)
SLGmin = minimum gate spacing
18
 Dummy gate
The dummy pattern may be formed to reduce the production tolerance.

G
B
D

Dummy gate Dummy gate 19

 Interdigitated body contact
The body/well contact may be added to immobilize the
substrate/well potential in the very large MOSFET.
G
B
D

S
20
 IN1 IN2 OUT
VDD

Layout of logic gate

High area utilization
Constant height of all cell
Horizontal runs of metal are used to
supply power (Rail), and vertical runs
of metal (or poly) are used to input
and to output the signals.
2NAND
Outline box of the cell

poly-1 n-well
n+ Metal-1
p+ Metal-2
Contact Via-1
VSS 21
 Matching layout
Matching layout is used to enhances the relative
precision of device pair (e.g. a differential pair, a
current mirror). (around 1%)
Use of The repeat of warp of the fundamental unit
The devices of the different shape and direction match very
poorly.
Use of the dummy pattern
Use of the common centroid pattern
Trimming is necessary if you expect more precise
matching.(less than 0.1%)
22
 Distribution of GOX thickness

Flux of O2
G G

GOX GOX
Temperature and flow
n+ n+ FOX n+ n+ FOX
distribution in the oxidation S D S D
furnace

Distribution of GOX thickness

Fluctuation of Vth and Ids

several %
23
 Common centroid layout
The fluctuation of the device characteristics may be
canceled using the common centroid.
1. The centroid of the matched devices should coincident.
2. The array should be symmetric around both the x and y-axis.
3. Each matched device should consist of an equal number of segments
oriented in either direction.

A B B A A B A B B A A B B A

4 segments B A B A A B B A A B
4 segments 8 segments A B B A
B A A B
16 segments24
 Segmentation and Placement for
common centroid layout
W/2
MOSFET A
W

Dummy Dummy

D D
GA GB
Matched
devices S S
GB GA
MOSFET B
D D
Dummy Dummy

25
Distribution of device parameter
Layout sample of a differential pair
VSS D2 D1 D2 VSS

Dummy Dummy
G2 S12 G1 S12 G2
poly-1 D1 D2
Metal-1
n+ Metal-2
G1 G2
p+ Via-1
Contact VSS S12 26
(2) Layout of the passive devices

27
Example of the characteristics of
the passive device
Component Values Mismatch Temp. Volt.
Coefficient Coefficient
MOS Cap. 2.2 2.7 0.05% 50 ppm/ 50 ppm/V
fF/m2
Poly2/Poly1 0.8 1.0 fF/ 0.05% 50 ppm/ 50 ppm/V
Cap. m2
p+ Resister 80 150 / 0.4% 1500 ppm/ 200 ppm/V
p+ diff. Resistor 50 80 / 0.4% 1500 ppm/ 200 ppm/V
Poly Resistor 20 40 / 0.4% 1500 ppm/ 100 ppm/V
N-well Resister 1 k 2k / 1% 8000 ppm/ 10k ppm/V
The mismatch error on a chip is very small.

28
 Structure of MIM capacitor
Poly Capacitor (Before 0.25m CMOS process)
MIM Capacitor (After 0.18m CMOS process)

VDD VDD
(Shield) (Shield) Metal-x+1

Capacitor Metal
Poly-2
Poly-1
Metal-x
N+ N+
FOX(SiO2 FOX(SiO2
N-well N-well
P-substrate P-substrate
Poly Capacitor MIM Capacitor
29
 Layout sample of a MIM capacitor
Metal-5 Metal-4

CMIM Dummy CM

Cp

Device model with parasitic CM

Metal-4
Capacitor Metal (CM)
Metal-5 MIM Capacitor with the dummy CM
VIA4
Dummy (The dummy metal is automatically inserted, if the dummy is not
specify. The dummy metal may work as a parasitic capacitance.) 30
 Structure of spiral inductor
Metal-4 CP

Top metal
Metal-1 CF
L RS
CF

Slit (prevent the Device model with the parasitic

induction current) Top Metal

Top Top metal or dedicated layer for

VIA4 inductor is used.
M4
The inductor is dissipative in the
M1 VSS chip area.
(Shield) FOX(SiO2)

Substrate
Cross section
31
 Structure of the resistance
Active Active Active
M1
Protect M1
VDD
(Shield) P+ FOX N+ FOX
N+ N-well N-well
Silicide
P-substrate P-substrate

p+ resistor n-well resistor

M1
VDD
(Shield) Poly

N+ FOX
N-well

P-substrate

poly resistor 32
Layout sample of a poly resistor
L
R RS (recommended L/W > 5)
W
RS : SheetResistance

poly Device model with the parasitic

Metal-1

L
Protect (non-silicide area)
p-select, n-select or high-resistance 33
 Common centroid layout of a
resistor pair
R Dummy

R
R2

R2

Dummy
Metal-1 p+ diffusion
34
(3) Shielding and guard ring

35
 Type of noise
Inherent noise
Noise resulting from the discrete and random movement of charge
in a device
Thermal noise, Flicker noise, shot noise
The noise floor depends on the circuit design quality
Quantization noise
Noise resulting from the finite digital word size
The SNR (signal-to-noise ratio) depends on the accuracy of ADC
and DAC.
Coupled noise (Crosstalk)
Noise resulting from the signals adjacent circuits deeding into each
other
The noise immunity depends on a layout.
36
 Type of coupled noise

Electromagnetic model Circuit model

Capacitive coupling Parasitic capacitance
Inductive coupling Parasitic inductance
Substrate current Parasitic resistance

37
 Capacitive coupling
Analog circuit
Vdig
Digital signal
Cc
Vanalog
Analog signal Vsig Rout Cs

Analog circuit
1 Vsig
SNR
j Cc Rout Vdig

38
 Shielding of interconnects
Shielding plate Shielding line
Signal
W Analog circuit Digital circuit
Digital line

3W p-substrate p-substrate
GND

Analog line
analog VSS

39
 Shielding of substrate

Analog signal Capacitor

Digital signal VDD VDD

FOX FOX
n+ n+
Shield Shield
Noise
(charge and discharge) n-well

p-substrate

Cross section

40
 (absorption of

(termination of
Guard ring minority carrier)
n-guard ring
electric field)
p-guard ring

Digital circuit
Analog circuit (noise source)

p-substrate
analog VSS

digital VDD digital VSS

41
 Inductive coupling

Analog circuit The induction noise is in

Magnetic flux proportion to the loop area S
S of the signal and power line.
I2(t) GND

I2(t)
I1(t)
Digital signal current I1(t)
Current

42
 Translational symmetric layout
(In-phase circuit)

magnetic flux magnetic flux
Analog circuit Analog circuit

VDD VSS VDD VSS

The translational symmetry reduces The mirror symmetry intensifies

induced current. the induced current. 43
 Pin assignment
The analog input should be arranged in a perpendicular
direction on digital output and the power supply pin.
Vin

VDD
Adjacent placement
Analog Circuit VSS

Increase the distance

Digital Circuit VDD
Vout Adjacent placement
VSS

44
 Bypass capacitors on VDD, VSS
lines
p-substrateVSS

VDD

The noise in the VDD, VSS line is

bypassed through the bypass capacitors. Small MOS capacitors
under the power line.
45
(4) ESD (Electrostatic Discharge)
Protection

46
 Input Pad with ESD protection
The ESD protection is required to prevent the damage of the GOX of
a MOSFET from the static charge buildup.

VSS Input Pad VDD

Input VDD
Pad FOX FOX
CMOS p+ n+
Circuit n-well

VSS p-substrate

Schematic Cross section

NOTE: If the inductive load is used the output, the amplitude of the output
signal is larger than power supply voltage. In this case, the ESD protection
diode must be connected tandemly. 47
Layout sample of pad ESD protection
Pad
Layer
n-well
n-active (n+)
p-active (p+)
poly-1
contact
metal-1
via-1
metal-2

VDD

VSS
Input 48