VLSI Circuits and Design 10EE764

UNIVERSITY QUESTION BANK

UNIT 1
1. Explain the action of enhancement mode transistor for different values of Vgs and Vds
[07 marks , June/July2016]
2. How is an nMOS transistor fabricated? Explain with neat sketches
[10 marks, July 2014, June/July2016]
3. What is a tristate inverter? Explain. [03 marks June/July 2015]
4. Explain the fabrication steps in P-well CMOS fabrication. [10 marks, June 2014]
5. Obtain the dc transfer characteristics of a CMOS inverter and mark all the regions
showing the status of PMOS and NMOS. [10 marks, June 2014]
6. Explain the Nmos fabrication process, with neat diagram. [10 marks, June /July2015 ]
7. Explain the influence of n/p on the DC transfer characteristics of inverter.
[05 marks, June 2014]
8. Describe in detail step-by-step procedure of P-well CMOS fabrication.
[08 marks, Dec/Jan- 2014/15 ]
9. Explain the transfer plot of CMOS inverter with necessary expression for Vout in each
region. [08marks, June 2014]
10. Write a note on transmission gate. [04 marks, June/July 2015 ]
11. Bring out the salient features of fabrication of P-well CMOS inverter.
[8 marks, June/July15]
12. With neat diagrams, explain the working of enhancement mode NMOS transistor, for
different values of Vds. [8 marks, June 15]
13. What are the advantages of N-well CMOS circuits? List the main steps involved in N-
well CMOS fabrication? [6 marks, Jan/Feb 14]
14. Draw the structure of a P-well CMOS inverter. Neatly label the parts
[4 marks, Jan/Feb 14]
15. Explain the procedure for producing E beam mask. [June/July2016]

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VLSI Circuits and Design 10EE764

UNIT 2
1. What is noise margin? Obtain the values of Vil, Vih, Vol, & Voh from transfer
characteristics of a typical inverter. [06 marks, June 2014]
2. What is -based design? What are the merits and demerits.
[04 marks, Dec/Jan- 2014/15]
3. Compare CMOS and bipolar technologies. [04 marks, June 2013, June/July2016]
4. Explain the transmission gate operation. [04 marks, June2015 ]
5. Draw -based design rules for double metal CMOS process for layers and transistors.
[08 marks, June/July2016]
6. Draw the circuit diagram and stick diagram for nand gate. [04 marks, June/July2016]
7. Draw the circuit schematic and stick diagram for CMOS 2 input NOR gate.
[07 marks, June 2015]
8. With neat sketches, explain based design rules for pMOS, Nmos and nMOS depletion
mode transistor. [06 marks, Dec/Jan- 2014/15]
9. list the colour, stick encoding, mask layout encoding, layers for a simple metal Nmos
process. [07 marks, June2015]
10. Show that pull up-to-pull down ratio for nMOS inverter driven through one or more pass

transistor, is [8marks, June 15, June/July2016]

11. Explain the working of Bi-CMOS inverter with and without static current flow.
[Jan/Feb 14, 6marks]
12. With a circuit, explain two different forms of pull up for inverter. [Jan/Feb 14, 6marks]
13. Show that pull-up to pull-down ratio for an nMOS inverter, driven through one or more
pass transistor, is 8:1 [June/July2016, 7marks]
14. With neat circuit diagrams, explain the merits and demerits of BiCMOS inverter
configurations. [Dec/Jan- 2014/15, 6marks]

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VLSI Circuits and Design 10EE764

UNIT 3
1. Give the -based design rules for different layers, p and n MOSFETS and contact cuts.
[08 marks, June/July2016]
2. Explain the operation of CMOS dynamic logic. Discuss the merits and demerits.
[06 marks, June/July2016]
3. Obtain the stick diagram and layout of a two-way selector with enable.
[06 marks, June 2014]
4. Draw the circuit schematic and stick diagram of CMOS 2- input NAND gate.
[06 marks, June2015]
5. Explain different types of pseudoNMOS logic. [07 marks, June2015]
6. Explain CMOS domain logic and derive the evaluation voltage equation.
[08 marks, Dec/Jan- 2014/15]
7. Explain 2-input x-nor gate in pass transistor logic. [05 marks, June2015]

8. Realize Z= for a clocked CMOS logic.

[06 marks, June 2014]
9. What are the properties of nMOS and pMOS switches? How is transmission gate useful?
[08 marks, June/July2016]
10. Discuss the latch up in CMOS with p-well or n-well structure. [Jun/July 15, 6marks]

11. Bring out lambda based nMOS design rules, with examples. [Jun/July 15, 6marks]
12. Bring out micron rules for CMOS with examples, giving the difference between burled
and butting contact [Jan/Feb 14, 8marks]
13. Draw the stick diagram and layout for an NMOS two way selector , with enable input.
[Jun/July 15, 6marks]
14. What are design rules/ Give the significance of lambda based design rules. With neat
diagrams, explain lambda based design rules as applicable to MOS layers and transistors.
[Jun/July 15, 8marks]
15. What are the advantages of a complementary transistor pull-up, for an inverter? With
relevant diagrams, explain the CMOS inverter operation in different regions.
[6marks, Jun/July 15]

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VLSI Circuits and Design 10EE764

UNIT 4
1. What are the features of CMOS domino logic? Explain with neat diagram.
[06 marks, Jule/july 2015]
2. Define sheet resistance and standard unit of capacitance Cg. Calculate ON resistance
for nMOS inverter with Rsn=10k, Zpu=4, & Zpd=1. [06 marks, Jule/july 2015]
3. obtain the expression for total delay for N stages of nMOS & CMOS inverters in terms
of width factor, f and delay . [08 marks Dec/Jan- 2014/15]
4. Explain the terms rise time, fall time, delay time, derive the equation for fall time of
CMOS inverter. [08 marks, June/July 2016]
5. Provide scaling factors for gate area, gate delay, sat current. [06 marks, June 2014 ]
6. Explain briefly the wiring capacitances. [06 marks, Jule/july 2015]
7. What are the scaling factors of i) Parasitic capacitance Cx ii) Power dissipation per unit
area Pa. [04 marks, June 2014]
8. Calculate the ON resistance for nMOS inverter with Rsn=10k, Zpu=8 and Zpd=1.
[4marks, Jule/july 2015]
9. What are the possible effects of propagation delay in cascaded pass transistor chain and
long polysilicon wires? [12 marks, Jule/july 2015]
10. What is sheet resistance? Calculate sheet resistance of transistor channel if
if n transistor channel [Jan/Feb 14, 4marks]
11. Derive an expression for rise time and fall time of CMOS inverter.
[Jule/july 2015, 6marks]
12. Calculate the resistance between Vdd and Vss of an NMOS inverter with pull-up to pull-
down ratio=4 and show that the ratio rule does not apply for CMOS inverter. Take
lambda=5micrometer. [June/July 2015, 6marks]
13. Calculate the total capacitance in pico farads between the substrate and the structure
shown in fig for lambda=5micrometer. Use standard values.
[Dec/Jan- 2014/15, 7marks]

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VLSI Circuits and Design 10EE764

14. Give the concept of sheet resistence, square capacitance and delay unit.
[June/July 16, 8marks]
15. For cascaded inverters as drivers for large capacitive loads, show that minimum delay for
given where f is the width of the inverter, N is number of
stages. What are super buffer ? Explain. [June/July 16, 10marks]

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VLSI Circuits and Design 10EE764

UNIT 5
1. What are the scaling factors for: Gate capacitance Cg Max. Operating frequency of
Current density J Power speed product Pt [08 marks, Dec/Jan- 2014/15 ]
2. What are the properties of nMOS and pMOS switches? How is transmission gate useful?
3. obtain the logic implementation of 4-way multiplexer using nMOS switches.
[06 marks, Jule/july 2015]
4. Explain restoring logic, in details. [04 marks, June 2014]
5. How to implement the switch logic for 4-way multiplier? Explain.
[08 marks, Jule/july 2015 ]
6. Explain how to implement the switch logic of four way multiplexer, using transmission
gate. [10 marks, Dec/Jan- 2014/15]
7. Explain the dynamic 4-bit shift register, using nMOS logic. [4 marks, Jule/july 2015]
8. Calculate the area capacitance for the following structure if relative capacitances are,

[7marks, Jule/july 2016]

9. For combined voltage and electric field scaling, find scaling factors in terms of alpha,
beta, for the following parameters [6marks, Jan/Feb 14]

10. Discuss limitations of scaling for interconnect and contact resistance.

[7marks, Dec/Jan- 2014/15]
11. Explain different scaling models by considering the relevant diagram of an NMOS
transistor [6marks, Jan/Feb 14]
12. Obtain the scaling factors for the following transistor parameters, by considering the
constant voltage scaling model:

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VLSI Circuits and Design 10EE764

I. Gate area
II. Gate capacitance per unit area
III. Gate capacitance [9marks, Jule/july 2016]
13. By considering a suitable example, compare the metal interconnect and electro-optical
interconnect models. [6marks, June/July 2016]
14. Explain the pre charge bus approach, used in system design. [08 marks, June/July 2016]

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VLSI Circuits and Design 10EE764

UNIT 6
1. How to implement arithmetic and logic operations with a standard adder? Explain with
the help of logic expressions. [07 marks, June/July 2015]
2. Explain structured design approach for a parity generator. [06 marks, June/July 2016]
3. Explain the 4x4 cross bar switch operation. Mention the salient features of sub system
design process. [08 marks, Dec/Jan- 2014/15]
4. How can 4-bit ALU architecture be used to implement an adder. [ 06 marks, June 2014]
5. Discuss the problems associated in VLSI design. [04 marks, June/July 2016]
6. Explain 4-bit Braun multiplier, with net diagram. [10 marks, June/July 2015]
7. For a combined voltage and electric field scaling, show that the scaling factor for
effective voltage Va is (m+)/(m+1) where m is a real number. [6marks, July 14]
8. What are the guidelines for a subsystem design process? Bring out the merits and
demerits between pass transistor and transmission gate. [8marks, Dec/Jan- 2014-15]
9. What are the limitations of sub-threshold current scaling and current density?
[6marks, Dec/Jan 2014-15]
10. Explain the structured design approach for an n-bit bus arbitration logic and draw the
NMOS stick diagram for its basic cell [10marks, July 14]
11. With a suitable example, explain the concept of dynamic CMOS logic.
[10marks, June/July 2016]

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VLSI Circuits and Design 10EE764

UNIT 7

1. What is structured design process? Explain. [08 marks, June/July 2015]

2. What are the system timing considerations? [06 marks, June 2014]
3. Show the functioning of a single transistor dynamic memory cell.[06 marks, June/July 2016]
4. Explain the read and write operations in dynamic memory cell. [06 marks, June/July 2015]
5. Explain boot multiplier, with an example. [08 marks, Dec/Jan- 2014/15]
6. Explain different types of I/O pads. [06 marks, June 2014]
7. Explain the working of one transistor dynamic memory cell, with schematic and stick
diagram. [06 marks, June/July 2015]
8. Explain nMOS Pseudo static memory cell, with stick diagram. [08 marks, June/July 2016]
9. Explain the concept of system partitioning in VLSI chip testing. [06 marks, June 2014]
10. Why NOR gate structure is preferred to NAND for nMOS? Derive an expression for
Zpu/Zpd ratio for NAND and NOR gate. [June/July 2014, 6marks]
11. Explain the pseudo nMOS and CMOS domino logic showing the difference between the two.
[Dec/Jan14, 8 marks]
12. Give the structured design of bus arbitration logic for n-line bus. [Dec/Jan14, 8 marks]
13. What is two phase clocking? Draw and explain a combinational circuit to generate a two
phase clock. [June/July 2016, 6marks]
14. With a neat diagram and relevant expressions, explain the implementation of a 4 bit ALU,
using full adders. [June/July 14, 12marks]
15. What is regularity? Explain. [June/July 14, 2marks]

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VLSI Circuits and Design 10EE764

UNIT 8
1. Write short notes on:
a. I/O pads
b. Test and testability
c. Pseduo nMOS logic
d. Bi-CMOS logic [20 marks June/July 2014]
2. Explain the ground rubs for a system design. [10 marks, June/July 2015 ]
3. Discuss the current limiations for VDD and GND rails [4marks, June/July 2014,]
4. For a 4 bit arithmetic processor, explain any two architectures [6marks, Dec09/Jan14]
5. Give the regular design of an adder cell and show how arithmetic and logical functions
are implemented using adder cell. [10marks, Dec/Jan 2014/15]
6. Write short notes on:
I. Super buffers
II. Barrel shifter
III. Switch Logic
IV. Dynamic shift register. [20marks, June/July 2014]
7. Write a note on testability and testing. [10 marks, June/July 2016]

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