Processes

Dr DC Hendry

February 17, 2006

1 Processes

The VHDL process is certainly the most important modeling construct within VHDL. The
process statement itself is another concurrent statement, and so executes in parallel with
other concurrent statements in the same architecture body. Internally however, the process
statement is sequential. This as we shall see permits a number of sequential statements to
be used to model a particular function of a design. We are all used to writing sequential
code, in languages such as C or C++, and so can readily write such code in VHDL.

Processes in VHDL may be loosely categorised into two flavours, those which include a
sensitivity list, and those which include a wait statement. First, those with a sensitivity
list.

Figure 1 shows an example of a simple process. Figure 2 on the next page shows the syntax
of a process.

HalfAdder : process(a, b)
begin
carry <= a and b;
sum <= a or b;
end process HalfAdder;

Figure 1: A Simple Process

This process is the logic for a half adder. The process is named as HalfAdder, and is
sensitive to the signals a and b. This means that whenever either of the signals a or b
change value then the process is executed from the beginning. So if a or b changes then
new values will be scheduled to be placed on carry and sum after one delay.

Note that no time, not even time passes between the execution of the two assignments.
Thus if signal a changes at time 10 nS, the both of the sequential assignment statements to
carry and sum will be executed at time 10 nS. Both carry and sum will be scheduled then
to be updated at time 10 nS + .

On reaching the end of the process, as it has a sensitivity list (the list in round brackets
consisting of a, b), the process suspends execution.

This is how the real half adder would operate, if either of the input signals changes, then
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the internal circuitry would calculate potentially new output values. The usefullness of
the VHDL process is that we can specify this relationship using a sequential calculation.
Actually its a little bit more tricky than that, but well come to that soon.

Figure 2 shows the syntax of a process. Note that the sensitivity list is optional, and we
will see later how this alternative form of process is used.

[<process-name> : ] PROCESS [<sensitivity-list> ] [<process-declarations>]

BEGIN <process-statements> END PROCESS [<process-name>] ;
<sensitivity-list> ::= ( <signal-name> [, <signal-name> ...] )

Figure 2: Process Syntax

Note also that the process name is optional, but I recommend always including one. This
it turns out make the debugging processor simpler, if you do not give a process a name,
then at debug time you will have to refer to the process by a system generated name. Such
system generated names are seldom memorable!

The <process-statements> part is a list of sequential statements that are executed in

sequence, and in the absence of wait statements, all at the same time. Note also, that
unless the process includes a sensitivity list, once the last statement of the process has been
executed, the process restarts from the first statement, again without any passage of time.

2 Relationship to Concurrent Statements

In this section we will illustrate the correspondence between concurrent assignment state-
ments and processes. As we will see, the concurrent statements we have used to date, are
in fact a shorthand for simple processes.

Consider the VHDL concurrent assignment statement:

x <= a and b;

and the process:

xp : process(a, b)
begin
x <= a and b;
end process xp;

The first statement is in fact simply a shorthand for the process. Both statements require
that whenever a or b change value, that the value of x is scheduled to be updated after one
delay.

In the next example we have two outputs, x and y.

x <= a or b;
y <= b and c;

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and for the process version

xy : process(a, b, c)
begin
x <= a or b;
y <= b and c;
end process xy;

In this case the corresponce is not quite so precise, although the logical effect is identical.
Can you see the difference? If not, consider what happens when a or c changes value.

3 Wait Statement

The second form of process uses a wait statement. A wait statement has a variety of forms:

wait on sensitivity list

wait until boolean expression
wait for time expression

NOTE: When a process without a sensitivity list reaches the last sequential statement, it
immediately continues to execute the first statement.

3.1 wait on sensitivity list

This version of the wait statement is an alternative form of the sensitivity list found at the
head of a process. Placing the sensitivity list in a wait statement gives more flexibility in
constructing the process. It should be said however, that this form of wait statement is
seldom used. Here is an example of such a wait statement:

wait on a, b;

When the process reaches this statement, the process is suspended until one of the signals a
or b changes value. While the process waits for this change to occur, simulation time passes.
Here is yet another way of expressing the concurrent assignment statement:

x <= a and b;

using a process with a wait statement:

xy : process
begin
x <= a and b;
wait on a, b;
end process xy;

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3.2 wait until boolean expression

In this form of the wait statement a Boolean expression is provided. The wait statement
again suspends execution of the process until the Boolean expression is true. The next state-
ment Ill show you is an archetypal synthesis construct - LEARN IT!. Heres the statement
in the context of a process which models a D type flip flop:

dff : process
begin
Q <= D;
wait until clkevent and clk = 1;
end process dff;

Basically this says copy the signal D to the signal Q whenever we see a rising edge on signal
clk. The Boolean expression in the wait statement is:

clkevent and clk = 1

So the expression consists of two parts, both of which must be true for the overall expression
to be true. The first part is clkevent, this uses a signal attribute, event which is true
only when the signal before it has just changed value. The additional condition of clk =
1 makes it a rising edge.

The crucial point here is that this construct is recognised by the synthesis tools, and the
code above will become a positive edge triggered D type flip flop.

3.3 wait for time expression

The last form of wait statement simply specifies a given time interval during which the
process will be suspended. This statement is not synthesisable, it is however widely used
within testbenches.

Here is an example:

wait for 10 nS;

Another very common example to see at the end of a process in a testbench is:

wait;

This is interpreted as wait forever. Remember that once a process has completed
executing all its statements, it returns to the first statement and continues from there. To
avoid a loop, either have a sensitivity list, or include wait statements in the body of the
process. If you want the process to execute once only, use the wait forever statement
above.

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4 Assert and Report Statements

There are a variety of sequential statements that may appear within a process body. We
look at these in the next lecture, after we consider variables. First we look at two very
simple statements that are widely used for simple error checking and reporting. The first of
these, the assert statement was included in the first standard for VHDL. The second, the
report statement is a simplified version of the assert statement introduced in VHDL-93.

4.1 Assert Statement

The assert statement takes the form:

assert <condition>
report <message>
severity <severity-level>;

The idea is that the assert statement checks that <condition> is true, and if not, prints
<message> on the simulator console. The severity level is one of NOTE, WARNING, ERROR and
FAILURE.

Typically a simulator will continue execution for severity levels NOTE and WARNING, but halt
execution for ERROR or FAILURE.

Here is an example:
assert actualSignal = expectedSignal
report Wrong output
severity error;

It became common practice to use:

assert 1 = 0
report Some message to be printed
severity note;

and so in the VHDL-97 the report statement was added.

4.2 Report Statement

The report statement takes the form:

report <message>
severity <severity-level>;

The report statement simply outputs the given message at the given severity level, an
example:
report Verification of Component X Succeeded
severity note;

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