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Chapter one Narrow Band Impedance Matching Networks
Chapter One
Narrow Band Impedance Matching Networks
1. Introduction
This section marks a turning point in that we now begin to apply the theory and techniques of
the previous Semester to practical problems in microwave engineering. We begin with the
topic of impedance matching, which is often a part of the larger design process for a
microwave component or system. The basic idea of impedance matching is illustrated in
Figure 1.1, which shows an impedance matching network placed between load impedance and
a transmission line. The matching network is ideally lossless, to avoid unnecessary loss of
power, and is usually designed so that the impedance seen looking into the matching network
is Z0. Then reflections are eliminated on the transmission line to the left of the matching
network, although there will be multiple reflections between the matching network and the
load. This procedure is also referred to as tuning. Impedance matching or tuning is important
for the following reasons:
Maximum power is delivered when the load is matched to the line (assuming the generator
is matched), and power loss in the feed line is minimized.
linearizing the frequency response of the circuit.
Impedance matching sensitive receiver components (antenna, low-noise amplifier, etc.)
improves the signal-to-noise ratio of the system.
Impedance matching in a power distribution network (such as an antenna array feed
network) will reduce amplitude and phase errors.
As long as the load impedance, ZL, has some nonzero real part, a matching network can
always be found. Factors that may be important in the selection of a particular matching
network include the following:
Complexity-As with most engineering solutions, the simplest design that satisfies the
required specifications is generally the most preferable. A simpler matching network is
usually cheaper, more reliable, and less lossy than a more complex design.
Bandwidth-Any type of matching network can ideally give a perfect match (zero
reflection) at a single frequency. In many applications, however, it is desirable to match a
load over a band of frequencies. There are several ways of doing this with, of course, a
corresponding increase in complexity.
Implementation-Depending on the type of transmission line or waveguide being used, one
type of matching network may be preferable compared to another. For example, tuning
stubs are much easier to implement in waveguide than are multisection quarter-wave
transformers.
Adjustability-in some applications the matching network may require adjustment to match
a variable load impedance. Some types of matching networks are more amenable than
others in this regard.
Fig. 1.1 A lossless network matching an arbitrary load impedance to a transmission line.
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The matching networks may be one of the forms

Matching with Lumped Elements
- L Network
- T & Networks
- Lumped Elements for MIC : Chip R, L, C.
Microstrip Single-Stub and Double-Stub Tuning
Quarter-Wave Transformer
2. Matching with Lumped Elements

In this section L, T and lumped sections will be used to form matching circuits. They are
alternatives employed at low RF frequencies. The basis for these circuits is that for any series
circuit consisting of a series resistance RS and reactance XS there can be found an equivalent
circuit comprising a parallel resistance RP and reactance XP. Fig. 1-2 shows the situation.
From Fig. 1-2 it can be deduced for the series circuit that
Z RS jX S
0.5
Z RS2 X S2 (1-1)
for parallel circuit
jX P RP
Z
RP jX P
X P RP
Z 0.5
(1-2)
RP2 X P2
Equations (1-1) and (1-2) are equivalent so that
X P RP 0. 5
RS2 X S2
2 2 0.5
RP X P
(1-3)
In order to simplify the above expression it is RS XS
necessary to define the quality factor Q for the series and
parallel networks in Fig. 2-3. For the series parallel LR XP
circuits in Fig. 2-3 the quality factors are respectively given
by:
XS
Series circuit Q (1-4a) RP
RS
RP
Parallel circuit Q (1-4b) Z
XP
Fig. 2-2 Series and parallel LR
Equations (2-4) are combined to form:
RP
Q2 1 (1-5)
RS
Equation (2-5) is very significant since it indicates that any two resistances RP and RS can be
matched by carefully controlling the Q of a matching network.
2.1 L-section Lumped Reactive Matching Networks

Probably the simplest type of matching network is the L section, which uses two reactive
elements to match arbitrary load impedance ( ) to generator impedance
( ). There are two possible configurations for this network, as shown in Fig. 1.3.
If the normalized load impedance, zL = ZL/RG, is inside the 1 + jx circle on the Smith chart
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( ), then the circuit of Fig. 1.3.a should be used. If the normalized load impedance is
outside the 1 + jx circle on the Smith chart ( ), the circuit of Fig. 1.3.b has to be used.
The 1 + jx circle is the resistance circle on the impedance Smith chart for which r = 1.
ZG jX2 ZG jX2
jX1 ZL jX1 ZL
(a) (b)
Fig. 1.3 L section matching networks
(a) Network for zL, inside the 1 + jx circle (b) Network for zL outside the 1 + jx circle
The idea of L matching is to put the larger of the two resistances to be matched in
parallel with a reactive element as stated previously. Depending on the position of the first
component (as viewed from the first resistance Z0) an up or downward transformation of the
load resistance can be obtained. The second element in the L-section is used for removing the
residual reactance caused by the transformation element.
In either of the configurations of Fig. 1.3, the reactive elements may be either inductors
or capacitors, depending on the load impedance. Thus, there are eight distinct possibilities for
the matching circuit for various load impedances as illustrated in Fig. 1.4. If the frequency is
low enough and/or the circuit size is small enough, actual lumped-element capacitors and
inductors can be used. This may be feasible for frequencies up to about 1 GHz or so, although
modem microwave integrated circuits may be small enough so that lumped elements can be
used at higher frequencies as well. There is, however, a large range of frequencies and circuit
sizes where lumped elements may not be realizable. This is a limitation of the L section
matching technique.
Fig. 1.4 Eight distinct possibilities for the L section matching networks
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Remarks: How does one choose a circuit among the above possibilities?
There are a number of popular reasons for choosing one over another.
1. Sometimes matching components can be used as dc blocks (capacitors) or to provide
bias currents (inductors).
2. Some circuits may result in more reasonable component values.
3. Personal preference. Sometimes when all paths look equal, you just have to shoot
from the hip and pick one.
4. Stability. Since transistor gain is higher at lower frequencies, there may be a low
frequency stability problem. In such a case, sometimes a highpass network (series
capacitor, parallel inductor) at the input may be more stable.
5. Harmonic filtering can be done with a lowpass matching network (series L, parallel
C). This may be important, for example, for power amplifiers (PA)
We will now derive the analytic expressions for the matching network elements of the
two cases in Fig. 1.3, then illustrate an alternative design procedure using the Smith chart.
2.1.1 Analytic Solutions

Although we will discuss a simple graphical solution using the Smith chart a procedure best
illustrated by an example, it may be useful to derive expressions for the L section matching
network components. Such expressions would be useful in a computer-aided design program
for L section matching, or when it is necessary to have more accuracy than the Smith chart
can provide.
The inputs to the design procedure are the complex load and generator impedances
and . The outputs are the reactances X1 and X2. For either type,
the matching network transforms the load impedance ZL into the complex conjugate of the
generator impedance, that is,
conjugate match (1-6)
Where is the input impedance looking into the L-section:
( )
==
(1-7)
== +
With and . Inserting eqs. (1-7) into the condition (1-6) and equating the
real and imaginary parts of the two sides, we obtain a system of equations for X1 and X2 with
solution for the two types:
Solution for network of Fig. 1.3.a Solution for network of Fig. 1.3.b

= =
1 1
( ) ( )
= 1+ = 1+
5
Remark: The Q quantities play the role of series impedance Q factors as explained before.
Indeed, the X2 equations in all cases imply that the Q is equal to the ratio of the total series
reactances by the corresponding series resistance, that is, or .
2.2 and Sections Lumped Reactive Matching Networks: (three-element matching)

The main disadvantage of the two-element matching is in not having the choice of the
operating Q. The Q for the L-networks is generally very small, and is in fact the lowest
possible value for matching network matching ZG to ZL. This is undesirable since the circuit
will be able to match unequal impedances only. It is useful also to be able to maintain circuit
Q at a value between 10 and 20. A low circuit Q implies that any harmonics present in the
input signal are not readily suppressed. A very high Q may lead to increased circuit losses due
to large currents that flow in the circuit at resonance. Where high Q networks or where large
impedance transformation are required, often three-element circuits (see Fig. 1.5) have to be
employed. These circuits provide the designer the freedom to specify an operating Q
restricted only with the practicability of the resulting component values.
jX1 jX3 jX2

ZG jX2 ZL ZG jX1 jX3 ZL
a) T-matching b) -matching
Fig. 1-5 Three-element matching networks
Two elements in these sections are transforming elements. One of these elements causes
the resistance to increase, while the other to decrease it. The reactance level is set by the last
element in the section. To understand this fact, the circuits of Fig. 1-5 may be regarded as a
cascade of two L-sections.
The T circuit of Fig. 1-5a can be dissected into two L-sections terminated by a hypothetical
resistance ZH (ZH = RH + jXH) as shown in Fig. 1-6.
jX1 jX3
RG jX2 RH jX 2 RL
R1 < RH
L network 1 L network 2
R2 < RH
Fig. 1.6 Dissected T-section
This dissection is very convenient since the rules that apply to the simple L circuit can be
applied to this problem. The only point to note is that the hypothetical resistance must have a
higher resistance than either RG and RL, i.e. the resistances to be matched.
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It should be noted that the parallel combination of X2 and X 2 form the shunt reactance
X2. The design procedure is shown in the following flow chart.
ZG, ZL and Q are known
No Yes
RL < RG
Q1 Q Q2 Q
RH RG Q12 1 RH RL Q22 1
RH RH
X2 X "2
Q1 Q1
X1 X G R1 Q1 X3 XL RL Q2
RH RH
Q2 1 Q1 1
RL RG
RH RH
X2 X2
Q2 Q1
X3 X L RL Q2 X1 X G RG Q1
X2 X2 Here 4 possible circuits

X2
X2 X2 may be obtained.
Design flow chart of the reactive matching T-network
Now that suitable design techniques have been developed to cope with L section and T
section matching circuits, consider next the section shown in Fig. 1-5b. Fig. 1-7 shows a
form of the circuit suitable for discussion.
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jX2 jX 2
ZG jX1 jX3 ZL
RH
RG > RH
L-network 1 L-network 1 RL > RH
Fig. 1-7 Dissected -section
Repeating the development of a design methodology for the T-section but applied to the -
section this time, the -section is dissected into two distinct L-sections. Each of these may
now be analyzed yielding the flow chart shown below.
RG, RL and Q are Known
Yes No
RL < RG
Q1 Q Q2 Q
2 2
R G X G R2
X L2
RH 2 RH L
RG Q1 1 RL Q22 1
X G RG Q2 X" 2 RH Q2
X1
RG X L RL Q2
1 X3
RH RL
RH 1
X '2 RH
Q1
RL X L2 RG X G2
Q2 1 Q1 1
RH RH RL RH RG RH
X" 2 RH Q2 X G RG Q1
X1
X L RL Q2 RG
X3 1
RL RH
1
RH X'2 RH Q1
X2 X2 X2
Design flow chart of the reactive matching -network

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3. Transmission line sections matching networks

At relatively high microwave frequencies, transmission line sections can be used to design
matching networks. This may take one of the forms:
Quarter-wavelength transformers (single or multiple)
Matching stubs (shunts or series, single or multiple)
Tapered transmission lines
Combination of the above
Only the first 2 forms will be studied in this chapter. Although matching two complex
impedances with Transmission line sections is possible we restrict the design in this section to
matching load impedance to characteristic impedance .
3.1 Quarter-Wavelength Transformer with Series Section

The idea is to insert a quarter-wavelength transformer at a distance from the load
corresponding to a voltage minimum or maximum. For example, Fig. 1.8 shows the case of a
single quarter-wavelength section inserted at a distance Lmin from the load. At that point, the wave
impedance seen by the quarter-wave transformer will be real-valued and given by Zmin = Z0 / L, where
L is the SWR of the unmatched load. Alternatively, one can choose a point of voltage maximum Lmax
at which the wave impedance will be Zmax =Z0 L.
Fig. 1.8 Quarter-wavelength transformer for matching a complex load.
The electrical lengths Lmin or Lmax are related to the phase angle L of the load reflection
coefficient L by :
= , = , ( )
(1-8)
= , = , ( )
With is the wavelength at the operating frequency. The impedance of the quarter-wavelength
segment can be calculated simply as:
= = and = = (1-9)
3.2 Quarter-Wavelength Transformer With Shunt Stub

Two other possible methods of matching a complex load are to use a shorted or opened stub connected
in parallel with the load and adjusting its length or its line impedance so that its susceptance cancels
the load susceptance, resulting in a real load that can then be matched by the quarter-wave section.
In the first method, the stub length is chosen to be either /8 or 3 /8 and its impedance is
determined in order to provide the required cancellation of susceptance.
In the second method, the stubs characteristic impedance is chosen to have a convenient value
and its length is determined in order to provide the susceptance cancellation.
These methods are shown in Fig. 1-9. In practice, they are mostly used with microstrip lines
that have easily adjustable impedances. The methods are similar to the stub matching methods
discussed in Sec. 3.3 in which the stub is not connected at the load but rather after the series segment.
9
Fig. 1.9 Matching with a quarter-wavelength section and a shunt stub.
Let = be the load admittance. The admittance of a shorted stub of

characteristic admittance = and length is ( ) and that of an
opened stub, ( ).
The total admittance at point a in Fig. 1.9 is required to be real-valued, resulting in the
susceptance cancellation condition:
+ ( ) = ( ) (1-10)
For an opened stub the condition becomes ( ) . In the first method, the
stub length is d = /8 or /8 with phase thicknesses d = /4 or /4. The corresponding
values of the cotangents and tangents are ( ) ( ) or ( )=
( ) .
Then, the susceptance cancellation condition becomes for a shorted /8-stub or
an opened /8-stub, and for a shorted /8-stub or an opened /8-stub. The case
must be chosen when BL > 0 and , when BL < 0.
In the second method, Z2 is chosen and the length d is determined from the condition
(1-10), ( )= for a shorted stub, and ( ) for an opened
one. The resulting d must be reduced modulo /2 to a positive value.
With the cancellation of the load susceptance, the impedance looking to the right of
point a will be real-valued, = = . Therefore, the quarter-wavelength section will
have impedance:
= = (1-11)
Particular cases
1. If the load is resistive, that is, then the quarter wavelength section is used alone without
stub and its characteristic impedance = .
2. If either of the conditions or + is satis ied then the one section series
impedance transformer of fig. 1-10 can be used.
Fig. 1-10 One-section series impedance transformer.

10
Both the section impedance Z1 and length L1 are treated as unknowns to be fixed by requiring the
matching condition 1 = 0 at the operating frequency. The solution is given by:
( )
= = (1-12)
3.3 Single Stub Matching

We next consider a matching technique that uses a single open-circuited or short- circuited
length of transmission line (a "stub"), connected either in parallel or in series with the
transmission feed line at a certain distance from the load, as shown in Fig.1.11. Such a tuning
circuit is convenient from a microwave fabrication aspect, since lumped elements are not
required. The shunt tuning stub is especially easy to fabricate in microstrip or stripline form.
In single-stub tuning, the two adjustable parameters are the distance, d, from the load to
the stub position, and the value of susceptance or reactance provided by the shunt or series
stub. For the shunt-stub case, the basic idea is to select d so that the admittance, Y, seen
looking into the line at distance d from the load is of the form Y0+ j B. Then the stub
susceptance is chosen as -jB, resulting in a matched condition. For the series stub case, the
distance d is selected so that the impedance, Z, seen looking into the line at a distance d from
the load is of the form Z0 + j X. Then the stub reactance is chosen as -jX, resulting in a
matched condition.
As discussed in the previous course, the proper length of open or shorted transmission line
can provide any desired value of reactance or susceptance. For a given susceptance or
reactance, the difference in lengths of an open- or short-circuited stub is > /4. For
transmission line media such as microstrip or stripline, open-circuited stubs are easier to
fabricate since a hole through the substrate to the ground plane is not needed. For lines like
coax or waveguide, however, short-circuited stubs are usually preferred, because the cross-
sectional area of such an open-circuited line may be large enough (electrically) to radiate, in
which case the stub is no longer purely reactive.
Fig. 1.11 Single-stub tuning circuits;

11
(a) shunt stub,

(b) series stub.
Below we discuss both Smith chart and analytic solutions for shunt and series stub
tuning. The Smith chart solutions are fast, intuitive, and usually accurate enough in practice.
The analytic expressions are more accurate, and useful for computer analysis.
i) Shunt Stubs
The single-stub shunt tuning circuit is shown in Fig.1.11.a. To derive formulas for d
and l, let the load impedance be written as ZL = 1/YL = RL + jXL. Then the impedance Z
down a length, d, of line from the load is
( RL jX L ) jZ 0 t
Z Z0 (1.13)
Z 0 j( RL jX L )t
1
where t = tan d .The admittance at this point is Y = G + j B =
Z
where
RL ( 1 t 2 )
G (1.14a)
RL2 ( X L Z 0 t )2
RL2 t ( Z 0 X L t )( X L Z 0 t )
B (1.14b)
Z O [ RL2 ( X L Z 0 t )2 ]
Now d (which implies) is chosen so that G = Y0 = 1/Z0. From (1.14a), this results in a
quadratic equation for t:
Z0 (RL-Z0)t2 2XLZ0 t+(RLZ0-R 2L X 2L ) = 0
Solution for t gives
2
XL RL Z 0 RL X L2 / Z 0
t , for RL Z0 (1.15)
RL Z 0
If RL = Z0 then t = -XL /2Z0. Thus the two principal solutions for d are
1
tan 1 t
d 2 t 0
(1.16)
1
( tan 1 t ) t 0
2
To find the required stub lengths, first use t in (1.14b) to find the stub susceptance, Bs= -B.
Then, for an open-circuited stub,
1 B 1 B
0
tan 1 S tan 1 , (1.17a)
2 Y0 2 Y0
While for a short-circuited stub,
s 1 1 Y0 1 1 Y0
tan tan (1.17b)
2 Bs 2 B
If the length given by (1.17a) or (1.17b) is negative, /2 can be added to give a positive result.
ii) Series Stubs

The series stub tuning circuit is shown in Figure 1.11b. To derive formulas for d and l for the
series-stub tuner, let the load admittance be written as YL = 1/ZL = GL + jBL. Then the
admittance Y down a length, d, of line from the load is
12
( GL jBL ) jtY0
Y Y0 (1.18)
Y0 jt ( G L jBL )
where t = tan d, and Y0 = 1/Z0. Then the impedance at this point is
1
Z=R+jX=
Y
where
GL ( 1 t 2 )
R (1.19a)
G L2 ( BL Y0 t )2
G L2 t ( Y0 tBL )( BL tY0 )
X (1.19b)
Y0 G L2 ( BL Y0t )2
Now d (which implies t) is chosen so that R = Z0 = 1/Y0. From (1.19a), this results in a
quadratic equation for t:
Y0 G L Y0 t 2 2 BLY0 t G LY0 G L2 BL2 0
Solving for t gives
BL G L [( Y0 G L )2 BL2 ] / Y0
t for GL Y0 (1.20)
G L Y0
If Gl = Y0 then t = -BL /2Y0. Then the two principal solutions for d are
1 1
tan t
d 2 t 0
(1.21)
1 1 t 0
( tan t)
2
The required stub lengths are determined by first using t in (1.19b) to find the reactance,
X. This reactance is the negative of the necessary stub reactance, Xs .
Thus, for a short-circuited stub,
1 Xs 1 X
s
tan 1 tan 1 , (1.22a)
2 Z0 2 Z0
while for an open-circuited stub,
1 Z0 1 Z0
0
tan1 tan 1
, (1.22b)
2 Xs 2 X
If the length given by (1.22a) or (1.22b) is negative, /2 can be added to give a positive result.
Remark: the single stub tuner can also be designed using Smith chart graphical procedure as
outlined below:
i) Single Shunt Stub Tuner Design Procedure
1. Locate normalized load impedance and draw VSWR circle (normalized load admittance
point is 180o from the normalized impedance point).
2. From the normalized load admittance point, rotate CW (toward generator) on the VSWR
circle until it intersects the r = 1 circle. This rotation distance is the length d of the
terminated section of the line. The normalized admittance at this point is 1 + jb.
3. Beginning at the stub end (rightmost Smith chart point is the admittance of a short-circuit,
leftmost Smith chart point is the admittance of an open-circuit), rotate CW (toward
generator) until the point at 0 - jb is reached. This rotation distance is the stub length l.
ii) Single Series Stub Tuner Design Procedure
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1) Locate normalized load impedance and draw VSWR circle.

2) From the normalized load impedance point, rotate CW (toward generator) on the VSWR
circle until it intersects the r = 1 circle. This rotation distance is the length d of the
terminated section of the line. The normalized impedance at this point is 1 + j x.
3) Beginning at the stub end (leftmost Smith chart point is the impedance of a short-circuit,
rightmost Smith chart point is the impedance of an open-circuit), rotate CW (toward
generator) until the point at 0 j x is reached. This rotation distance is the stub length l.
3.4 Double Stub Matching

The single-stub tuners of the previous section are able to match any load impedance (as long
as it has a nonzero real part) to a transmission line, but suffer from the disadvantage of
requiring a variable length of line between the load and the stub. This may not be a problem
for a fixed matching circuit, but would probably pose some difficulty if an adjustable tuner
was desired. In this case, the double-stub tuner, which uses two tuning stubs in fixed
positions, can be used. Such tuners are often fabricated in coaxial line, with adjustable stubs
connected in parallel to the main coaxial line. We will see, however, that the double-stub
tuner cannot match all load impedances.
The double-stub tuner circuit is shown in Fig. 1.12a, where the load may be an arbitrary
distance from the first stub. Although this is more representative of a practical situation, the
circuit of Fig. 1.12b, where the load Y 'L has been transformed back to the position of the first
stub, is easier to deal with and does not lose any generality. The stubs shown in Fig. 1.12 are
shunt stubs, which are usually easier to implement in practice than are series stubs; the latter
could be used just as well, in principle. In either case, the stubs can be open-circuited or short-
circuited.
Fig.1.12 Double-stub tuning.

(a) Original circuit with the load an arbitrary distance from the first stub.
(b) Equivalent circuit with load at the first stub.
Analytic Solution
Just to the left of the first stub in Fig. 1.12b, the admittance is
14
Y1 = GL + j(BL + B1), (1.23)

where YL = GL + jBL is the load admittance and B1, is the susceptance of the first stub. After
transforming through a length d of transmission line, the admittance just to the right of the
second stub is
G j( BL B1 Y0t )
Y2 Y0 L (1.24)
Y0 jt ( G L jBL jB1 )
where t = tan d and Y0 = 1 /Z0. At this point, the real part of Y2 must equal Y0, which leads to
the equation
1 t 2 ( Y0 BL t B1t )Y0
GL2 GLY0 2 0 (1.25)
t t2
Solving for GL gives
1 t2 1 4t 2 ( Y0 BLt B1t )2
GL Y0 1 (1.26)
2t 2 Y0 ( 1 t 2 )2
Since GL is real, the quantity within the square root must be nonnegative, and so
4t 2 ( Y0 BL t B1t )2
0 1.
Y0 ( 1 t 2 )2
This implies that
1 t2 Y0
0 G L Y0 2
(1.27)
2t sin2 d
which gives the range on GL that can be matched for a given stub spacing, d. After d has been
fixed, the first stub susceptance can be determined from (1.25) as
Y0 ( 1 t 2 )G LY0 G L2 t 2
B1 BL (1.28)
t
Then the second stub susceptance can be found from the negative of the imaginary part of
(1.24) to be
Y0 Y0GL ( 1 t 2 ) G L2 t 2 G LY0
B2 (1.29)
GL t
The upper and lower signs in (1.28) and (1.29) correspond to the same solutions. The open-
circuited stub length is found as
1 B
0
tan 1 (1.30)
2 Y0
while the short-circuited stub length is found as
1 Y
S
tan 1 0 (1.31)
2 B
B1 for stub 1
Where B
B2 for stub 2
Remark: Given the load impedance, we need to follow these steps to complete the double stub
design:
(a) Find the normalized load impedance and determine the corresponding location on the chart.
(b) Draw the circle of constant magnitude of the reflection coefficient | | for the given load.
15
(c) Determine the normalized load admittance on the chart. This is obtained by rotating -180 on the
constant | | circle, from the load impedance point. From now on, all values read on the chart are
normalized admittances.
(d) Find the normalized admittance at location dstub1 by moving clockwise on the constant | | circle.
(e) Draw the auxiliary circle.
(f) Add the first stub admittance so that the normalized admittance point on the Smith chart
reaches the auxiliary circle (two possible solutions). The admittance point will move on the
corresponding conductance circle, since the stub does not alter the real part of the
admittance.
(g) Map the normalized admittance obtained on the auxiliary circle to the location of the
second stub dstub2. The point must be on the unitary conductance circle.
(h) Add the second stub admittance so that the total parallel admittance equals the
characteristic admittance of the line to achieve exact matching condition.
(1)
(2)
16
(3)
(4)
17
Remark: As mentioned earlier, a double stub configuration with fixed stub location may not
be able to match a certain range of load impedances. This is easily seen on the Smith chart. If
the normalized admittance of the line, at the first stub location, falls inside a certain forbidden
conductance circle tangent to the auxiliary circle (and always contained inside the unitary
conductance circle), it is not possible to find a value for the first stub that can bring the
normalized admittance to the auxiliary circle. Therefore, it is impossible to position the
normalized admittance of the second stub location on the unitary conductance circle.
When this condition occurs, the location of one of the stubs must be changed appropriately.
Alternatively, a third stub could be added. Examples of forbidden regions follow.
18
Chapter Two Use of S-parameters with two port-networks 19
CHAPTER
TWO
USE OF S-PARAMETERS WITH TWO PORT-NETWORKS
1. INTRODUCTION
Network analysis is encountered during almost every phase of the design process. For example, an
amplifier design usually begins by analyzing a number of transistors and selecting one that meets
specifications. The device is then analyzed in more detail to determine the necessary source and load
impedance. Once the impedance is defined, input and output matching networks can be designed and the
complete amplifier analyzed to determine its characteristics. Assuming the design meets specifications,
the ideal circuit model is modified to include non-ideal components and parasitics due to the physical
layout, and then the complete model is analyzed and perhaps optimized. The final step is to determine
production yields based on component and layout tolerances, and then center the design to maximize the
number of production circuits that meet specifications.
This chapter is devoted to the analysis of two-port network, since they play an important role in the
design of two-port microwave systems. Furthermore, most components can be represented as a two-port
network, and many circuits can be modeled by interconnecting these networks using a combination of the
cascade, series, parallel, series-parallel, and parallel-series connections. In a way or another, the
scattering parameters matrix (S-matrix) can be used to characterize these networks and the
interconnecting techniques described in the previous course can be largely used. The S-matrix may not
directly be used, instead, other parameter matrices such as Z, Y, or ABCD derived from the S-matrix are
in place used. The following sections will show some two-port network concepts derived from the
knowledge of the S-matrix.
2. TWO-PORT NETWORK STABILITY

In the two-port network shown in Fig.1-1, oscillations are possible when either the input port or the
output port presents an impedance with negative real part. This occurs when in > 1 or out > 1. If
some passive terminations at the two ports can produce input and output impedances having negative real
parts, the two-port is said to be potentially unstable.
Zin Zout
Two-port
Z1 network Z2
1 in out 2
Fig. 1-1 Stability of two-port network
We suppose that the two-port network is characterized by its scattering matrix given by
S11 S12
S
S21 S 22
So, the input reflection coefficient is given by:
S12 S 21 2
in S11 S11 (2-1)
1 S 22 2
The output reflection coefficient is given by:
S12 S 21 1
out S22
S 22 (2-2)
1 S11 1
The stability of the two port network can be analyzed by graphical technique as follows.
When the two-port network shown in Fig. 1-1 is potentially unstable, there may be values of 1 and 2
for which the real parts of Zin and Zout are negative. These values of 1 and 2 (i.e. regions in the Smith
chart ) can be determined using the following procedure.
First, the regions where values of 2 and 1 produce in = 1 and out = 1 are determined
respectively. Equating magnitude of equation (1-1) and equation (1-2) to unity and solving for the values
of 2 and 1 shows that the solution for 2 and 1 lie on circles whose equations are given by:
S 22 S11 S12 S 21
2 2 2 2 2
(2-3)
S 22 S22
S11 S 22 S12 S 21
1 2 2 2 2
(2-4)
S11 S11
Where S11S22 S12 S 21 (2-4)
The radii and centers of the circles where in = 1 and out = 1 in the 2-plane and 1-plane,
respectively, are obtained from equation (1-3) and equation (1-4); namely
2 values for in = 1 (output stability circle)
S 12 S 21 (2-5)
radius R2 2 2
S 22
S 22 S 11 (2-6)
center 2 2 2
S 22
1 values for out = 1 (input stability circle)
radius R1
S 12 S 21 (2-7)
2 2
S 11
S 11 S 22 (2-8)
center 1 2 2
S 11
With the S-parameters of the two-port network device at one frequency, the expressions (1-5) to (1-8) can
be calculated, plotted. Fig. 2 illustrates graphical construction of the stability circles where in = 1 and
out = 1. On one side of the stability circle boundary, in the 2 -plane, we will have in <1 and on the
other side in >1. Similarly, in the 1 -plane, on one side of the stability circle boundary, we will have
out <1 and on the other side out > 1.
R2 R1
=1 out =1
in 2 1
C2
=1 C1 1 =1
2
2 -plane 1 -plane
Fig. 1-2 Stability circles construction on Smith chart
Next, we need to determine which area in the Smith chart represents the unstable region. In other
words, the region where values of 2 ( 2 <1) produce in >1 and where values 1 ( 1 <1) produce
out >1. To this end, we observe that if Z2 = Z0 then 2 =0 and from equation (1-1) it results that
in = S 11 . If the magnitude of S 11 is less than unity, then in < 1 when 2 = 0. That is, the center of
the Smith chart in Fig. 1-2 represents the stable operating point. On the other hand, if the magnitude of
S11 is greater than unity when Z2 = Z0, then in >1 when 2 = 0, and therefore the center of the Smith
chart in Fig. 1-2 represents the unstable operating point. Same thing applies for the input stability circle.
When S11 <1 and S22 <1, the two-port network is unconditionally stable if K > 1 and < 1.
Where:
2 2 2
1 S11 S 22
k (2-9)
2 S12 S 21
If either S11 > 1 or S22 > 1, the network can not be conditionally stable because the termination 2 = 0
or 1 = 0 will produce in > 1 or out > 1.
In conclusion, this is a summary for the different possible locations for an unstable (or stable) load
reflection coefficients. That is, the locus of 2 such that the output stability circle in = 1.
Note: we determine whether the center of the Smith chart is inside or outside the output stability by
studying the sign of ( 2 - R2 ) which is equivalent to studying the sign of ( S22 2 - 2
)(1 - S11 2).
the same thing applies for the input stability circle by replacing S11 by S22 and S22 by S11.
Case S11 < 1:
S22 > (the center of the Smith chart is outside the stability circle i.e. 2 - R2 > 0 ); the
overlapped area between the stability circle and the Smith chart gives the unstable region as shown in
Fig. 1-3.
S22 < (the center of the Smith chart is inside the stability circle i.e. 2 - R2 < 0 ); the
overlapped area between the stability circle and the Smith chart gives the stable region as shown in
Fig. 1-4.
R2
in =1 2
in =1
in >1
in <1 R2
C2 C2
2 =1 2 =1
in <1
in >1
2 -plane 2 -plane
Fig. 1-3 Smith chart illustrating the unstable Fig. 1-4 Smith chart illustrating the unstable
region in 2 -plane for case S11 < 1 and region in 2 -plane for case S11 < 1 and
S22 > S22 <
Chapter two Use of S-parameters with two port-networks 22
Case S11 > 1:

S22 > (the center of the Smith chart is inside the stability circle i.e. 2 - R2 < 0 ); the
overlapped area between the stability circle and the Smith chart gives the unstable region as shown in
Fig. 1-5.
S22 < (the center of the Smith chart is outside the stability circle i.e. 2 - R2 > 0 ); the
overlapped area between the stability circle and the Smith chart gives the stable region as shown in
Fig. 1-6.
R2
in =1 2
in <1
in =1 in >1 R2
C2 C2
2 =1 2 =1
in >1
in <1
2 -plane 2 -plane
Fig. 1-5 Smith chart illustrating the unstable Fig. 1-6 Smith chart illustrating the unstable
region in 2 -plane for case S11 > 1 and region in 2 -plane for case S11 > 1 and
S22 > . S22 <
3 SIMULTANEOUS CONJUGATE MATCH

Review: General conditions for conjugate power match between a generator and a load
Consider the following circuit
a1
Zg b1
bg
Vg Z0 ZL
Zg, g ZL,
l L
Fig. 1-7 Generator delivering power to a load
For maximum power transfer one must satisfy both

ZL Z g and Z g Z0
The first condition is well known as conjugate impedance match. The second fulfills the requirement for
the generator to deliver all of its available power to the transmission.
If the first conditions is satisfied, then (for l = 0) L g .
The mismatch loss is an important concept in the design of a microwave systems.
Define the conjugate mismatch by the ratio of available power from the generator to the power delivered
to the load (nonreflecting generator):
PA PA 1
Mc 1
PL PA Pref 2
1 L
If both load and generator are reflecting so:
a1 bg b1 g with bg is the wave emitting from the generator.
the net power delivered to the load is
2 2 2 2
PL a1 b1 a1 1 L
Since b1 a1 L then a1 bg a1 L g
bg
or a1
1 L g
2 2
bg 1 L
consequently PL 2
which is function of bg , L , and g.
1 L g
For maximum power transfer ( L g ) substituted to the last equation yields to the available power
from the generator.
2 * 2 2
bg 1 g bg
PA 2 2
*
1 g g 1 g
Accordingly, the conjugate mismatch in the general case is given by:
2
*
PA 1 g g
Mc 1 (2-10)
PL 2 2
1 L 1 g
Utility: if the reflection coefficients L and g and the available power PA are known then PL can be
found.
3-1 STUDY OF TWO-PORT NETWORKS
For two-port networks with K (stability factor) greater than 1, it is possible to simultaneously conjugate
match the two ports to produce maximum possible gain (Gma). Conditions for simultaneous conjugate
match are:
S12 S 21 L *
S11 S11 g (2-11)
1 S 22 L
S12 S21 g *
and S 22 S 22 L (2-12)
1 S11 g
which become
*
1 L S 22 S11 g L S12 S21 0 (2-13)
*
1 g S11 S22 L g S12 S21 0 (2-14)
from which we can write:
*
g S11
L (2-15)
g S 22
*
L S 22
g (2-16)
L S11
Substituting in equation (1-14) yields:
2 B1 C1*
g g 0 (2-17)
C1 C1
2 2 2
with C1 S11 S*22 and B1 1 S 22 S11
The solution for equation (1-17) is found as:

2
B1 1 B1 C 1*
Gm 4
2C1 2 C1 C1
2
C 1* B1 B1
1 (2-18)
C1 2 C1 2 C1
Remark
Equation (1-17) has two solution for Gm . One using the positive sign and the other using the negative
B1
sing in front of the radical. When 1 , the square root is real, and one solution with a magnitude
2C1
greater then one, or negative real, and another with magnitude less then one or positive real. The desired
positive real solution is obtained by selecting the sign opposite that of B1 . A plus sign when B1 is
B1
negative and a negative sign when B1 is positive. However, when 1 , the square root is
2C1
imaginary, and both solutions have magnitudes equal to one. Therefore in examining equation (1-18)
there are four cases to consider as shown below:
B1 > 0 Normal condition B1 < 0

Case 1 Case 2 Case 3 Case4
B1 B1 B1 B1
1 1 1 1
2 C1 2 C1 2 C1 2 C1
K>1 K<1 K>1 K<1
Useful solution given Gm = 1 Potentially unstable Gm = 1
in equation (1-19) not useful eventhough K > 1 not useful
Only case one can produce useful solution (simultaneous conjugate match) since (see exercise proposed
below). Also, B1 < 0 can occur only if the two-port network is potentially unstable. For the useful solution
from the previous table, the expression is given by:
2
C 1* B1 B1
gm 1 (2-19)
C1 2 C1 2C 1
Approximation, for very small values of S12 and , C1 = S11
* 2
S 11 B1 B1
gm 1 (2-20)
S 12 0 C1 2 C1 2C 1
A similar results can be obtained for the load termination as:

* 2
C 2 B2 B2
Lm 1 (2-21)
C 2 2 C2 2C 2
* 2 2 2
with C2 S 22 S11 and B2 1 S11 S 22
Approximation, for very small values of S12 and , C2 = S22
2
S *22 B2 B2
Lm S 12 0
1 (2-22)
C2 2C2 2C 2
Exercise:
B1
Prove that if 1 then K > 1.
2 C1
4 Power gains
Several definitions can be attributed for a two port network regarding the input and/or out reflection
coefficients. Before giving these definitions, it is important to give the representation of a generator.
4- Generator representation
when a generator or source of power is connected to the two port network, the generator emits a wave bG
if a non-reflecting load is connected ( in 0 ). In the general case where the load is not matched,
consider Fig. 1-7. The first wave incident on the two port is bG , which is reflected as bG which in ,
reflected as bG in G , and so on. Thus the sum of the reflected waves coming toward the generator is
bG in
b1 bG in 1 bG in bG in 2 (2-23)
1 bG in
b1
Since in , Equ. (1-23) becomes
a1
bG b1
b1 (2-24a)
a1 G b1
a1 bG b1bG (2-24b)
This is an important relationship in S-parameter analysis. The incident wave on the two-port a1 is not
equal to bG unless the load is non-reflecting, which would give b1 0 .
An alternate expression for a1 is given as follows. Since in b1 , Equ. (1-24b) gives:

a1
a1 bG 1 G a1
bG
bG a1
a1 (2-25)
1 1 G
Generator b1 Two-port Load
in
bG
bG in
bG in G
bG 2
in G
bG 2 2
in G
etc.
Fig. 1-8 Wave reflections at generator port
Now we discuss the power gain definitions. For that, we refer to Fig. 1-9.
ZG
VG M1 Two-port M2 ZL
PA Pin Pavo PL
Available Actual Available Actual
4-2 Transducer power gain
Fig. 1-9 Available power and actual power for a two-port connected to a generator and a load
Power gain is often measured in the laboratory using only a signal generator and power meter. Power
output from the generator is measured. Then the network is connected to the signal source, and the power
is measured at the output of the network. Power gain is defined as the ratio of output power to input
power, or, in the case of decibel measurement referenced to a standard power level, the difference
between output and input readings. Gain measured in this manner is formally defined as :
power delivered to the load PL
GT transducer gain
power available from the generator Pavg
Remark: GT is the most useful gain measurement because it accounts for mismatch loss at both the input
and output ports of the network. We determine the power available from the generator by connecting a
complex conjugate load which results in maximum power transfer. When the network is connected, any
deviation from the complex conjugate impedance results in a portion of the input power reflected back
into the generator. Similarly, any mismatch between the network output and the load is reflected back into
the network, and the measurement reflects the true performance of the network when inserted between the
generator and the load. The expression for the transducer power gain as a function of G, L and all four
S-parameters is given by:
2 2 2
1 G S 21 1 L
GT 2
(2-26)
1 S 11 G 1 S 22 L S 12 S 21 G L
For convenience, the transducer power gain is expressed as a function of the input and output reflection
coefficients as:
2 2 2
1 G S 21 1 L
GT 2 2
(2-27)
1 in G 1 S 22 L
2 2 2
1 G S 21 1 L
GT 2 2
(2-28)
1 S 11 G 1 out L
4-3 Maximum available gain
when the stability factor K is greater than one, the maximum gain is the transducer gain for the
conjugately matched two port network discussed in section 3, or
2 2 2
1 Gm S 21 1 Lm
Gmax 2
(2-29)
1 S 11 Gm 1 S 22 Lm S 12 S 21 Gm Lm
which is known as the maximum gain and defines the highest achievable gain from the stable device. We
can also use expression for Gm and Lm when S 12 S 21 0 to write:
S 21
Gmax K K2 1 (2-30)
S 12
4-4 Available power gain
when designing low-noise amplifiers, the noise figure is primarily determined by the input impedance.
We usually design the input matching network for minimum noise figure and the output matching
network maximum gain. The minimum noise impedance rarely coincides with the complex conjugate
input impedance, causing a mismatch on the input plane. We can define the gain which results when the
input is mismatched and the output matched as:
power available from the network Pava
G A transducer gain
power available from the generator Pavg
The available power gain, GA, is a special case of the transducer gain. It follows by substituting
*
L out in Equ. (1-28), this gives:
2 2
1 G S 21
GA GA G ,S 2 2
(2-31)
1 S 11 G 1 out
4-5 Operating power gain
The design of some networks requires a mismatch at the output port and a match at the input port. For
example, we usually design the output matching network of a power amplifier to provide maximum
output power, or perhaps minimum harmonic distortion at high drive levels, and the input network for
maximum gain. We can follow a procedure similar to that for available gain and define:
power delivered to the load PL
G operating gain
power into the network Pin
*
The operating gain, G, is also a special case of the transducer gain with the input matched or G int
then Equ. (1-28) reduces to:
2 2
1 L S 21
GA GA L ,S 2 2
(2-32)
1 int 1 S 22 L
4-5 Unilateral case
When the input and the output ports are isolated, the device is said to be unilateral. This can be
understood by noting that S 12 0 .
The unilateral transducer gain is found as:
2 2
1 G 2 1 L
GTU 2
S 21 2
(2-33)
1 S 11 G 1 S 22 L
The effect of G mismatch and L can be clearly seen in the Equ. (1-33).
*
For an input and output match, G S 11 and L S *22 , the maximum available gain of Equ. (1-29)
reduces to:
1 2 1
GU max 2
S 21 2
(2-34)
1 S 11 1 S 22
Remarks:
Inspecting Equ. (1-34), we see that the expression consists of three terms. The first term represents the
input mismatch due S11, the second term is the insertion gain of the device, and the third term is the
output mismatch due to S22.
For potentially stable (K < 1) devices, the maximum achievable gain is infinite, but a useful figure of
merit is the maximum stable gain Gms, given by:
S 21 Y21
GmsG (1-35)
S 12 Y12
This is the gain that can be achieved by resistively loading the two port such that K = 1 and then
simultaneously conjugately matching the input and output ports. For conditionally stable two ports, the
maximum stable gain is a helpful limit in power gain that can be approached as the input and output
mismatch is reduced. If a simultaneous conjugate match is attempted, the two port will oscillate if K < 1.
One additional power gain is the unilateral power gain. This is the maximum available power gain
when the two-ports have been simultaneously conjugately matched and the feedback parameter has been
neutralized to zero. The conditions are indicated in Fig. 1-10 for unilateral power gain:
2
S 21 S 12
U *
(1-36)
2 K S 21 S 12 2 e S 21 S 12
Lossless
shunt
feedback
network
S12 2 = U
S12 = 0
Lossless Two-port Lossless
M1 device M2
S11 = 0 (a) S22 = 0
S21 2 = U
S12 = 0
Two-port device Lossless
Lossless
M1 M2
Lossless series
feed back S22 = 0
S11 = 0
(b)
S12 = 0 S21 2 = U
Lossless
M1 M2
Lossless series
feed back
S11 = 0 S22 = 0
(c)
S12 = 0 S21 2 = U
Lossless
M1 M2
Lossless series
feed back
S11 = 0 S22 = 0
(d)
Fig. 1-10 Conditions for unilateral gain: (a) shunt feedback; (b) series feedback
(c) parallel-series feedback; (d) series-parallel
chapter three Amplifier design 30
-
CHAPTER
THREE
AMPLIFIER DESIGN
1. INTRODUCTION
In this chapter we introduce some design principles used for microwave transistor amplifier. The design
procedure is based on the s-parameters of the transistor. The transistor could be a bipolar transistor, a
FET, an HEMT or an HBT. Although modern design procedures are usually carried out using computer-
aided design tools, the use of equations and graphs will help in understanding some fundamental design
principles.
In the task of amplifier design the first, and perhaps most important, step is selecting an active device.
Typically, we look at maximum gain, minimum noise and maximum output power for a number of
devices, select those that best match the design specifications, then make a final decision based on cost,
availability, or a combination of factors.
An amplifier should not oscillate in operating bandwidth. An unconditionally stable transistor
amplifiers will not oscillate under any passive terminations of the input or output circuits. Most modern
active devices are potentially unstable, which means that the device can oscillate under certain passive
terminations. It therefore requires careful design to avoid oscillations. In some cases it is necessary to add
stabilization networks which reduce the gain and output power while increasing the noise figure. A device
that is acceptable before stabilization may not be acceptable after it is stabilized.
Once the device is selected, we must determine the source and the load impedance necessary to
provide the desired performance. We can design input and output matching networks based on source and
load impedance, combine these networks with the active device to confirm that the design meets the
specifications.
2. MICROWAVE AMPLIFIER CONFIGURATION:

Fig. 3-1 shows a microwave transistor amplifier configuration.
bS b1
Z0 PL
Input S11 S12 Output
matchin a1 matchin
g g Z0
Source network network
S21 S22
S in out L
ZS Zin Zout ZL
Fig. 3-1 Transistor amplifier circuit configuration
The circuit consists of an input matching network, a transistor, and an output matching network. The
amplifier is connected to a source within a characteristic impedance Z0 and a load with the same
characteristic impedance.
3. MAXIMUM GAIN DESIGN

In the design of narrowband amplifiers for maximum gain, the input and output matching networks must
transform the source and the load reflection coefficients S and L to the matched counterparts Sm and
Lm as given in (2-19) and (2-21), respectively, when the transistor is unconditionally stable, that is,
K > 1 and < 1 where K and are given by (2-4) and (2-9) respectively. Furthermore, the
unconditional stability criteria can be written as:
-
2 2 2 2
1 S11 S12 S21 B1 1 S11 S 22 0
2 2 2 2
1 S 22 S12 S21 B2 1 S 22 S11 0
Under these conditions, the maximum gain can be found according to the results of chapter two as:
S 21
Gmax K K2 1 (3-1)
S12
2 1
Sm C1* B1 B12 4 C1 2
(3-2)
2 C1
2 1
Lm C*2 B2 B22 4 C2 2
(3-3)
2 C2
with C1 S11 S*22 ; C2 S 22 *

S11 and S11S22 - S12S21
Remark: from equation (3-1) we see that for K > 1 and K 1, the maximum transducer power gain
Gmax S21 S12 . This quantity is called the maximum stable gain of the transistor, that is,
S21
MSG (3-4)
S12
Conclusion: An amplifier can be designed using stable active device by selecting the conjugately
matched input and output terminations. The gain of such an amplifier is the highest gain that can be
delivered from the active device. In this case, the operating gain of the amplifier is the same as the
transducer gain of the amplifier an is given by equation (3-1).
Example # 1: The S-parameters of a GaAs MESFET measured at 6 GHz are given as:
S11 0.614 167.4 S 21 2.187 32.4
S12 0.046 654 S 22 0.716 83
Design a narrow-band amplifier at 6 GHz using the device for maximum gain. Calculate the transducer
power gain.
Solution: First, the FET must be checked for its stability. Using results of chapter one we get =
0.34195 113.16 =0.34195 < 1, K = 1.1296 > 1 and S11 = 0. 614 < 1. Thus the FET is
unconditionally stable. Hence, maximum gain can be achieved by simultaneously conjugate match the
source and load. Using equations 3-2) and (3-3) the required terminations are found as:
Sm 0.868 169.75 Lm 0.9 84.47
The maximum transducer gain is equal to the maximum operating gain for the simultaneously conjugate
matched device, it is given by equation (3-1): GT max G p max 28.7 14.5dB . With the computed
terminations it is now possible to synthesize the input and output matching networks. We will use the
conventional single-stub impedance matching on the Smith chart .
Input matching network
From Sm 0.868 169.75 , the conjugate matched input immittances Zsm and Ysm are located on
the Smith chart in Fig. 3-2. A circular arc whose center the center of the Smith chart is drawn through Ysm
and the upper half of the unit resistance circle at point A (1+ j3.4 ). The distance from Z = 0 to the line
drawn from the center and in tangent with the reactive circle +j3.4 passing through point A is the length
of the input stub in parallel with the 50 source (0.204 in length). The distance from point A to Ysm is
the length of the input line that connects the open stub to the input of the FET (0.056 in length). The
two lines have the same characteristic impedance of 50 .
-
Output matching network

From Lm 0.9 84.47 , the conjugate matched input immittances ZLm and YLm are located on the
Smith chart in Fig. 3-2. A circular arc whose center the center of the Smith chart is drawn through Y Lm
and the Lower half of the unit resistance circle at point A (1- j4.2 ). The distance from Z = 0 to the line
84.47
ZLm
169.75
ZSm
YSm
YLm
Fig 3-2 An input and output matching network design foe Example # 1.
drawn from the center and in tangent with the reactive circle j4.2 passing through point B, which is
0.287 , is the length of the output open stub. The distance from point B to YLm, which is 0.097 ,
Z0 = 50 CB
CB Z0 = 50
L3 = 0.097
L2 = 0.056
L4 = 0.287
50
50
Z0 = 50
Z0 = 50
Fig 3-3 A 6 GHz maximum gain GaAs FET amplifier.

determines the length of the output line that connects the output of the FET to the output shunt open stub.
The two lines have the same characteristic impedance of 50 .
The complete amplifier with input and output matching networks is shown in Fig. 3-3. The capacitors CB
are dc bias blocking capacitors and must be selected to have very low loss at 6 GHz, low impedance
compared to 50 . (you can, if you want build your circuit using microstrip technology).
In this example, the GaAs FET is unconditionally stable at 6 GHz, and the conjugate matching is
possible for maximum gain. When the GaAs FET is potentially unstable, the design must incorporate the
stability condition as illustrated below.
For designs using potentially unstable active devices, the maximum operating gain corresponds to a
source and / or load terminations outside the S and / or L Smith chart. Hence, it is not achievable and is
-
thus meaningless. In designing with potentially unstable devices, one has to give up looking for
maximum gain (conjugate input / output matching), but rather one should be looking for realizable source
and load termination by defining a lower (than maximum) gain. The operating power gain of an active
device for any arbitrarily termination is given by:
2 2
power delivred to the load S 21 1 L
Gp 2 2
input power 1 L S 22 S11 L
Note that G p is independent of S by virtue of its own definition.
Gp
Now let g p 2
denote the normalized power gain, that is,
S21
2
1 L
gp 2 2
(3-5)
1 L S22 S11 L
The locus of all L that results in a constant value of g p is expressed by the circle equation of the form:
2 2
g pC*2 g p S12 S 21 2 g p S12 S 21 K 1
L 2 2
1 g p S 22 2 2 2
1 g p S 22
The center and the radius of circle are:
g pC*2
Center pc 2 2
1 g p S 22
2
g 2p S12 S21 2 g p S12 S 21 K 1
Radius R pc 2 2
1 g p S 22
The circle is known as the constant power-gain circle. The constant power-gain circle is on the Smith
chart of the L plane. It is the locus of the load terminations ( Ls), which when connected to port 2 of the
2
active device will provide an operating gain of S 21 g p .
In amplifier design using potentially unstable device, a set of constant power gain circles is
generated first. A load reflection coefficient L in the Stable region of the L-plane Smith chart, with as
high gain as desired, is selected. The source reflection coefficient S can be found by choosing the
complex conjugate of the input reflection coefficients, i.e.
* S12 S 21 L
S S11
1 S 22 L
*
S11 L
S (3-6)
1 S22 L
Remark: The value of the S as given by equation (3-6) is usable if it falls well inside the stable region of
the S-plane Smith chart. Otherwise, a different value of L has to be selected and the procedures are
repeated until both L and S are on the Stable region.
Example # 2: At 2 GHz, the GaAs FET HFET-1101 biased for maximum gain has the following
scattering parameters:
S11 0.894 60.6 S 21 3.122 123.6
S12 0.021 62.4 S 22 0.781 27.6
Solution: For this transistor, one can obtain = 0.697 -83.1 =0.697 < 1, and K = 0.618 < 1.
Thus according to the stability criteria stated in chapter one, the FET is potentially unstable. We note that
at this frequency, the maximum stable gain is given by (3-4) as MSG = 21.93 dB. In order to select a
stable load, the load stability circle is plotted on the Smith chart in Fig. 3-4. Its center CL and its radius RL
are given by (1-7) and (1-8) L =1.367 46.9 and RL = 0.5. Suppose that we want to design an amplifier
with 20 dB (1.93 dB less than maximum stable gain); thus let Gp = 20 dB. Hence the normalized power
Gp
gain g p 10 . 26 . The 20 dB constant power gain circle with center Cp = 0.766 46.9 and
2
S 21
radius Rp = 0.346 is plotted on the Smith chart of Fig. 3-4. The region of the Smith chart outside the load
stability is the stable load region. Any load in this region an on the 20 dB constant power gain circle will
make the amplifier stable and yield a gain of 20 dB. Select the load reflection coefficient
L 0.42 46.9 that satisfy the above conditions, then according to (3-6), the source reflection
coefficient that together with the selected load yield 20 dB of transducer power gain is given as
S 0.915 62.6 . This source must be a stable source, indeed it is outside the source stability circle
with center S = 1.136 68.4 and radius RS = 0.198. proceeding as in example #1, the input and output
matching circuits are given in Fig. 3-5.
Source stability
circle
L
L
Load stability
S circle
20 dB gain
circle
L
0.036
YL
A
B
0.095
YS 0.129
Fig 3-4 An input and output matching network design for example # 2
Z0 = 50 CB
CB Z0 = 50
L3 = 0.095
L2 = 0.129
L4 = 0.133
50
50
Z0 = 50
L4 = 0.036
Z0 = 50
Fig 3-5 A 2 GHz GaAs FET amplifier.

4. USE OF UNILATERAL TRANSISTORS

For unilateral transistors, S12 = 0. The signal only flows from the input port to the output port of the
device. Most transistors have small S12 values and can be considered as unilateral. Hence:
2 2
1 S 2 1 L
GT GTu 2
S21 2
1 S11 S 1 S 22 L
in S11 and out S 22

The transducer power gain can be optimized by optimizing the input and output matching networks. The
maximum gain occurs when
* *
S S11 and L S* *
in 22 in
1 2 1
GTu max 2
S 21 2
1 S11 1 S 22
Given a unilateral transistor with known S-parameters, an amplifier can be designed with maximum gain
following the procedure given below.
1. Check the stability.
2. Calculate GTu max .
*
3. Find S S11 and L S* .
22
1 S 1 L
4. From S and L, find S and ZL from the Smith chart or Z S
Z L Z0 . Z0
1 S 1 L
5. Design the matching Networks to match Z0 to ZS and Z0 to ZL using the methods described in
chapter two and in the previous course.
5. CONSTANT GAIN CIRCLES FOR THE UNILATERAL CASE

In many design cases, maximum gain may not be desirable due to other considerations, such as noise
figure and bandwidth. The design is accomplished by plotting the constant-gain circles and determining
the S and ZL to meet the requirements.
2 2
1 S 2 1 L
Again GTu 2
S21 2
(3-7)
1 S11 S 1 S22 L
GS G0GL
assuming the unconditionally stable case, S11 < 1 and S22 < 1 then,
2
1 S 1
GS 2
and GS max 2
(3-8a)
1 S11 S 1 S11
2
1 L 1
GL 2
and GL max 2
(3-8b)
1 S 22 L 1 S 22
define normalized gain factors gS and gL as:

2
GS 1 S 2
gS 2
1 S11 0 gS 1 (3-9a)
GS max 1 S11 S
2
GL 1 L 2
gL 2
1 S 22 0 gL 1 (3-9b)
GL max 1 S 22 L
If we fixe gS , the locus of S determines a circle with center and radius of:
*
g S S11
Center S 2
1 1 g S S11
1 gS 1 S11 2
Radius RS 2
1 1 g S S11
Similarly, the constant-gain circles for the output network have:
g L S*22
Center L 2
1 1 g L S 22
1 gL 1 S22 2
Radius RL 2
1 1 g L S 22
Example # 3 a transistor has the following S-parameters at 10 GHz. Draw the constant gain circles for
GS of (a) GSmax, (b) 2 dB, (c) 1 dB, (d) 0 dB and (e) 1 dB.
S11 0.706 160 S 21 5.01 85
S12 0. S22 0.508 20
*
Solution: (a) GSmax = 1.994 = 3 dB, S S11 0.706 160
(b) GS = 2 dB = 1.585, gS = 0.795, S = 0.625 and RS = 0.253.
(c) GS = 1 dB = 1.259, gS = 0.631, S = 0.546 and RS = 0.373.
(d) GS = 0 dB = 1.000, gS = 0.501, S = 0.471 and RS = 0.472.
(e) GS = -1 dB = 0.794, gS = 0.398, S = 0.401 and RS = 0.556.
The constant-gain circles for the stated gains are shown in Fig. 3-6.
160 -1 dB
2 dB 1 dB 0 dB
3 dB
S plane
Fig 3-6 Constant gain circles in S plane
6. LOW NOISE AMPLIFIER DESIGN

The noise figure of a transistor is defined as the amount of noise added by the transistor, i.e.
S
F N in
S
N out
If the transistor is modeled as a two-port network, the noise figure can be expressed as
2
R S opt
F Fmin 4 n 2
(3-10)
Z0 1 1
2
opt S
Where S is the reflection coefficient of the source as seen by the input of the transistor, Fmin is the
minimum (optimal) noise figure when S is set to an optimal level opt . 0 is the system impedance
used to define the S , and Rn is an important parameter known as the equivalent noise resistance of the
transistor.
Remark: the noise performance of an active device is completely described by Fmin , Rn and opt .
These parameters can either be measured or taken from the data sheet of the active device.
The source termination S can be chosen to be opt if the amplifier is to be designed for the lowest
noise figure. This is always possible if the device is unconditionally stable. The output port is normally
conjugally matched for max power transfer to the load, i.e.
S12 S 21 opt S 22 opt
L S 22 (3-11)
1 S11 opt 1 S11 opt
For potentially unstable transistors, it is necessary to ensure that S = opt lies in the stable region of
the source stability circle plot. If the input port stability is not satisfied by S = opt , then a value other
than opt must be chosen for S at the expense of having a noise figure greater than Fmin . After selecting
, whether it is equal to opt or not, conjugate at the output is normally assumed. The
S L so calculated
must also lie within the stable region of the load stability circle plot.
Example # 4 this example demonstrates the design of low noise GaAs FET amplifier using the HFET-
1101 at 6 GHz whose noise parameters at this frequency are given as Fmin 2.2 dB , opt 0.575 138 ,
and Rn 6.64 . The HFET-1101 scattering parameters at minimum noise figure bias are:
S11 0.674 152 S 21 1.740 36.4
S12 0.075 6.2 S 22 0.600 92.6
Solution: For this transistor, one can obtain = 0.385 134.3 =0.385 < 1, and K = 1.275 > 1.
Thus according to the stability criteria stated in chapter one, the GaAs FET is unconditionally stable at
this bias condition. With the minimum noise figure reflection coefficient opt as the source, the load that
produces the maximum gain at the minimum noise bias is given by the cascade load formula in (3-11) as:
S 22 opt
L 0.602 104
1 S11 opt
With these terminations the transducer power gain of this amplifier G = 9.73 dB. The graphical method
of previous examples can be used to synthesize the input and output matching networks. Here we offer
another approach.
Input matching network
The impedance Zopt, corresponding to From opt 0.575 138 is Zopt = 15.32 + j17.6. Hence the
admittance Yopt = 0.028 j0.032. It is seen that Yopt can be realized by paralleling a conductance of 0.027
mhos and a succeptance of 0.032 mhos. To realize the succeptance, we note that an open-circuited stub is
seen to have an input admittance Y = jY0tan and if = 2 l/ = 3 /4 (i.e. l = 3 /8), then Y=-jY0. Thus an
open circuited stub that is three-eight of a wavelength long looks like a shunt element with admittance
jY0. For our case, Y=-jY0 = -j0.032 and thus Y0 =0.032 or Z0 = 31.25 is the characteristic impedance
of the open-circuited stub. Since the source generator is 50 and in order to realize the parallel
conductance element of 0.028 mhos, a quarter-wave transformer (l = /4) of characteristic impedance

1
50 0.028 42.26 is employed. The input matching network is shown in Fig. 3.7.
Output matching network
The output impedance ZL, corresponding L , is ZL = 19.28 + j35.32. Hence the admittance YL =
0.012 j0.022. As above the output matching network can be realized with a three-eights of a wavelength
long open-circuited stub of impedance 45.45 and a quarter-wave transformer of characteristic
impedance 64.55 as shown in Fig. 3.7.
Z0 = 64.6 CB
CB Z0 = 42.3
L4 = /4
/8
L1 = /4 50
Z0 = 45.5
/8
50 Z0 = 31.3
L3 = 3
L2 = 3
Fig 3-7 A 6 GHz low noise GaAs FET amplifier.

7. NOISE CIRCLES
If the design using S = opt is not possible because opt is in the unstable region or is too near to the
source stability circle, we may design for a prescribed noise figure F Fi . To this end we define a
parameter Ni such that
2
S opt
Ni 2
(3-12)
1 S
From equation (3-10), we have
Ni Rn
Fi Fmin 4 rn 2
where rn
1 Z0
opt
Then we can write:
2
Fi Fmin 1 opt
Ni (3-13)
4 rn
Using equations (3-12) and (3-13) one can obtain
S F RF (3-14)
opt 1 2
Where center F and radius N i2 N i 1 RF
opt (3-15)
1 Ni 1 Ni
So the locus S having the same value of Fi defines a family of circles called constant noise figure
circles.
Example # 5 this example is used to demonstrate the design of low noise amplifier at 2 GHz using a
GaAs FET potentially unstable at this frequency. We use an HFET-1101 whose noise parameters and
whose S-parameters at the minimum noise bias are given as Fmin 1.25 dB , opt 0.730 60 , and
Rn 19.4 . And
S11 0.935 51.9 S 21 2.166 128.3
S12 0.045 54.6 S 22 0.733 30.5
Solution: For this transistor, one can obtain = 0.7 -74.4 =0.7 < 1, and K = 0.405 < 1. Thus The
FET is potentially unstable. To check whether the optimum noise source reflection coefficient is a stable
source at 2 GHz, the source stability circle is
plotted on the Smith chart as shown in Fig. 3-8,
with center CS =1.126 61.4 and RS = 0.252.
From Fig. 3-8 it is seen that opt is a stable source
reflection coefficient. To achieve the maximum Source stability
circle Load stability
gain with opt as a source, the load reflection circle
coefficient L must be selected by the cascade min L
load formula (3-11). i.e. L 0.831 44.3 . This L
load reflection coefficient falls inside the load
stability circle with center CL = 2.622 77.4 and
radius RL = 2.06 and hence is not appropriate. The
selection of stable load reflection coefficients must
be such that they can produce gain as high as
possible and can be practically realizable on
microstrip substrates. Based upon these criteria, we Fig 3-8 A low noise amplifier design using
select a new stable load reflection coefficient a potentially unstable GaAs FET
L 0.831 34 that lie outside the load stability
circle as shown in Fig. 3-8. With the obtained terminations the transducer power gain G = 17 dB (the
minimum stable gain is MSG = 16.8 dB). Using the procedure in Example # 4, the input and output
matching networks that realize the terminations are presented in Fig. 3-9.
Z0 = 158 CB
CB Z0 = 110
L4 = /4
/8
L1 = /4 50
Z0 = 167
/8
50
Z0 = 89.5
L3 = 3
L2 = 3
Fig 3-9 A 2 GHz low noise GaAs FET amplifier.
Example # 6 this example shows how to generate the noise circles. Consider the bipolar transistor
HXTR-6105 at 2 GHz whose noise parameters are given as Fmin 2.25 dB , opt 0.429 170 , and
Rn 5.04 . Suppose we want to plot the 3 dB noise figure circle. Then Fi = 3 dB and using (3-13) we
get Ni = 0.261. and Substituting Ni into (3-15) yields F = 0.34 173 and RF = 0.42.
Remark: in many cases, the designer has to compromise noise figure and gain in order to achieve a low
overall system noise figure. Such design can be accomplished systematically using constant noise figure
circles and constant available power gain circles as described in the subsequent discussion.
The available power gain as derived in chapter one is given by:

2 2
S 21 1 S
Ga 2 2 2 2
(3-16)
1 S 21 S S21 2 Re C1 S
Where C1 S11 S*22 . Note Ga is independent of L by virtue of its own definition.

Ga
Now if we let g a 2
denote the normalized available power gain, then (3-16) represents a circle that
S 21
is the locus of all S that results in the same g a .
The center and the radius of circle are:
g aC1*
Center ac 2 2
1 g a S11
2
g a2 S12 S 21 2 g a S12 S 21 K 1
Radius Rac 2 2
1 g a S11
The circle is known as the constant available power-gain circle. The constant available power-gain circle
is on the Smith chart of the S plane. It is the locus of the source terminations ( Ss), which when
2
connected to port 1 of the active device will provide an operating gain of S 21 g a . After S is chosen,
the correct value of L to maximize Ga and to realize the two-port transducer power gain G = Ga is given
by the cascade-load formula as:
S 22 S
L (3-17)
1 S S11
The constant available power gain circle and the constant noise circle can be plotted together on the Smith
chart and their intersections, if they exist, yield the input reflection coefficient S that provides the desired
noise figure and gain.
Example # 7 this example demonstrates the design of a GaAs FET amplifier that compromises between
noise figure and gain at 6 GHz. Typical noise parameters and scattering parameters are given as
Fmin 2.9 dB , opt 0.542 141 , and Rn 9.42
S11 0.641 171.3 S 21 2.058 28.5
and
S12 0.057 16.3 S 22 0.572 95.7
Solution: From the above data = 0.302 109.8 =0.302 < 1, and K = 1.509 > 1. Hence the GaAs
FET is unconditionally stable at this bias condition. The maximum gain is given as Gmax = Ga,max = Gp,max
= 11.36 dB; the gain with the associated minimum noise
is 9.33 dB. We decide that a compromise between noise
figure and gain is necessary if an input reflection 3.15 dB
coefficient S exists. noise circle
Let Fi = 3.15 dB and Ga = 10.55 dB. Fi-circle and Ga- S
circle have centers CF and Ca and radii RF and Ra as S

shown in Fig. 3-9.
CF = 0.507 141 RF = 0.217. 10.55 dB
Ca = 0.691 177.3 Ra = 0.243. gain circle
These two circles intersect at two points. The source
reflection coefficients S and S at these points provide
an amplifier with 3.15 dB noise figure and 10.55 dB
gain. The selection of the source reflection coefficients
Fig 3-9 A noise and gain compromise design
S and S must be such that they and their
corresponding reflection coefficients can be practically
realizable on microstrip substrate. Select S = 0.68 156. Using (3-17) we obtain L = 0.68 156.
chapter four Oscillator design 41
CHAPTER
FOUR
OSCILLATOR DESIGN
1. INTRODUCTION
The design of transistor oscillators is very similar to the design of transistor amplifier. The same dc bias
levels, and the set of S-parameters can be used for oscillator design. The load does not know whether it is
connected to an amplifier or to an oscillator. In the oscillator, the circuit is designed to be unstable.
A number of techniques are available for the design of microwave oscillator. Generally speaking, the
design consists of two parts, namely, the characterization of the active device and the determination of the
embedding elements.
Resonators are normally incorporated into the oscillator design to achieve low noise and high-
frequency stability. The resonator can be a lumped element, a distributed transmission line, a cavity or a
dielectric disk.
In this chapter, we are concerned with the design of microwave oscillator narrow in bandwidth, using
transistors which characterized by their scattering parameters at the frequency of oscillation.
2. TWO PORT-OSCILLATOR DESIGN

Current approach to oscillator design using active two-port device involves the reduction to a one port
configuration by embedding the active device in a suitable circuit. The circuit topology is usually chosen
to resonate one port so that stability factor, K, is less than unity; the other port circuit is then designed to
match the resulting output impedance with negative real part. the two-port network is shown in Fig. 4-1.
Input S11 S12 Output

matching matching
network network
M1 M2
S21 S22
T in out L
ZT Zin Zout ZL
Fig. 4-1 Two port oscillator model
For the oscillation to occur at a frequency f0 , the following conditions need to be satisfied:
Rout V , f0 RL f0 (4-1) X out V , f0 X L f0 0 (4-2)
Where Rout is negative. The first equation ensures that out 1 , and the second equation determines
the frequency. As long as Rout V , f 0 at a certain voltage V is greater than RL , the network has the
potential for oscillation. In the other hand, when the power supply voltages are turned on, the oscillations
start to build from the noise level. The output power amplitude continues to grow until it is limited by the
saturation effects of the device. The negative resistance Rout is a function of voltage, and as the
oscillation power is increased, the negative resistance value is reduced. If the negative resistance is
decreased to a value lower than the load resistance, oscillation will cease. This problem can be eliminated
by designing the amplitude of the negative resistance at V = 0 to be much larger than the load. For
example, a design factor of R out V , f 0 3 R L f 0 is used in practice to ensure that oscillation
does not stop as it approaches steady conditions.
2-1 CONDITIONS OF OSCILLATIONS
The conditions for oscillation can also be expressed as:
K 1 (4-3)
T in 1 (4-4)
L out 1 (4-5)
Since L and T are less than unity, equations (4-4) and (4-5) imply that in 1 (input port is
oscillating ) and out 1 (output port is oscillating).
Question: prove that if the terminating port ( at M1) is oscillating, then the output port is simultaneously
oscillating.
The design procedure for the two port oscillator design is given in the following flow chart:
Start Calculate K K <1 Resonate T
Change the Calculate S22

configuration
of the device or Change T
add feedback
S22 >1
Calculate L
Fig. 4-2 Oscillator design flowchart End
The steps used for designing a transistor oscillator are qualitatively repeated below as:
Select a potentially unstable transistor at the frequency of oscillation. If the active device is not
potentially unstable, use feed-back element to make the device unstable ( in the following section, one
method is used in the design of a series-feed-back network in a transistor negative resistance
oscillator), or change the configuration.
Design the terminating network, ZT or T, to make out > 1 by selecting ZT or T in the unstable zone
of the input stability circle.
From ZT and the transistor small-signal S-parameters, calculate out and confirm that out > 1 as:
S12 S 21 T
out S 22 , out 1
1 S11 T
Choose the load according to the oscillation conditions as follows:
1
X out V , f0 X L f0 0 and R L f 0 Rout V , f 0
3
The value chosen for load impedance ZL usually produces a working oscillator. The measured oscillation
frequency will be shifted from the design value since X out f0 used in determining f0 , is assumed
independent of the amplitude V.
Design the load-matching network to transform a 50 to ZL.
Example # 1 the S-parameters of a GaAs MESFET at 8 GHz are given by:

S11 0.980 160 S21 0.6745 161
S12 0.390 54 S 22 0.465 120
Design an 8 GHz oscillator using this device.
Solution :
Check the stability at 8 GHz. Using equations (2-4*) and (2-9) we find K = 0.529 < 1 the device is
potentially unstable.
Chose ZT or T to make out > 1 by drawing a
stability circle in the input (terminating) plane.
The input stability circle has a center and a
radius given by : CS = 1.35 -156 and Terminating
RS = 0.521. The circle is plotted in Fig. 4-3. If stability
ZT is chosen at A shown in Fig. 4-3 then circle
ZT = -j7.5 .
A
ZT can be obtained using an open circuit stub of
Z0 = 50 and l = 0.226 (ZT = -j7.5 = j Z0 cot
(2 l/ ).
Unstable
With ZT connected, the output termination is region
obtained as :
S12 S 21 T Fig 4-3 Terminating port stability circle.
out S 22 12.8 - 16.6 , out 1
1 S22 T
Which correspond to Zout = -58.0 + j 2.61 .
1
Design RL Rout 19.3 and X L X out j 2.61 .
3
3. SERIES FEED-BACK NETWORK DESIGN

In a negative resistance oscillator, the parasitic capacitances of the transistor provide some or all of the
feedback needed for oscillation. However, a properly designed series
feedback network can significantly increase the negative resistance
presented by the two-port network. (e.g. in the design of oscillator using
BJT in common base configuration, it is fairly common to use an transistor
[ Za ]
inductor from the base to ground to increase the instability region in the
Smith chart). This section discusses a method that can be used to design
the series-feedback network, shown in Fig. 4-4. The purpose of the
Feedback
series feedback network is to produce values of S11 and S22 greater network
than one for the two-port network. The values of S11 and S22, as seen in [ Zf ]
Fig. 4-4 are obtained in a Z0 system, where Z0 (typically 50 ) is the
normalizing impedance.
Fig. 4-4 two-port network using
3-1. PRESENTATION OF THE METHOD series feedback configuration
This method uses impedance matrices of the transistor and the series-
feedback network, denoted by [ Za ] and [ Zf ], respectively, to calculate
the overall S-parameters of the two-port network in Fig. 4-4.
z11,a z12 ,a zf zf
Let Za Z0 and Z f Z0
z21,a z22 ,a zf zf
Where zf = r + jx is the impedance of the series feedback network (i.e., zf = Zf / Z0 ), and z11,a, z12,a, z21,a
and z22,a are the transistors normalized impedance parameters (i.e., z11,a = Z11,a / Z0 , etc. ). Then, the
impedance matrix of the two-port, denoted by [ Z ], is given as
z11,a zf z12 ,a zf
Z Za Zf Z0 (4-6)
z21,a zf z22 ,a zf
Now, converting the impedance parameters of equation (4-6) to the corresponding S-parameters gives
S11 S12
S
S 21 S22
such that
zf A B
S11 (4-7)
zf E D
zf A F
S 22 (4-8)
zf E D
2 2
S12 zf z12 ,a S 21 zf z21,a
G G
where
A z11,a z 22 ,z z12 ,a z 21,a B z11,a z 22 ,a z12 ,a z 21,a z11,a z 22 ,a 1
D z11,a z22 ,a z12 ,a z21,a z11,a z 22 ,a 1 E z11,a z22 , z z12 ,a z21,a 2
F z11,a z 22 ,a z12 ,a z 21,a z11,a z 22 ,a 1 G zf E D.
Equations (4-7) and (4-8) describe a mapping between the normalized impedance zf and S11 and S22
reflection coefficients planes. Letting
1 f
zf
1 f
we can express equations (4-7) and (4-8) in the form
aS11 b
f (4-9)
cS11 d
aS22 b
and f (4-10)
cS22 d
where a = E + D, b = -( A + B ), c = D E, d = A B, b = - ( A + F ) and d = A F.
The mapping of the f 1 circle (i.e., the r = 0 circle ) onto the S11 and S22 planes provides
information about the feedback impedances that will increase the instability of the two-port.
Equation (4-9) and (4-10) are bilinear transformations. Hence, the f 1 circle maps onto circles in
the S11 and S22 planes with center ( Ci ) and radius (Ri ) (i = 1, 2 ) given by the following
In the S11 plane:
AD* BE*
C1 (4-11)
2 E* D
AD BE
R1 (4-12)
2 E* D
In the S22 plane:
AD* FE*
C2 (4-13)
2 E* D
AD FE
R2 (4-14)
2 E* D
A typical mapping of the f 1 circle onto the S11 can be examined in Fig. 4-5a. in this figure, the
maximum value of S11 , denoted by S11(max) , is shown as the point P1 given by
S11 max C1 R1 C1 (4-15)
The impedance of the feedback network at the maximum value of S11 is purely imaginary and is
denoted by zf = jx1(max). it can be calculated using equation (4-7), namely,
B S11 max D
zf jx1 max (4-16)
S11 max E A
Hence the reactance x1(max) is simply the imaginary part of equation (4-16). Furthermore, to properly
orient the mapping, it follows from equation (4-7) that the point zf = maps onto S11 = A / E and the point
zf =0 maps onto S11 = B / D (shown in Fig. 4-5a as points P2 and P3, respectively).
Similarly, S22(max) , is given by
S 22 max C2 R2 C2 (4-17
F S 22 max D
and zf jx2 max (4-18)
S 22 max E A
Again, the reactance x2(max) is simply the imaginary part of equation (4-18). Moreover, the zf = maps
onto S22 = A / E and zf =0 maps onto S22 = F / D.
P1
R1
Mapping of f =1
zf j1.710
At P1
C1 S11 S11, max 3.265 62.69
zf
At P2 A
S11 0.56 14.77
B
P3 zf 0
At P3 B
P2 S11 0.386 142
D
S11 plane (a)
zf j1.491
At P1
S 22 S 22 , max 2.083 84.02
S22 plane
P2 zf
P3 At P2 A
S 22 0.56 14.77
E
C2 zf 0
R2 At P3 F
S 22 1.11 28.5
D
Mapping of f =1
P1
(b)
Fig 4-5 (a) Mapping of f = 1circle onto S11 plane foe example #2
(b) Mapping of f = 1circle onto S22 plane for example #2
Design procedure: the implementation of the method is as follows:

1. Convert the S-parameters of the transistor to the z-parameters and calculate A, B, D, E, F, and G;
2. Use equations (4-11) to (4-14) to calculate C1, R1, C2, and R2;
3. Use equations (4-15) to (4-18) to calculate S11(max), S22(max), x1(max), and x2(max);
4. Plot the mapping of the f plane onto the S11 and S22 planes;
5. Select the appropriate zf value.
Example # 2: Consider a BJT whose S-parameters are:
S 11, a 0.386 142 S 21, a 1.380 45.4
S 12 , a 0.147 81.3 S 22 , a 1.110 28.5
Solution :
The associated z-parameters are
z 11, a 0.877 7.08 z 21, a 4.876 136.05
z 12 , a 0.519 9.36 z 22 , a 4.973 112.37
Then, from equations (4-11) to (4-18), we obtain
C1 1.646 62.69 C 2 1.068 84.02
R1 1.619 R 2 1.015
S 11 max 3.265 62.69 S 22 max 2.083 84.02
x1 max 1.710 x 2 max 1.490
These mappings onto the S11 and S22 planes are shown in Fig. 4.5. furthermore, it can be seen that using
zf jx1 max 1.710 , yields S 11 S 11 max 3.265 62.69 and from equation (4-8) it follows
that S 22 1.882 108.73 .
Remark: For this example, Fig. 4-5 shows that inductive feedback increases the values of S11 and S22 ,
while capacitive feedback makes the values of S11 and S22 to be less than one. As expected from the
bilinear transformation, the mapped Smith chart is distorted. Also observed that S11 and S22 are equivalent
when the feedback network is an open circuit (i.e., when z f , S 11 S 22 A E 0.56 14.77 ).
4. OPTIMUM OSCILLATOR DESIGN

I 1A I 2A
Since the oscillator is often working at maximum power,
+ Active +
the small signal parameters may not be accurate for a network
V1A V2A
precise design. For this reason, designers may use large - -
A
signal parameter set for power amplifier and oscillator
designs. Usually, the most significant effect under large-
signal drive is a reduction in S21 and changes in S22. Passive
+ + p
An oscillator consists of an active device and a passive network V2P I 2
V1P
load, which may be viewed as the embedding circuit for - P -
the active device. This is shown in Fig. 4-6. Using the Y
and Z parameters, the embedding conditions predict the Fig. 4-6 Equivalent circuit for transistor oscillator
maximum output power from the oscillator.
4-1 OSCILLATION CONDITIONS

the two simplest topologies of the passive network are the and T types shown in Fig. 4-7.
Y3 Z1 Z2
Y1 Y2 Z3
T
Fig. 4-7 Two special cases of the embedding network
The conditions for the equilibrium oscillation are:

For the network:
I 1A I 1p 0 (4-19) I 2A I 2p 0 (4-20)
For the T network:
V1A V1p 0 (4-21) V2A V2p 0 (4-22)

Where the supper scripts A and p refer to active and passive ports respectively.
4-2 DESIGN PROCEDURE

For unique determination of the embedding circuit, the requirement for obtaining the highest output
power is assumed. A voltage gain Hv (in case of the network) and a current gain Hi (in case of the T
network) exist at which the power delivered to the load is the highest. These gains are given as:
* *
Y21 Y12 Z 21 Z 12
Hv (4-23) Hi (4-24)
2 Re Y22 2 Re Z 22
Where Yij and Zij are the Y and the Z parameters of the active device (i, j = 1, 2).
To change the active state to oscillation state, with the whole embedding circuit elements determined
simultaneously, six different kinds of the embedding circuits can be considered as described in Fig. 4-8.
Each configuration has a positive feedback element.
X1 X3
X1 X2 X3 X1
X2 X3 X2
RL RL
RL
(1) (2) (3)
B3 B3 B2
B2 B1 B2 GL B1 B3
GL B1 GL
(4) (5) (6)

Fig. 4-8 Oscillator circuit configurations
The ground node is usually set at the load point. The elements of the six circuits are calculated either
from Z or Y parameters. If the S-parameters of an active device are available, the Z or Y parameters can
be obtained by conversion process from S to either Z or Y.
Remark: The characteristics of the embedding circuit can be divided into two categories, those forming
terminating impedances for both the input and the output ports and those providing feedback paths which
are required for oscillations using three terminal devices.
The basic equations for the values of the elements in the six oscillator circuits can be found in terms of
Z and Y parameters as follows:
Circuit #1: Circuit #2:

RL D1 Fr D3 Fi D 4 D1 Fr D3 Fi D4
RL 2
Fr 1 F
X1 D2 1 Fr D4 D3
Fi Fr
X1 D1 D3 D2 D4
D3 1 Fr Fi
X2 D4
Fi D1 D3
X2
Fr Fi
X3 D3 D4
Fi Fr
1 Fr D4 D1 D3 Fi D1
Fi
X3 2
1 F
Circuit #3: Where:
D1 Fr D 3 Fi D4 D1 Z 11 F Z 12
RL 2
F D2 m Z 11 F Z 12
D1 1 Fr D3 e Z 21 F Z 22
X1 D2
Fi
D4 m Z 21 F Z 22
2
D1 Fr F
Fi D3 Fr D4 Z 21 AZ 11
Fi F Fr jFi
X2 AZ 12 Z 22
2
F *
Y21 Y12
D1 A Ar jAi
X3 2 e Y22
Fi
Circuit #4: Circuit #5:
GL C1 Ar C 3 Ai C 4 C1 Ar C 3 Ai C 4
GL 2
Ar A
B1 C2 1 Ar C4 C3
Ai C1 Ar 1
B1 C2
C 3 Ar 1 Ai
B2 C4
Fi C1 Ar A
2
Ai C3 Ar C4
Ar Ai
B3 C3 C4
Ai B2 2
A
C1
B3
Ai
Circuit #6: Where:
C1 Ar C 3 Ai C 4 C1 e Y11 A Y12
GL 2
1 A
C2 m Y11 A Y12
Ar
B1 C1 C 3 C2 C4 C3 e Y21 A Y22
Ai
C1 C3 D4 m Y21 A Y22
B2
Ai
C1 1 Ar G L
X3
Ai
Example #3: Design an oscillator with the analytic approach for 500-um GaAs MESFET at VDS = 8V,
IDS = 50 mA (DXL 3501A) at 10 GHz. The S-parameters for this example are:
S 11 0.660 143 S 21 1.260 46

S 12 0.071 117 S 22 0.740 59
Solution:
A computer program is used to perform this example, where the S-parameters are converted to Z and Y
parameters with R0 = 50 . The results are given in Fig. 4-9 (all of the six circuits are given).
0.356 nH
2.55 nH
47.5 1.16 nH 0.292 pF 2.73 pF 2.28 nH 0.25 nH 0.13 nH

1.25 nH 28 .77
102
(1) (2) (3)
0.605 nH 5.77 nH
415
5.77 nH
3.01 nH
5.41 2.55 nH 379
0.683 pF 0.29 pF 0.33 nH
0.655 nH
(4) (5) (6)
Fig. 4-9 Solution of Example # 3
Remark: Sometimes although the embedding elements of the six configurations of the oscillator exist,
not all of them can be realized in practice, especially all of the parallel feedback configurations (circuits 4,
5, and 6); since there is no easy way to locate a capacitor between the gate (the base) and the drain (the
collector) without parasitic elements. However, in MMICs all the circuits can easily be realized
physically.
Appendix: conversion table: given the S-parameters of a transistor; Z and Y can be found as:
1 S 11 1 S 22 S 12 S 21 1 S 11 1 S 22 S 12 S 21
Z 11 Y11
z y
2 S 12 2 S 12
Z 12 Y12
z y
2 S 12 2 S 12
Z 21 Y21
z
y
1 S 11 1 S 22 S 12 S 21 1 S 11 1 S 22 S 12 S 21
Z 22 Y22
z
y
z 1 S 11 1 S 22 S 12 S 21 y 1 S 11 1 S 22 S 12 S 21
Z ij Z ij / R0 Yij Yij R0

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Chapter one Narrow Band Impedance Matching Networks

The matching networks may be one of the forms

2. Matching with Lumped Elements

2.1 L-section Lumped Reactive Matching Networks

2.1.1 Analytic Solutions

2.2 and Sections Lumped Reactive Matching Networks: (three-element matching)

jX1 jX3 jX2

Fig. 1-5 Three-element matching networks

ZG, ZL and Q are known

X2 X2 Here 4 possible circuits

Design flow chart of the reactive matching T-network

RG, RL and Q are Known

Design flow chart of the reactive matching -network

3. Transmission line sections matching networks

3.1 Quarter-Wavelength Transformer with Series Section

Fig. 1.8 Quarter-wavelength transformer for matching a complex load.

3.2 Quarter-Wavelength Transformer With Shunt Stub

Fig. 1.9 Matching with a quarter-wavelength section and a shunt stub.

Let = be the load admittance. The admittance of a shorted stub of

Fig. 1-10 One-section series impedance transformer.

3.3 Single Stub Matching

Fig. 1.11 Single-stub tuning circuits;

(a) shunt stub,

ii) Series Stubs

1) Locate normalized load impedance and draw VSWR circle.

3.4 Double Stub Matching

Fig.1.12 Double-stub tuning.

Y1 = GL + j(BL + B1), (1.23)

2. TWO-PORT NETWORK STABILITY

Fig. 1-1 Stability of two-port network

1 values for out = 1 (input stability circle)

Case S11 > 1:

3 SIMULTANEOUS CONJUGATE MATCH

Fig. 1-7 Generator delivering power to a load

For maximum power transfer one must satisfy both

Substituting in equation (1-14) yields:

The solution for equation (1-17) is found as:

B1 > 0 Normal condition B1 < 0

Approximation, for very small values of S12 and , C1 = S11

A similar results can be obtained for the load termination as:

An alternate expression for a1 is given as follows. Since in b1 , Equ. (1-24b) gives:

Generator b1 Two-port Load

S11 = 0 (a) S22 = 0

2. MICROWAVE AMPLIFIER CONFIGURATION:

3. MAXIMUM GAIN DESIGN

with C1 S11 S*22 ; C2 S 22 *

Output matching network

Fig 3-3 A 6 GHz maximum gain GaAs FET amplifier.

Fig 3-5 A 2 GHz GaAs FET amplifier.

4. USE OF UNILATERAL TRANSISTORS

in S11 and out S 22

5. CONSTANT GAIN CIRCLES FOR THE UNILATERAL CASE

define normalized gain factors gS and gL as:

Fig 3-6 Constant gain circles in S plane

6. LOW NOISE AMPLIFIER DESIGN

conductance element of 0.028 mhos, a quarter-wave transformer (l = /4) of characteristic impedance

Fig 3-7 A 6 GHz low noise GaAs FET amplifier.

Fig 3-9 A 2 GHz low noise GaAs FET amplifier.

The available power gain as derived in chapter one is given by:

Where C1 S11 S*22 . Note Ga is independent of L by virtue of its own definition.

circle have centers CF and Ca and radii RF and Ra as S

2. TWO PORT-OSCILLATOR DESIGN

Input S11 S12 Output

Start Calculate K K <1 Resonate T

with C1 S11 S22 ; C2 S 22