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10. (b) 25. (b) 40. (d) 55. (d) 70. (c)
11. (c) 26. (d) 41. (d) 56. (b) 71. (a)
12. (c) 27. (c) 42. (c) 57. (c) 72. (a)
13. (d) 28. (b) 43. (d) 58. (d) 73. (d)
14. (c) 29. (c) 44. (d) 59. (b) 74. (a)
15. (c) 30. (a) 45. (c) 60. (b) 75. (b)
12 ESE 2018 Prelims Exam Classroom Test Series
1. (c)
t
Energy, E = v (t ) i(t ) dt
dq
But, i(t) = or i(t) dt = dq
dt
3
t 3 2q 2 3q 3
E = v (t ) dq = (1 + 2q + 3q ) dq = q + + 2
2 3 1
1
= [(3 1) + (32 12) + (33 13)]
= 2 + (9 1) + (27 1) = 2 + 8 + 26 = 36 J
2. (c)
A A
Vs R Vs
B B
R
A A
Is Is
B B
3. (b)
The internal resistance will be in series with the load. Rs I
Circuit current will be +
5
21 Voc 21 V VT RL 2
I = =3A
7
Terminal voltage = I RL = 3 2 = 6 V
4. (d)
15
By inspection, i = = 3.75 A
4
and the current through 3 resistor is,
15
i = =5A
3
is 1
i i
15 V + 4 i 3
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E & T Engineering | Test 1 13
5. (b)
The given circuit can be reduced as
R1 = 2
+ v
6v + Req = [(5 + 1) 4 2]
+ 20 V
= 1.09
6. (d)
Given, I = 25 mA
Isc = 50 mA
V = 0.5 V
Isc Req V R
Req
I = R + R Isc
eq
Req
25 = 50
R + Req
50
or 1 = R
25 R eq
or Req = R
V = IR
0.5 V = 25 mA R
0.5
or R = k = 20
25
Req = 20
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14 ESE 2018 Prelims Exam Classroom Test Series
7. (d)
Let 1 = primary coil flux
12 = mutual flux
where 12 = K 1 = 0.5 1 = 0.7
0.7 7
1 = = = 1.4 Wb
0.5 5
The primary coil inductance,
7
250
L1 =
N 1
= 5 = 25 = 5 H
I1 70 5
8. (c)
A
3
1A 2 6 4A
+ 6V
2 2
4V
+ 2V
B
The given circuit can be reduced as,
A
A
A
2A 3 6 3A 1
1A 2 4A 1 A
3V 2
1 2V
2A 2 2 1A B
1 1A 1V
B
B B
A
1A 2
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E & T Engineering | Test 1 15
9. (c)
Redrawing the circuit, we get,
R
R
R R R/2
R R
A B R/2 R R/2
R/2 R R/2
R R R
A B
A B
R 3
Req = 3 R = R
2
5
3
For R = 20 , Req = (20) = 12
5
10. (b)
1
0 =
LeqC
Here, Leq = L1 + L2 2M = 1 + 5 4 = 2 H
C = 2F
1 1
0 = = = 0.5 rad/sec
2 2 2
11. (c)
Under resonance, XL = XC
The current flowing through the inductor is equal to the current flowing through the capacitor.
V V
I = =
X L 2 fL
1
where, f =
2 LC
V 2 LC
I = =V C
2 L L
12. (c)
According to the question,
Vs = I (Rs + RL )
Vs = 4(Rs + 5) ...(i)
Vs = 2(Rs + 20) ...(ii)
By solving equation (i) and (ii), we get,
Vs = 60 V and Rs = 10
For maximum power transfer,
Rs = RL
Vs2 602
Pmax = = = 90 W
4RL 4 10
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16 ESE 2018 Prelims Exam Classroom Test Series
13. (d)
Resonant frequency
Bandwidth =
Quality factor
C
For parallel RLC circuit, Q = R
L
1
and 0 =
LC
1 L
BW =
R LC C
1
BW = BW is independent of L
RC
14. (c)
The impedance matrix is given by,
V1 j L1 j M I1
V = j M j L I
2 2 2
Here L1 = 3 H, L2 = 8 H, and M = 2 H
From figure (B),
Leq = L1 + L2 + 2M = 3 + 8 + 4 = 15 H
15. (c)
Condition Condition
Parameters for for
symmetrical reciprocal
Z-parameter Z11 = Z22 Z12 = Z21
16. (a)
Let, v be the reference vector, it is clearly observed from the question that, i lags v by 30.
Vm 18
Also, = =9
Im 2
Z = R 2 + (L)2
9 2 = R 2 + (L ) 2 ...(i)
L 1
= tan30 =
R 3
R = 3 (L) ...(ii)
( )
2
From equation (i) and (ii), 92 = 3 L + (L)2
2(L) = 9
9 9
L = = = 0.5 H = 9 rad/sec
2 29
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E & T Engineering | Test 1 17
17. (c)
V 2 100 100
R = = = 1k
P 10
V 100
IR = = = 0.1 A
R 1000
I = IR2 + IC2
0.3 = (0.1)2 + ( IC )2
1 1
or, IC = (0.3)2 (0.1)2 = 32 12 = 2 2
10 10
IC = 0.2828
IC 0.2828 0.2828
C = = = 9 F
2 f V 2 50 100 314 100
18. (b)
By applying KCL at node A, VA
12 VA 24 VA I
+3+ = 0 2
4 2 4 3A
12 VA + 12 + 48 2VA = 0
12 V +
24 V
3VA = 72
+
VA = 24 V
12 VA 12
I = = = 3 A
4 4
19. (a)
The absence of any independent source leads to VTh = 0 V
Now, to calculate RTh a dc source Vdc is applied across the terminal A and B.
2i
1 2 A Idc
+
V 4 2 +
Vdc
i
V V
Here, Vdc V = 2i = 2 =
4 2
3
or Vdc = V
2
By applying KCL at node (2), we get,
Vdc V
+ = Idc
2 4
Vdc 2/3 Vdc
or Idc = +
2 4
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18 ESE 2018 Prelims Exam Classroom Test Series
2
Idc = Vdc
3
Vdc 3
or =
Idc 2
20. (d)
Given graph is a complete graph
the maximum number of possible trees = nn 2
where n = total number of nodes
n=4
Total number of trees = 4(4 2)
= 42 = 16
21. (c)
The connected graph is
1
a
5
c d
3
2
6
b
4
22. (c)
The internal impedance of the circuit is
Zin = 3 + j4 8 j = (3 4 j )
The open circuit voltage across RL
Voc = 500 Volts
As per the maximum power transfer theorem, for maximum power transfer,
or, RL = (3 4 j ) = 9 + 16 = 5
50 0 50 0
I = =
(3 j 4 + 5) 8 j4
500 500
I = = A
64 + 16 4 5
2
2 50 0
Pmax = I RL = 5
4 5
50 50 2500
= 5 = = 156.25 W
16 5 16
23. (b)
Considering the second node equation
i2 i4 + i5 i6 = 0
2 4 + 4 i6 = 0
i6 = 2 A
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E & T Engineering | Test 1 19
24. (a)
When the switch was opened
2 F 2 F
Ceq
2 F 2 F
Ceq = 2
2 2 8
= = 2 F
+ 2 4
2
When the switch get closed
A
2 F 2 F
Ceq
2 F 2 F
4 F 4 F 16
=
C eq = = 2 F
8 F 8
25. (b)
The time constant for an RC circuit is
= Ceq Req
2 4 8 4
Here, Req = (2 4 ) =
6
=
6
=
3
3 1 3
and Ceq = F= F
4 4
4 3
= = 1 sec
3 4
26. (d)
The number of links = Total number of independent loops
Bn+1 = 3
B8+1 = 3
B = 10
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20 ESE 2018 Prelims Exam Classroom Test Series
27. (c)
2 2
i(t)
+
4t v(t) 2t
e 1H e
28. (b)
By applying source transformation, we come to known that the circuit act as a parallel RLC circuit.
8 40 F 16 mH Is
C 40 1 8
Q = R =8 10 3 = 8 =
L 16 20 20
1 1 20
The damping factor, = = = = 1.25
2Q 8 16
2
20
> 1 Overdamped
29. (c)
The charging current equation for RL circuit is
i(t ) =
V
R
(
1 e t / u (t ) )
L
where, = = time constant
R
2
= = 0.1 sec
20
100
i = (1 e t / 0.1)u(t ) = 5(1 e 10 t )u (t ) A
20
di
= 50e 10 t u (t) A/s
dt
The rate of change of current at the instant just after closing the switch (t = 0+) is
di
(t = 0 + ) = 50 A/s
dt
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E & T Engineering | Test 1 21
30. (a)
Taking the circuit in Laplace domain, we get,
I(s)
2 2
s
1
+ s
s
1
I(s) = s
2
2 + +s
s
1 1
= 2
=
s + 2s + 2 (s + 1)2 + 1
By taking inverse Laplace transform,
t
i(t) = e sint u(t ) A
31. (b)
5I0
I1 2 I0 I2
+ +
V1 I1 I2 V2
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22 ESE 2018 Prelims Exam Classroom Test Series
32. (c)
V1
1 2
I1 +
V1
+
I1 1 2 V2
(1 + )I1
V1 1 V2
Using KVL,
V1 = I1 + I2
V2 = (1 j )I2 + I1
Finding transmission parameters, we get,
V1
A = =1
V2 I2 = 0
V1
B = = j
I2 V
2 =0
I1
C = = 1S
V2 I2 = 0
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E & T Engineering | Test 1 23
I1
D = = (1 j )
I2 V
2 =0
34. (c)
Elements should be also bilateral to satisfy the reciprocity.
37. (c)
di
v = L
dt
Thus, the potential drop across the inductor is proportional to the rate of change of the current.
38. (c)
(64)8 = 6 8 + 4 = (52)10
(64)10 + (52)10 = (12)10
thus X = 12
39. (d)
AND-NOT NAND (Universal gate)
NOTOR NOR (Universal gate)
40. (d)
The circuit can be redrawn as,
B
F
C
A
which can be redrawn as,
A+B
B B+C A +B+C
A+ B+C = A B C
C
A C+A
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24 ESE 2018 Prelims Exam Classroom Test Series
41. (d)
An n-bit ring counter can count only n-pulses whereas an n-bit ripple counter can count 2n pulses. In a ring
counter we do not require a decoder circuit because we can read the count by simply noting which flip-flop
is set.
42. (c)
(45)16 = 4 16 + 5 = (69)10
(45)10 (69)10 = (24)10
Now, (+24)10 = (011000)2
Thus, (24)10 = (101000)2
43. (d)
(110011)2 = (51)10
= (63)8 = (33)16 = (303)4
44. (d)
= AB (C + C )
= AB
45. (c)
CD
AB 00 01 11 10
00 1 0 1 0
01 1 0 1 1
11 1 0 0 0
10 1 0 0 0
46. (b)
MOD 78 = MOD(13) MOD (6)
47. (b)
f = w + w x + x yz
By solving,
f = w + x yz
So there is no need of Gate-2.
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E & T Engineering | Test 1 25
48. (c)
Positive logic Negative logic
A B C A B C A B C
0V 0V +5 V 0 0 1 1 1 0
0V +5 V 0V 0 1 0 1 0 1
+5 V 0V 0V 1 0 0 0 1 1
+5 V +5 V 0V 1 1 0 0 0 1
NOR NAND
49. (c)
F ( A,B,C) = m(0, 4, 6, 7)
BC
A 00 01 11 10
0 1 0 0 0
1 1 0 1 1
F ( A,B,C) = AB + BC
Thus logic circuit 2 and 3 can be used to implement this function.
50. (c)
The circuit can be redrawn as,
C B+C A(B + C)
B
A F
BC AB C
51. (a)
F = x1 y1(x0 y0 ) + x1 y1(x0y0 ) + x1 y1(x0 y0 ) + x1 y1(x0 y0 )
= x0 y0 (x1 y1 + x1 y1) + (x0 y0 )(x1 y1 + x1 y1)
= x0y 0 (x1 e y1) + x0y 0 (x1 y1)
= x0y 0 (x1 y1) + (x0y 0 )(x1 y1)
= x1 y 1 x0 y 0
52. (b)
The Master-Slave configuration is used to eliminate Race-around condition.
53. (d)
A MUX is used as a data selector. It can also be used in data acquisition devices where the input data is
to be received from many sources. It is also used as parallel to serial converter.
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26 ESE 2018 Prelims Exam Classroom Test Series
54. (b)
Given the initial state to be zero, thus the state sequence table can be given as
Qn J = (1) K = (Qn ) Qn +1
0 1 1 1
1 1 0 1
1 1 0 1
M M M M
55. (d)
T Qn Qn + 1
0 0 0
0 1 1
1 0 1
1 1 0
Qn + 1 = TQn + T Qn
57. (c)
Change in input causes the change in the state of the Moore machine. As the state changes, its corresponding
output will also change.
59. (b)
For J = 0 and K = 0, the output will remain 1 as the flip-flop will be in memory state.
For J = 1 and K = 0, the flip-flop will be in set position, thus the output will be equal to 1.
So, the possible input combination is, J = X and K = 0
60. (b)
Y = A + AB + ABC = A + AB
= A + B = AB
61. (b)
The state diagram of sequence detector which detects 0011 as a sequence can be drawn as
1/0 0/0
0/0 0/0 1/0
A B C D
0/0
1/1
64. (c)
(
x y xy = x (y x y ) = x y ( xy ) + y ( xy ) )
= x ( y (x + y ) + y (xy )) = x x y
= x ( x y ) + x( x + y ) = x + xy + x y
= x + xy = x + y
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E & T Engineering | Test 1 27
65. (c)
The given circuit can work as a 1-bit Johnson counter with MOD = 2n = 2(1) = 2.
fclock 50 103
So, fout = = = 25 kHz
2 2
67. (b)
F = (A + C )(B + C )(A + B )
= (A + C )(A + B ) (By consensus theorem)
68. (a)
16 5 16 address location with 5 bits in each location
69. (b)
CD
AB 00 01 11 10
00 1 1
01 1
11 1
10 1
Y = AB + CD
70. (c)
1st and 2nd are not necessary conditions to realize a logic function, they are only sufficient.
71. (a)
X1 = Y1
X2 = Y1 Y2
72. (a)
VFS
100 < (0.4) VFS
2n 1
1
n < 0.004
2 1
2n 1 > 250
n (minimum) = 8
73. (d)
A universal gate is a gate which can implement all Boolean functions without need to use any other type of
gate. The NAND and NOR gates are universal gates and XOR is not a universal gate because it is not
possible to implement all Boolean functions using XOR gates only.
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