Z.

Navabi
Digital System Test and Testable Design
Using HDL Models and Architectures

▶ Describes test methods in Verilog and PLI, which makes the methods
more understandable and the gates possible to simulate
▶ Simulations of gate models allows fault simulation and test
generation, while Verilog test benches inject faults, evaluate fault
coverage and apply new test patterns
▶ Describes DFT, compression, decompression, and BIST techniques
in Verilog, which makes the hardware of the architectures easier to
understand and allows simulation and evaluation of the testability
methods

Digital System Test and Testable Design: Using HDL Models and Architectures by:
Zainalabedin Navabi This book is about digital system test and testable design. The
concepts of testing and testability are treated together with digital design practices
2011, XVII, 435 p.
and methodologies. The book uses Verilog models and testbenches for implementing
and explaining fault simulation and test generation algorithms. Extensive use of Verilog
and Verilog PLI for test applications is what distinguishes this book from other test and
Printed book
testability books. Verilog eliminates ambiguities in test algorithms and BIST and DFT
Hardcover hardware architectures, and it clearly describes the architecture of the testability hardware
valid through November 5, 2017 and its test sessions. Describing many of the on-chip decompression algorithms in Verilog
▶ 69,95 € | £62.99 | $99.00 helps to evaluate these algorithms in terms of hardware overhead and timing, and
▶ *74,85 € (D) | 76,95 € (A) | CHF 100.50 thus feasibility of using them for System-on-Chip designs. Extensive use of testbenches
and testbench development techniques is another unique feature of this book. Using
PLI in developing testbenches and virtual testers provides a powerful programming
eBook
tool, interfaced with hardware described in Verilog. This mixed hardware / software
Available from your library or environment facilitates description of complex test programs and test strategies.
▶ springer.com/shop •Combines design and test •Describes test methods in Verilog and PLI, which makes the
methods more understandable and the gates possible to simulate •Simulation of gate
models allows fault simulation and test generation, while Verilog testbenches inject
MyCopy
faults, evaluate fault coverage and apply new test patterns •Describes DFT, compression,
Printed eBook for just decompression, and BIST techniques in Verilog, which makes the hardware of the
▶ € | $ 24.99 architectures easier to understand and allows simulation and evaluation of the testability
▶ springer.com/mycopy methods •Virtual testers (Verilog testbenches) play the role of ATEs for driving scan
tests and examining the circuit under test •Verilog descriptions of scan designs and BIST
architectures are available that can be used in actual designs •PLI test utilities developed
in-text are available for download •Introductory Video for Verilog basics, software
developed in-text, and PLI basics available for download •Powerpoint slides available for
each chapter

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