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5 4 3 2 1 01 Chocolate DIS (14" / 15" / 17") PCB 6L
5
4
3
2
1
01
Chocolate
DIS (14" / 15" / 17")
PCB 6L STACK UP
Intel SKYLAKE ULT Platform Block Diagram
D
LAYER 1 : TOP
LAYER 2 : SGND
LAYER 3 : IN1(High)
LAYER 4 : IN2(Low)
LAYER 5 : SVCC
LAYER 6 : BOT
D
VRAM DDR3L x 4 (900 MHz)
AMD MESO XT
DDR3L SODIMM1
256
x 16 x 4, 64 bit
SKYLAKE U
DDR3L
Maxima 8GBs
PCI-E Gen3
x 4 Lane
Max 4GBs
Processor
PAGE 17
Power : 25 (Watt)
Package : S3
Size : 23 x 23 (mm)
PAGE 18 19
DDR3L SODIMM2
DDR3L
Maxima 8GBs
PAGE 19~24
PAGE 18
Processor : Daul Core
Power : 15 (Watt)
Package : BGA1356
Size : 40 X 24 (mm)
RTD2136
LVDS (2CH)
Package : QFN-32
PAGE 22
PAGE 27/27
SATA0 - 1st HDD
SATA0 6GB/s
Package : 9.5 (mm)
eDP
C
C
Power :
PAGE 34
eDP X 2
PAGE 27/27
SATA ODD
Package : 12.7 (mm)
SATA1 3GB/s
HDMI Conn
Power :
PAGE 34
PAGE 28
DP Port 1
USB3.0 Port x 1
USB3.0 Interface
USB 3.0 Port 1,2,3(USB 2.0 Port 0,1,5)
Azalia
Port 1
PAGE 33
HP
USB2.0 Interface
PAGE 2~16
System BIOS
SPI Interface
SPI ROM
PAGE 10
Camera
Touch Screen
TPM
PAGE 32
Port2
Port7
SLB9665TT2.0 FW 5
PAGE 28
Elan EKTH3915 for 14",15"
Elan EKTH3918 for 17"
LPC Interface
PCIE Gen 1 x 1 Lane
PAGE 32
B
B
Embedded Controller
Audio Codec
Card Reader
LAN Controller
G-Sensor
H.P
iTE 8987
ALC3241
RTS5237S-GRT
RTL8111HSH(Giga)
M2 Card
Intel Rambo Peak
SM BUS
HP3DC2TR
PAGE32
RTL8107EH(10/100)
Power :
Power :
Power :
WLAN / BT Combo
Keyboard
Package : LQPF128
Package : MQFN
Package : LQPF48
Port6
PAGE 31
Power :
Size : 14 x 14 (mm)
Size : 6 x 6 (mm)
Size : 7 x 7 (mm)
Package : OFN32
Touch Pad
PAGE 35
PAGE 29
DB
DB
PAGE 34
PAGE 31
FAN
Speaker
PAGE 31
PAGE 29
A
A
Head Phone AMP
HPA022642RTJR
Combo Jack
PAGE 29
PROJECT : X1A
PROJECT : X1A
PROJECT : X1A
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Digital MIC
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
Custom
Custom
Custom
1A
1A
1A
PAGE 28
NB5
NB5
NB5
Block Diagram
Block Diagram
Block Diagram
Date:
Date:
Date:
Wednesday, May 13, 2015
Wednesday, May 13, 2015
Wednesday, May 13, 2015
Sheet
Sheet
Sheet
1
1
1
of
of
of
49
49
49
5
4
3
2
1
5 4 3 2 1 ? Need apply PN SKL_ULT U17A 02 IN_D2# E55 C47
5
4
3
2
1
?
Need apply PN
SKL_ULT
U17A
02
IN_D2#
E55
C47
INT_EDP_TXN0
[28]
IN_D2#
DDI1_TXN[0]
EDP_TXN[0]
INT_EDP_TXN0
[27]
IN_D2
F55
C46
INT_EDP_TXP0
Reserve EDP_HPD opposites circuit!
+3V
[4,10,11,12,13,14,15,16,17,18,27,28,29,30,31,32,33,34,35,41,43]
[28]
IN_D2
DDI1_TXP[0]
EDP_TXP[0]
INT_EDP_TXP0
[27]
IN_D1#
E58
D46
INT_EDP_TXN1
+1.0V
[4,6,16,32,35,40]
[28]
IN_D1#
DDI1_TXN[1]
EDP_TXN[1]
INT_EDP_TXN1
[27]
IN_D1
F58
C45
INT_EDP_TXP1
+VCCSTPLL
[4,5,6,9,40,41]
[28]
IN_D1
INT_EDP_TXP1
[27]
HDMI
DDI1_TXP[1]
EDP_TXP[1]
IN_D0#
F53
A45
+VCCIO
[6,16,40]
[28]
IN_D0#
DDI1_TXN[2]
EDP_TXN[2]
IN_D0
G53
B45
[28]
IN_D0
DDI1_TXP[2]
EDP_TXP[2]
IN_CLK#
F56
A47
[28]
IN_CLK#
DDI1_TXN[3]
EDP_TXN[3]
IN_CLK
G56
B47
+3V
[28]
IN_CLK
DDI1_TXP[3]
EDP_TXP[3]
C50
E45
INT_EDP_AUXN
DDI2_TXN[0]
DDI
EDP_AUXN
INT_EDP_AUXN
[27]
D
D50
EDP
F45
INT_EDP_AUXP
D
DDI2_TXP[0]
EDP_AUXP
INT_EDP_AUXP
[27]
C52
R90
DDI2_TXN[1]
D52
B52
EDP_DISP_UTIL
*10K/F_4
DDI2_TXP[1]
EDP_DISP_UTIL
TP46
A50
DDI2_TXN[2]
B50
G50
DDI2_TXP[2]
DDI1_AUXN
D51
F50
ULT_EDP_HPD
DDI2_TXN[3]
DDI1_AUXP
C51
E48
Q
DDI2_TXP[3]
DDI2_AUXN
F48
DDI2_AUXP
G46
R100
DDPB_CTRLDATA/ GPP_E19
Display Port B Detected
DDI3_AUXN
DISPLAY SIDEBANDS
F46
100K_4
DDI3_AUXP
L13
[28]
SDVO_CLK
GPP_E18/DDPB_CTRLCLK
L12
L9
HDMI_HPD_CON
This signal has a weak internal pull-down.
[28]
SDVO_DATA
GPP_E19/DDPB_CTRLDATA
GPP_E13/DDPB_HPD0
HDMI_HPD_CON
[28]
L7
GPP_E14/DDPC_HPD1
0 = Port B is not detected.
N7
L6
GPP_E20/DDPC_CTRLCLK
GPP_E15/DDPD_HPD2
DDPC_CTRLDATA
N8
N9
1 = Port B is detected.
TP121
GPP_E21/DDPC_CTRLDATA
GPP_E16/DDPE_HPD3
L10
ULT_EDP_HPD
GPP_E17/EDP_HPD
ULT_EDP_HPD
[27,28]
N11
GPP_E22/DDPD_CTRLCLK
DDPD_CTRLDATA
N12
R12
PCH_LVDS_BLON
TP122
GPP_E23/DDPD_CTRLDATA
EDP_BKLTEN
PCH_LVDS_BLON
[28]
R11
PCH_DPST_PWM
EDP_BKLTCTL
PCH_DPST_PWM
[27]
R96
24.9/F_4
EDP_RCOMP
E52
U13
PCH_DISP_ON
+VCCIO
EDP_RCOMP
EDP_VDDEN
PCH_DISP_ON
[28]
*SKL_ULT
REV = 1
1 OF 20
eDP_COMPIO and ICOMPO signals should be shorted near
balls and routed with typical impedance <25 mohms
?
1125 change R96 connection from +1.0V to +VCCIO
1222 del for DDP not use
C
C
Need apply PN
SKL_ULT
?
U17D
Close to EC
CATERR#
D63
TP45
CATERR#
EC_PECI
A54
[35]
EC_PECI
PECI
499/F_4
PROCHOT#
C65
+VCCSTPLL
R381
[35,36,41]
H_PROCHOT#
JTAG
PROCHOT#
PM_THRMTRIP#
C63
[35]
PM_THRMTRIP#
THERMTRIP#
A65
PM_THRMTRIP#
R404
1K_4
SKTOCC#
B61
XDP_TCK0
PROC_TCK
XDP_TCK0
[16]
CPU MISC
D60
XDP_TDI_CPU
0114
C55
PROC_TDI
XDP_TDI_CPU
[16]
[16]
XDP_BPM0
BPM#[0]
A61
XDP_TDO_CPU
D55
PROC_TDO
XDP_TDO_CPU
[16]
[16]
XDP_BPM1
BPM#[1]
C60
XDP_TMS_CPU
+VCCSTPLL
Del TP39, Add R557 with 0ohm
mount for 3D camera
B54
PROC_TMS
XDP_TMS_CPU
[16]
BPM#[2]
B59
XDP_TRST#_CPU
C56
PROC_TRST#
XDP_TRST#_CPU
[2,16]
BPM#[3]
R405
*49.9/F_4
CATERR#
Processor pull-up (CPU)
TO BE REPLACED WITH 1K OHMS FOR SKL .
470 OHM IS FOR I/P
B56
JTAG_TCK_PCH
R557
*0_4
3D_FW_GPIO_R
A6
PCH_JTAG_TCK
JTAG_TCK_PCH
[16]
[33]
3D_FW_GPIO
GPP_E3/CPU_GP0
D59
JTAG_TDI_PCH
CPU_GP1
A7
PCH_JTAG_TDI
JTAG_TDI_PCH
[16]
TP38
GPP_E7/CPU_GP1
A56
JTAG_TDO_PCH
CPU_GP2
BA5
PCH_JTAG_TDO
JTAG_TDO_PCH
[16]
TP98
GPP_B3/CPU_GP2
C59
JTAG_TMS_PCH
CPU_GP3
AY5
PCH_JTAG_TMS
JTAG_TMS_PCH
[16]
TP97
GPP_B4/CPU_GP3
C61
XDP_TRST#_CPU
+1.0V
0423 change to shortpad
PCH_TRST#
XDP_TRST#_CPU
[2,16]
A59
JTAGX_PCH
R198
49.9/F_4
PROC_POPIRCOMP
AT16
JTAGX
JTAGX_PCH
[16]
PROC_POPIRCOMP
R74
*0_4/S
R389
*51_4
JTAGX_PCH
R191
49.9/F_4
PCH_OPI_RCOMP
AU16
PCH_OPIRCOMP
B
R107
49.9/F_4
EDRAM_OPIO_RCOMP
H66
B
OPCE_RCOMP
R390
51_4
JTAG_TMS_PCH
R101
49.9/F_4
EOPIO_RCOMP
H65
OPC_RCOMP
PDC
PLACE NEAR CPU
R407
JTAG_TDI_PCH
+1.0V
51_4
4 OF 20
R408
51_4
JTAG_TDO_PCH
*SKL_ULT
REV = 1
XDP_TMS_CPU
R392
*51_4
R391
51_4
JTAG_TCK_PCH
XDP_TDI_CPU
R388
*51_4
Close to Chipset
XDP_TDO_CPU
R378
*51_4
1231 un-install R378, R392
+1.0V
H_PROCHOT#
R44
1K_4
XDP_TCK0
R406
51_4
XDP_TRST#_CPU R384
51_4
A
A
PROJECT : X1A
PROJECT : X1A
PROJECT : X1A
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
Custom
Custom
Custom
02
02
02
-- SKYPAKE 1/20(eDP/DDI)
-- SKYPAKE 1/20(eDP/DDI)
-- SKYPAKE 1/20(eDP/DDI)
1A
1A
1A
NB5
NB5
NB5
Date:
Date:
Date:
Friday, May 22, 2015
Friday, May 22, 2015
Friday, May 22, 2015
Sheet
Sheet
Sheet
2
2
2
of
of
of
49
49
49
5
4
3
2
1
5 4 3 2 1 03 [17] M_A_DQSN[7:0] [17] M_A_DQSP[7:0] [18] M_B_DQSN[7:0] [18] M_B_DQSP[7:0] [17]
5
4
3
2
1
03
[17]
M_A_DQSN[7:0]
[17]
M_A_DQSP[7:0]
[18]
M_B_DQSN[7:0]
[18]
M_B_DQSP[7:0]
[17]
M_A_DQ[63:0]
[18]
M_B_DQ[63:0]
SkyLake ULT Processor (DDR3L)
+1.35VSUS
[6,17,18,38,40]
D
D
?
?
Need apply PN
SKL_ULT
Need apply PN
SKL_ULT
U17B
U17C
AU53
M_A_CLKN0
[17]
DDR0_CKN[0]
M_A_DQ0
AL71
AT53
M_A_DQ32
AY39
AN45
M_A_CLKP0
[17]
M_B_CLKN0
[18]
DDR0_DQ[0]
DDR0_CKP[0]
DDR0_DQ[32]/DDR1_DQ[0]
DDR1_CKN[0]
M_A_DQ1
AL68
AU55
M_A_DQ33
AW39
AN46
M_A_CLKN1
[17]
M_B_CLKN1
[18]
DDR0_DQ[1]
DDR0_CKN[1]
DDR0_DQ[33]/DDR1_DQ[1]
DDR1_CKN[1]
M_A_DQ2
AN68
AT55
M_A_DQ34
AY37
AP45
M_A_CLKP1
[17]
M_B_CLKP0
[18]
DDR0_DQ[2]
DDR0_CKP[1]
DDR0_DQ[34]/DDR1_DQ[2]
DDR1_CKP[0]
M_A_DQ3
AN69
M_A_DQ35
AW37
AP46
M_B_CLKP1
[18]
DDR0_DQ[3]
DDR0_DQ[35]/DDR1_DQ[3]
DDR1_CKP[1]
M_A_DQ4
AL70
BA56
M_A_DQ36
BB39
M_A_CKE0
[17]
DDR0_DQ[4]
DDR0_CKE[0]
DDR0_DQ[36]/DDR1_DQ[4]
M_A_DQ5
AL69
BB56
M_A_DQ37
BA39
AN56
M_A_CKE1
[17]
M_B_CKE0
[18]
DDR0_DQ[5]
DDR0_CKE[1]
DDR0_DQ[37]/DDR1_DQ[5]
DDR1_CKE[0]
M_A_DQ6
AN70
AW56
M_A_DQ38
BA37
AP55
M_B_CKE1
[18]
DDR0_DQ[6]
DDR0_CKE[2]
DDR0_DQ[38]/DDR1_DQ[6]
DDR1_CKE[1]
M_A_DQ7
AN71
AY56
M_A_DQ39
BB37
AN55
DDR0_DQ[7]
DDR0_CKE[3]
DDR0_DQ[39]/DDR1_DQ[7]
DDR1_CKE[2]
M_A_DQ8
AR70
M_A_DQ40
AY35
AP53
DDR0_DQ[8]
DDR0_DQ[40]/DDR1_DQ[8]
DDR1_CKE[3]
M_A_DQ9
AR68
AU45
M_A_DQ41
AW35
M_A_CS#0
[17]
DDR0_DQ[9]
DDR0_CS#[0]
DDR0_DQ[41]/DDR1_DQ[9]
M_A_DQ10
AU71
AU43
M_A_DQ42
AY33
BB42
M_A_CS#1
[17]
M_B_CS#0
[18]
DDR0_DQ[10]
DDR0_CS#[1]
DDR0_DQ[42]/DDR1_DQ[10]
DDR1_CS#[0]
M_A_DQ11
AU68
AT45
M_A_DQ43
AW33
AY42
M_A_DIM0_ODT0
[17]
M_B_CS#1
[18]
DDR0_DQ[11]
DDR0_ODT[0]
DDR0_DQ[43]/DDR1_DQ[11]
DDR1_CS#[1]
M_A_DQ12
AR71
AT43
M_A_DQ44
BB35
BA42
M_A_DIM0_ODT1
[17]
M_B_DIM0_ODT0
[18]
DDR0_DQ[12]
DDR0_ODT[1]
DDR0_DQ[44]/DDR1_DQ[12]
DDR1_ODT[0]
M_A_DQ13
AR69
M_A_DQ45
BA35
AW42
M_B_DIM0_ODT1
[18]
DDR0_DQ[13]
DDR0_DQ[45]/DDR1_DQ[13]
DDR1_ODT[1]
M_A_DQ14
AU70
BA51
M_A_A5
M_A_DQ46
BA33
M_A_A5
[17]
DDR0_DQ[14]
DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5]
DDR0_DQ[46]/DDR1_DQ[14]
M_A_DQ15
AU69
BB54
M_A_A9
M_A_DQ47
BB33
AY48
M_B_A5
M_A_A9
[17]
M_B_A5
[18]
DDR0_DQ[15]
DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9]
DDR0_DQ[47]/DDR1_DQ[15]
DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5]
M_B_DQ0
AF65
BA52
M_A_A6
M_B_DQ32
AU40
AP50
M_B_A9
M_A_A6
[17]
M_B_A9
[18]
DDR1_DQ[0]/DDR0_DQ[16]
DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6]
DDR1_DQ[32]/DDR1_DQ[16]
DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9]
M_B_DQ1
AF64
AY52
M_A_A8
M_B_DQ33
AT40
BA48
M_B_A6
M_A_A8
[17]
M_B_A6
[18]
DDR1_DQ[1]/DDR0_DQ[17]
DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8]
DDR1_DQ[33]/DDR1_DQ[17]
DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6]
M_B_DQ2
AK65
AW52
M_A_A7
M_B_DQ34
AT37
BB48
M_B_A8
M_A_A7
[17]
M_B_A8
[18]
DDR1_DQ[2]/DDR0_DQ[18]
DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]
DDR1_DQ[34]/DDR1_DQ[18]
DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8]
M_B_DQ3
AK64
AY55
AP48
C
M_A_BS#2
M_B_DQ35
AU37
M_B_A7
C
M_A_BS#2
[17]
M_B_A7
[18]
DDR1_DQ[3]/DDR0_DQ[19]
DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]
DDR1_DQ[35]/DDR1_DQ[19]
DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]
M_B_DQ4
AF66
AW54
M_A_A12
M_B_DQ36
AR40
AP52
M_A_A12
[17]
M_B_BS#2
[18]
DDR1_DQ[4]/DDR0_DQ[20]
DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12]
DDR1_DQ[36]/DDR1_DQ[20]
DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]
M_B_DQ5
AF67
BA54
M_A_A11
M_B_DQ37
AP40
AN50
M_B_A12
M_A_A11
[17]
M_B_A12
[18]
DDR1_DQ[5]/DDR0_DQ[21]
DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]
DDR1_DQ[37]/DDR1_DQ[21]
DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12]
M_B_DQ6
AK67
BA55
M_A_A15
M_B_DQ38
AP37
AN48
M_B_A11
M_A_A15
[17]
M_B_A11
[18]
DDR1_DQ[6]/DDR0_DQ[22]
DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT#
DDR1_DQ[38]/DDR1_DQ[22]
DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]
M_B_DQ7
AK66
AY54
M_A_A14
M_B_DQ39
AR37
AN53
M_B_A15
M_A_A14
[17]
M_B_A15
[18]
DDR1_DQ[7]/DDR0_DQ[23]
DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]
DDR1_DQ[39]/DDR1_DQ[23]
DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT#
M_B_DQ8
AF70
M_B_DQ40
AT33
AN52
M_B_A14
M_B_A14
[18]
DDR1_DQ[8]/DDR0_DQ[24]
DDR1_DQ[40]/DDR1_DQ[24]
DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]
M_B_DQ9
AF68
AU46
M_A_A13
M_B_DQ41
AU33
M_A_A13
[17]
DDR1_DQ[9]/DDR0_DQ[25]
DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]
DDR1_DQ[41]/DDR1_DQ[25]
M_B_DQ10
AH71
AU48
M_B_DQ42
AU30
BA43
M_B_A13
M_A_CAS#
[17]
M_B_A13
[18]
DDR1_DQ[10]/DDR0_DQ[26]
DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]
DDR1_DQ[42]/DDR1_DQ[26]
DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]
M_B_DQ11
AH68
AT46
M_B_DQ43
AT30
AY43
M_A_WE#
[17]
M_B_CAS#
[18]
DDR1_DQ[11]/DDR0_DQ[27]
DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]
DDR1_DQ[43]/DDR1_DQ[27]
DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]
M_B_DQ12
AF71
AU50
M_B_DQ44
AR33
AY44
M_A_RAS#
[17]
M_B_WE#
[18]
DDR1_DQ[12]/DDR0_DQ[28]
DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]
DDR1_DQ[44]/DDR1_DQ[28]
DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]
M_B_DQ13
AF69
AU52
M_B_DQ45
AP33
AW44
M_A_BS#0
[17]
M_B_RAS#
[18]
DDR1_DQ[13]/DDR0_DQ[29]
DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]
DDR1_DQ[45]/DDR1_DQ[29]
DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]
M_B_DQ14
AH70
AY51
M_A_A2
M_B_DQ46
AR30
BB44
M_A_A2
[17]
M_B_BS#0
[18]
DDR1_DQ[14]/DDR0_DQ[30]
DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]
DDR1_DQ[46]/DDR1_DQ[30]
DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]
M_B_DQ15
AH69
AT48
M_B_DQ47
AP30
AY47
M_B_A2
M_A_BS#1
[17]
M_B_A2
[18]
DDR1_DQ[15]/DDR0_DQ[31]
DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]
DDR1_DQ[47]/DDR1_DQ[31]
DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]
M_A_DQ16
BB65
AT50
M_A_A10
M_A_DQ48
AY31
BA44
M_A_A10
[17]
M_B_BS#1
[18]
DDR0_DQ[16]/DDR0_DQ[32]
DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]
DDR0_DQ[48]/DDR1_DQ[32]
DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1]
M_A_DQ17
AW65
BB50
M_A_A1
M_A_DQ49
AW31
AW46
M_B_A10
M_A_A1
[17]
M_B_A10
[18]
DDR0_DQ[17]/DDR0_DQ[33]
DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1]
DDR0_DQ[49]/DDR1_DQ[33]
DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]
M_A_DQ18
AW63
AY50
M_A_A0
M_A_DQ50
AY29
AY46
M_B_A1
M_A_A0
[17]
M_B_A1
[18]
DDR0_DQ[18]/DDR0_DQ[34]
DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]
DDR0_DQ[50]/DDR1_DQ[34]
DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1]
M_A_DQ19
AY63
BA50
M_A_A3
M_A_DQ51
AW29
BA46
M_B_A0
M_A_A3
[17]
M_B_A0
[18]
DDR0_DQ[19]/DDR0_DQ[35]
DDR0_MA[3]
DDR0_DQ[51]/DDR1_DQ[35]
DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]
M_A_DQ20
BA65
BB52
M_A_A4
M_A_DQ52
BB31
BB46
M_B_A3
M_A_A4
[17]
M_B_A3
[18]
DDR0_DQ[20]/DDR0_DQ[36]
DDR0_MA[4]
DDR0_DQ[52]/DDR1_DQ[36]
DDR1_MA[3]
M_A_DQ21
AY65
M_A_DQ53
BA31
BA47
M_B_A4
M_B_A4
[18]
DDR0_DQ[21]/DDR0_DQ[37]
DDR0_DQ[53]/DDR1_DQ[37]
DDR1_MA[4]
M_A_DQ22
BA63
AM70
M_A_DQSN0
M_A_DQ54
BA29
DDR0_DQ[22]/DDR0_DQ[38]
DDR0_DQSN[0]
DDR0_DQ[54]/DDR1_DQ[38]
M_A_DQ23
BB63
AM69
M_A_DQSP0
M_A_DQ55
BB29
BA38
M_A_DQSN4
DDR0_DQ[23]/DDR0_DQ[39]
DDR0_DQSP[0]
DDR0_DQ[55]/DDR1_DQ[39]
DDR0_DQSN[4]/DDR1_DQSN[0]
M_A_DQ24
BA61
AT69
M_A_DQSN1
M_A_DQ56
AY27
AY38
M_A_DQSP4
DDR0_DQ[24]/DDR0_DQ[40]
DDR0_DQSN[1]
DDR0_DQ[56]/DDR1_DQ[40]
DDR0_DQSP[4]/DDR1_DQSP[0]
M_A_DQ25
AW61
AT70
M_A_DQSP1
M_A_DQ57
AW27
AY34
M_A_DQSN5
DDR0_DQ[25]/DDR0_DQ[41]
DDR0_DQSP[1]
DDR0_DQ[57]/DDR1_DQ[41]
DDR0_DQSN[5]/DDR1_DQSN[1]
M_A_DQ26
BB59
AH66
M_B_DQSN0
M_A_DQ58
AY25
BA34
M_A_DQSP5
DDR0_DQ[26]/DDR0_DQ[42]
DDR1_DQSN[0]/DDR0_DQSN[2]
DDR0_DQ[58]/DDR1_DQ[42]
DDR0_DQSP[5]/DDR1_DQSP[1]
M_A_DQ27
AW59
AH65
M_B_DQSP0
M_A_DQ59
AW25
AT38
M_B_DQSN4
DDR0_DQ[27]/DDR0_DQ[43]
DDR1_DQSP[0]/DDR0_DQSP[2]
DDR0_DQ[59]/DDR1_DQ[43]
DDR1_DQSN[4]/DDR1_DQSN[2]
M_A_DQ28
BB61
AG69
M_B_DQSN1
M_A_DQ60
BB27
AR38
M_B_DQSP4
DDR0_DQ[28]/DDR0_DQ[44]
DDR1_DQSN[1]/DDR0_DQSN[3]
DDR0_DQ[60]/DDR1_DQ[44]
DDR1_DQSP[4]/DDR1_DQSP[2]
M_A_DQ29
AY61
AG70
M_B_DQSP1
M_A_DQ61
BA27
AT32
M_B_DQSN5
DDR0_DQ[29]/DDR0_DQ[45]
DDR1_DQSP[1]/DDR0_DQSP[3]
DDR0_DQ[61]/DDR1_DQ[45]
DDR1_DQSN[5]/DDR1_DQSN[3]
M_A_DQ30
BA59
BA64
M_A_DQSN2
M_A_DQ62
BA25
AR32
M_B_DQSP5
DDR0_DQ[30]/DDR0_DQ[46]
DDR0_DQSN[2]/DDR0_DQSN[4]
DDR0_DQ[62]/DDR1_DQ[46]
DDR1_DQSP[5]/DDR1_DQSP[3]
M_A_DQ31
AY59
AY64
M_A_DQSP2
M_A_DQ63
BB25
BA30
M_A_DQSN6
DDR0_DQ[31]/DDR0_DQ[47]
DDR0_DQSP[2]/DDR0_DQSP[4]
DDR0_DQ[63]/DDR1_DQ[47]
DDR0_DQSN[6]/DDR1_DQSN[4]
AT66
AY60
AU27
AY30
+1.35VSUS
M_B_DQ16
M_A_DQSN3
M_B_DQ48
M_A_DQSP6
B
DDR1_DQ[16]/DDR0_DQ[48]
DDR0_DQSN[3]/DDR0_DQSN[5]
DDR1_DQ[48]
DDR0_DQSP[6]/DDR1_DQSP[4]
B
M_B_DQ17
AU66
BA60
M_A_DQSP3
M_B_DQ49
AT27
AY26
M_A_DQSN7
DDR1_DQ[17]/DDR0_DQ[49]
DDR0_DQSP[3]/DDR0_DQSP[5]
DDR1_DQ[49]
DDR0_DQSN[7]/DDR1_DQSN[5]
M_B_DQ18
AP65
AR66
M_B_DQSN2
M_B_DQ50
AT25
BA26
M_A_DQSP7
DDR1_DQ[18]/DDR0_DQ[50]
DDR1_DQSN[2]/DDR0_DQSN[6]
DDR1_DQ[50]
DDR0_DQSP[7]/DDR1_DQSP[5]
M_B_DQ19
AN65
AR65
M_B_DQSP2
M_B_DQ51
AU25
AR25
M_B_DQSN6
DDR1_DQ[19]/DDR0_DQ[51]
DDR1_DQSP[2]/DDR0_DQSP[6]
DDR1_DQ[51]
DDR1_DQSN[6]
M_B_DQ20
AN66
AR61
M_B_DQSN3
M_B_DQ52
AP27
AR27
M_B_DQSP6
DDR1_DQ[20]/DDR0_DQ[52]
DDR1_DQSN[3]/DDR0_DQSN[7]
DDR1_DQ[52]
DDR1_DQSP[6]
M_B_DQ21
AP66
AR60
M_B_DQSP3
M_B_DQ53
AN27
AR22
M_B_DQSN7
R285
DDR1_DQ[21]/DDR0_DQ[53]
DDR1_DQSP[3]/DDR0_DQSP[7]
DDR1_DQ[53]
DDR1_DQSN[7]
M_B_DQ22
AT65
M_B_DQ54
AN25
AR21
M_B_DQSP7
470/F_4
DDR1_DQ[22]/DDR0_DQ[54]
DDR1_DQ[54]
DDR1_DQSP[7]
M_B_DQ23
AU65
AW50
M_B_DQ55
AP25
DDR1_DQ[23]/DDR0_DQ[55]
DDR0_ALERT#
DDR1_DQ[55]
M_B_DQ24
AT61
AT52
DDR0_PAR
M_B_DQ56
AT22
AN43
DDR1_DQ[24]/DDR0_DQ[56]
DDR0_PAR
TP12
DDR1_DQ[56]
DDR1_ALERT#
M_B_DQ25
AU61
M_B_DQ57
AU22
AP43
DDR1_PAR
DDR1_DQ[25]/DDR0_DQ[57]
DDR1_DQ[57]
DDR1_PAR
TP14
M_B_DQ26
AP60
AY67
SM_VREF
M_B_DQ58
AU21
AT13
SM_DRAMRST#
SM_VREF
[17]
DDR3_DRAMRST#
[17,18]
DDR1_DQ[26]/DDR0_DQ[58]
DDR_VREF_CA
DDR1_DQ[58]
DRAM_RESET#
M_B_DQ27
AN60
AY68
SMDDR_VREF_DQ0_M3
M_B_DQ59
AT21
AR18
SM_RCOMP_0
R159
121/F_4
SMDDR_VREF_DQ0_M3
[17]
DDR1_DQ[27]/DDR0_DQ[59]
DDR0_VREF_DQ
DDR1_DQ[59]
DDR_RCOMP[0]
M_B_DQ28
AN61
BA67
SMDDR_VREF_DQ1_M3
M_B_DQ60
AN22
AT18
SM_RCOMP_1
20mils width
R162
80.6/F_4
NIL-DDR CH -
SMDDR_VREF_DQ1_M3
[18]
DDR1_DQ[28]/DDR0_DQ[60]
DDR1_VREF_DQ
DDR1_DQ[60]
DDR_RCOMP[1]
M_B_DQ29
AP61
A
M_B_DQ61
AP22
AU18
SM_RCOMP_2
R163
100/F_4
DDR1_DQ[29]/DDR0_DQ[61]
DDR1_DQ[61]
DDR_RCOMP[2]
M_B_DQ30
AT60
AW67
DDR_VTT_CNTL
M_B_DQ62
AP21
DDR_VTT_CNTL
[4,18]
DDR1_DQ[30]/DDR0_DQ[62]
DDR_VTT_CNTL
DDR1_DQ[62]
M_B_DQ31
AU60
M_B_DQ63
AN21
NIL-DDR CH -
DDR1_DQ[31]/DDR0_DQ[63]
DDR1_DQ[63]
PDC
B
*SKL_ULT
REV = 1
2 OF 20
*SKL_ULT
REV = 1
3 OF 20
A
A
PROJECT : X1A
PROJECT : X1A
PROJECT : X1A
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
Custom
Custom
Custom
04
04
04
-- SKYPAKE 3/20(DDR3-A I/F)
-- SKYPAKE 3/20(DDR3-A I/F)
-- SKYPAKE 3/20(DDR3-A I/F)
1A
1A
1A
NB5
NB5
NB5
Date:
Date:
Date:
Wednesday, May 13, 2015
Wednesday, May 13, 2015
Wednesday, May 13, 2015
Sheet
Sheet
Sheet
3
3
3
of
of
of
49
49
49
5
4
3
2
1
5 4 3 2 1 04 [10,11,12,14,15,16,18] +3V_DEEP_SUS [2,10,11,12,13,14,15,16,17,18,27,28,29,30,31,32,33,34,35,41,43]
5
4
3
2
1
04
[10,11,12,14,15,16,18]
+3V_DEEP_SUS
[2,10,11,12,13,14,15,16,17,18,27,28,29,30,31,32,33,34,35,41,43]
+3V
[10,15,16,32,34,35,37,39,40,43,44,46]
+3VS5
[2,5,6,9,40,41]
+VCCSTPLL
[2,6,16,32,35,40]
+1.0V
?
Need apply PN
SKL_ULT
U17K
PCH Pull-high/low(CLG)
SYSTEM POWER MANAGEMENT
C
AT11
PCH_SLP_S0_N
GPP_B12/SLP_S0#
PCH_SLP_S0_N
[16,35]
AP15
GPD4/SLP_S3#
SUSB#
[16,35]
PLTRST#
AN10
BA16
GPP_B13/PLTRST#
GPD5/SLP_S4#
SUSC#
[16,35]
D
SYS_RESET#
B5
AY16
+3V_DEEP_SUS
D
[16]
SYS_RESET#
SYS_RESET#
GPD10/SLP_S5#
SLP_S5#
[16]
RSMRST#
AY17
[35]
RSMRST#
RSMRST#
AN15
SLP_SUS#_EC
SUSWARN#
R193
10K_4
SLP_SUS#
SLP_SUS#_EC
[35]
R394
*10K_4 PROCPWRGD
A68
AW15
PROCPWRGD
SLP_LAN#
EC26
H_VCCST_PWRGD
B65
BB17
GPD9
SUSACK#
R200
10K_4
VCCST_PWRGD
GPD9/SLP_WLAN#
TP105
*220P/50V_4
C560
*0.1U/16V_4
AN16
GPD6/SLP_A#
SLP_A#
[16]
SYS_PWROK
B6
RF_OFF_PCH
R187
10K_4
[16]
SYS_PWROK
SYS_PWROK
PCH_PWROK
BA20
BA15
DNBSWON#
[16,35]
EC_PWROK
PCH_PWROK
GPD3/PWRBTN#
DNBSWON#
[35]
DSWROK_EC_R
BB20
AY15
AC_PRESENT_EC
DSW_PWROK
GPD1/ACPRESENT
AC_PRESENT_EC
[20,35]
SUSWARN#
*0_4
R196
AU13
RF_OFF_PCH
+3VS5
GPD0/BATLOW#
RF_OFF_PCH
[34]
R192
*0_4/S
SUSWARN#
AR13
[35]
SUSWARN#_EC
GPP_A13/SUSWARN#/SUSPWRDNACK
0_4
R199
SUSACK#
AP11
PCIE_WAKE#
R204
1K_4
[35]
SUSACK#_EC
GPP_A15/SUSACK#
0423 change to shortpad
AU11
GPP_A11/PME#
PCIE_WAKE#
BB15
AP16
INTRUDER#_R
1M_4
R165
AC_PRESENT_EC
R203
*10K_4
[30,34,35]
PCIE_WAKE#
+3V_RTC
WAKE#
INTRUDER#
LAN_WAKE#
AM15
GPD2/LAN_WAKE#
AW17
AM10
LAN_WAKE#
R591
*10K_4
GPD11/LANPHYPC
GPP_B11/EXT_PWR_GATE#
DDR_VTT_CNTL
AT15
AM11
GPP_B2
[3,18]
DDR_VTT_CNTL
GPD7/RSVD
GPP_B2/VRALERT#
TP10
+3V
Need check circuit!!!!
Should be delete
*SKL_ULT
REV = 1
11 OF 20
SYS_RESET#
R415
10K_4
?
RSMRST#
R208
10K_4
DSWROK_EC
R224
100K/F_4
C
C
For DS3 Sequence
For HWPG, +1.0V and +VCCSTPLL Sequence
+1.0V
+5VS5
+3VS5
For DS3 -->Ra
Non-DS3 -->Rb
Rb
RSMRST#
+1.0V
+VCCSTPLL
R212
*0_4
1216 colayout
+VCCSTPLL & +1.0V
R26
R23
R30
15K/F_4
100K_4
10K_4
R215
0_4
DSWROK_EC_R
[35]
DSWROK_EC
R380
R379
Ra
HWPG
1K_4
*1K_4
D12
1
2
RB500V-40
H_VCCST_PWRGD_R
R395
60.4/F_4
H_VCCST_PWRGD
+1.0V_PWRGD_G2
2
Q5
[16,35,37,38,39]
HWPG
2N7002K
R16
100K_4
PLTRST#(CLG)
R395 close to CPU side
H_VCCST_PWRGD trace 0.3" - 1.5"
+1.0V_PWRGD_G1
2
Q6
Check Q2010 Rise/Fall time less than 100ns
C543
METR3904-G
*10P/50V_4
C32
R21
PLTRST#
[16,19,30,32,34,35]
0.1U/16V_4
100K_4
R14
100K/F_4
B
B
1110 Add Citcuit for +1.0V Power Good
System PWR_OK(CLG)
SYS_PWROK
R411
0_4
EC_PWROK
R412
10K/F_4
A
A
PROJECT : X1A
PROJECT : X1A
PROJECT : X1A
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
Custom
Custom
Custom
06
06
06
-- SKYPAKE 5/20(Power Manger)
-- SKYPAKE 5/20(Power Manger)
-- SKYPAKE 5/20(Power Manger)
1A
1A
1A
NB5
NB5
NB5
Date:
Date:
Date:
Friday, May 22, 2015
Friday, May 22, 2015
Friday, May 22, 2015
Sheet
Sheet
Sheet
4
4
4
of
of
of
49
49
49
5
4
3
2
1
1
3
1
3
5 4 3 2 1 [41] +VCC_CORE 05 [2,4,6,16,32,35,40] +1.0V [6] +VCCSTG ? Need apply
5
4
3
2
1
[41]
+VCC_CORE
05
[2,4,6,16,32,35,40]
+1.0V
[6]
+VCCSTG
?
Need apply PN
[2,4,6,9,40,41]
+VCCSTPLL
SKL_ULT
U17L
+VCC_CORE
+VCC_CORE
Under U17
CPU POWER 1 OF 4
Under U17
A30
G32
VCC_A30
VCC_G32
A34
33A
G33
VCC_A34
VCC_G33
A39
G35
VCC_A39
VCC_G35
A44
G37
C566
C155
C567
C169
C529
C194
C162
VCC_A44
VCC_G37
C59
C47
C52
C518
C517
C519
C60
C524
AK33
G38
1U/6.3V_4
1U/6.3V_4
1U/6.3V_4
1U/6.3V_4
1U/6.3V_4
1U/6.3V_4
1U/6.3V_4
VCC_AK33
VCC_G38
10U/6.3V_6
22U/6.3V_6
22U/6.3V_6
22U/6.3V_6
47U/6.3VS_8
22U/6.3V_6
22U/6.3V_6
22U/6.3V_6
AK35
G40
VCC_AK35
VCC_G40
D
AK37
G42
D
VCC_AK37
VCC_G42
AK38
J30
100- ±1%
VCC_AK38
VCC_J30
AK40
J33
VCC_AK40
VCC_J33
AL33
J37
VCC_AL33
VCC_J37
AL37
J40
pull-up to VCC
near processor.
VCC_AL37
VCC_J40
AL40
K33
C568
C133
C140
C147
C195
C182
C122
C112
VCC_AL40
VCC_K33
C95
C193
C123
C180
C181
C121
C547
AM32
K35
1U/6.3V_4
1U/6.3V_4
1U/6.3V_4
1U/6.3V_4
1U/6.3V_4
1U/6.3V_4
1U/6.3V_4
1U/6.3V_4
VCC_AM32
VCC_K35
10U/6.3V_4
10U/6.3V_4
10U/6.3V_4
10U/6.3V_4
10U/6.3V_4
10U/6.3V_4
10U/6.3V_4
AM33
K37
VCC_AM33
VCC_K37
AM35
K38
VCC_AM35
VCC_K38
AM37
K40
VCC_AM37
VCC_K40
AM38
K42
VCC_AM38
VCC_K42
G30
K43
R98
*100/F_4
VCC_G30
VCC_K43
+VCC_CORE
K32
E32
RSVD_K32
VCC_SENSE
[41]
VCC_SENSE
C523
C63
C83
C70
C520
C55
E33
VSS_SENSE
[41]
VSS_SENSE
22U/6.3V_6
22U/6.3V_6
22U/6.3V_6
22U/6.3V_6
22U/6.3V_6
22U/6.3V_6
AK32
RSVD_AK32
B63
H_CPU_SVIDALRT#
R99
*100/F_4
VIDALERT#
AB62
A63
VR_SVID_CLK_R
VCCOPC_AB62
VIDSCK
P62
D64
H_CPU_SVIDDAT
VCCOPC_P62
VIDSOUT
V62
VCCOPC_V62
G20
VCCSTG_G20
+VCCSTG
H63
VCC_OPC_1P8_H63
G61
VCC_OPC_1P8_G61
AC63
VCCOPC_SENSE
AE63
VSSOPC_SENSE
AE62
VCCEOPIO
AG62
VCCEOPIO
C
C
VCCEOPIO_SENSE
AL63
TP13
VCCEOPIO_SENSE
VSSEOPIO_SENSE
AJ62
TP8
VSSEOPIO_SENSE
PDC
Layout note: need routing together and ALERT need between CLK and DATA.
*SKL_ULT
REV = 1
12 OF 20
Close U17
?
+VCCSTPLL
+VCC_CORE
CLOSE TO CPU
PLACE THE PU RESISTORS
R385
56.2/F_4
SVID ALERT
C151
C522
C521
C167
C135
C136
C166
C152
47U/6.3VS_8
47U/6.3VS_8
47U/6.3VS_8
47U/6.3VS_8
47U/6.3VS_8
47U/6.3VS_8
47U/6.3VS_8
47U/6.3VS_8
H_CPU_SVIDALRT#
R398
220/F_4
VR_SVID_ALERT#
[41]
C534
+VCC_CORE
*0.1U/16V_4
C120
C87
C93
C113
C535
C538
C565
C562
10U/6.3V_4
10U/6.3V_4
10U/6.3V_4
10U/6.3V_4
10U/6.3V_4
10U/6.3V_4
10U/6.3V_4
10U/6.3V_4
+VCCSTPLL
B
B
PLACE THE PU RESISTORS
CLOSE TO VR
PULL UP IS IN THE VR MODULE
R383
*54.9/F_4
SVID CLK
VR_SVID_CLK_R
R403
*0_4/S
VR_SVID_CLK
[41]
0423 change to shortpad
+VCCSTPLL
R397
100/F_4
CLOSE TO CPU
PLACE THE PU RESISTORS
SVID DATA
H_CPU_SVIDDAT
R382
*0_4/S
VR_SVID_DATA
[41]
0423 change to shortpad
A
A
PROJECT : X1A
PROJECT : X1A
PROJECT : X1A
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
Custom
Custom
Custom
07
07
07
-- SKYPAKE 6/20 (POWER-1)
-- SKYPAKE 6/20 (POWER-1)
-- SKYPAKE 6/20 (POWER-1)
1A
1A
1A
NB5
NB5
NB5
Date:
Date:
Date:
Wednesday, May 13, 2015
Wednesday, May 13, 2015
Wednesday, May 13, 2015
Sheet
Sheet
Sheet
5
5
5
of
of
of
49
49
49
5
4
3
2
1
5 4 3 2 1 +VCCSTPLL [2,4,5,9,40,41] +VCCSA [41,42] 06 +1.35VSUS [3,17,18,38,40] +1.0V_DEEP_SUS
5
4
3
2
1
+VCCSTPLL
[2,4,5,9,40,41]
+VCCSA
[41,42]
06
+1.35VSUS
[3,17,18,38,40]
+1.0V_DEEP_SUS
[9,13,15,16,39,40]
+1.0V
[2,4,16,32,35,40]
+3VPCU
[13,30,31,32,33,34,35,36,37]
+VCCIO
[2,16,40]
Need apply PN
+1.35VSUS
+VCCIO
?
Under U17
U17N
SKL_ULT
Under U17
Close U17
CPU POWER 3 OF 4
AU23
AK28
VDDQ_AU23
VCCIO
AU28
2A
3.1A
AK30
VDDQ_AU28
VCCIO
D
C281
C297
C268
C271
C270
C258
AU35
AL30
C161
C188
C190
C154
C138
C145
C189
C178
C192
C168
D
VDDQ_AU35
VCCIO
10U/6.3V_4
10U/6.3V_4
1U/6.3V_4
1U/6.3V_4
1U/6.3V_4
1U/6.3V_4
AU42
AL42
1U/6.3V_4
1U/6.3V_4
1U/6.3V_4
10U/6.3V_4
10U/6.3V_4
10U/6.3V_4
1U/6.3V_4
1U/6.3V_4
1U/6.3V_4
1U/6.3V_4
BB23
VDDQ_AU42
VCCIO
AM28
VDDQ_BB23
VCCIO
BB32
AM30
VDDQ_BB32
VCCIO
Close U17
BB41
AM42
+VCCSA
BB47
VDDQ_BB41
VCCIO
Under U17
VDDQ_BB47
BB51
AK23
VDDQ_BB51
VCCSA
4.5A
AK25
VCCSA
G23
VCCSA
C260
C278
C269
C273
AM40
G25
VDDQC
VCCSA
10U/6.3V_4
10U/6.3V_4
10U/6.3V_4
10U/6.3V_4
G27
C544
C530
C67
C532
C80
C94
C170
C107
C125
C542
C551
C558
C86
C536
VCCSA
A18
0.12A
G28
1U/6.3V_4
1U/6.3V_4
1U/6.3V_4
1U/6.3V_4
1U/6.3V_4
1U/6.3V_4
1U/6.3V_4
10U/6.3V_4
10U/6.3V_4
10U/6.3V_4
10U/6.3V_4
10U/6.3V_4
10U/6.3V_4
10U/6.3V_4
+VCCSTPLL
VCCST
VCCSA
C200
C196
J22
VCCSA
*10U/6.3V_4
1U/6.3V_4
A22
0.04A
J23
+VCCSTG
VCCSTG_A22
VCCSA
J27
VCCSA
AL23
K23
+VCCPLL_OC
VCCPLL_OC
VCCSA
K25
Close U17
VCCSA
+VCCSTPLL
120mA
K20
0.12A
K27
C126
C108
C163
C179
C41
C91
VCCPLL_K20
VCCSA
Close U17 Under U17
K21
K28
10U/6.3V_4
10U/6.3V_4
10U/6.3V_4
10U/6.3V_4
10U/6.3V_4
10U/6.3V_4
+VCCPLL
VCCPLL_K21
VCCSA
R556
0_4
K30
VCCSA
+VCCIO
+1.0V
+VCCSTG
AM23
VCCIO_VCCSENSE
VCCIO_SENSE
AM22
VCCIO_VSSSENSE
VSSIO_SENSE
R75
*0_4
H21
VSSSA_SENSE
VSSSA_SENSE
[41]
+VCCIO
H20
VCCIO_VCCSENSE
R135
100/F_4
VCCSA_SENSE
VCCSA_SENSE
[41]
E
R589
*0_4
0421 Add R588,R589
for Modern Stand By
*SKL_ULT
REV = 1
14 OF 20
VCCIO_VSSSENSE
R186
100/F_4
C
C
+1.35VSUS
+VCCPLL_OC
R168
0_6
+1.35V_VCCPLL_OC
R588
*0_6
+VCCSTPLL
+VCCPLL
R67
*0_6/S
0423 change to shortpad
IO Thrm Protect
1226 Add thermistor circuit for CPU & DDR
Under U17
+VCCSTG
+VCCPLL_OC
+3VPCU
+3VPCU
+3VPCU
C98
C230
For 65 degree, 1.8v limit, (SW)
For 65 degree, 1.8v limit, (SW)
For 65 degree, 1.8v limit, (SW)
1U/6.3V_4
1U/6.3V_4
R146
R549
R551
20K/F_4
20K/F_4
*20K/F_4
B
B
Close A18 Ball
+VCCSTPLL
R550 close R44
R552 close U12
For 75 degree, 1.2v limit, (HW)
For 75 degree, 1.2v limit, (HW)
For 75 degree, 1.2v limit, (HW)
C96
C82
THRM_MOINTOR1
[35]
THRM_MOINTOR2
[35]
THRM_MOINTOR3
[35]
*1U/6.3V_4
*22U/6.3V_6
THER_PIPE
THER_CPU
THER_DDR
R142
C206
R550
C659
R552
C660
100K_4 NTC
0.1U/16V_4
100K_4 NTC
0.1U/16V_4
*100K_4 NTC
*0.1U/16V_4
Close U17
+VCCSTPLL
+VCCPLL
+1.35VSUS
C69
C134
Close U17
1U/6.3V_4
1U/6.3V_4
A
A
C229
C240
C237
C255
C228
C238
C257
C289
C279
C305
10U/6.3V_6
10U/6.3V_6
10U/6.3V_6
10U/6.3V_6
10U/6.3V_6
10U/6.3V_6
1U/6.3V_4
1U/6.3V_4
1U/6.3V_4
1U/6.3V_4
PROJECT : X1A
PROJECT : X1A
PROJECT : X1A
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
Custom
Custom
Custom
08
08
08
-- SKYPAKE 7/20 (POWER-2)
-- SKYPAKE 7/20 (POWER-2)
-- SKYPAKE 7/20 (POWER-2)
1A
1A
1A
NB5
NB5
NB5
Date:
Date:
Date:
Friday, May 22, 2015
Friday, May 22, 2015
Friday, May 22, 2015
Sheet
Sheet
Sheet
6
6
6
of
of
of
49
49
49
5
4
3
2
1
1
2
1
2
1
2

5

4

3

2

1

D

C

5 4 3 2 1 D C B A 07 D C B A +VCCGT [41]

B

A

07
07

D

C

5 4 3 2 1 D C B A 07 D C B A +VCCGT [41]

B

A

5 4 3 2 1 D C B A 07 D C B A +VCCGT [41]

+VCCGT

[41]

U17M

Need apply PN
?

+VCCGT

SKL_ULT

+VCCGT

Close U17 CPU POWER 2 OF 4 Under U17 N70 VCCGT A48 N71 VCCGT VCCGT
Close U17
CPU POWER 2 OF 4
Under U17
N70
VCCGT
A48
N71
VCCGT
VCCGT
A53
R63
31A
VCCGT
VCCGT
A58
R64
C175
C157
C143
C124
C149
C150
VCCGT
VCCGT
C76
C186
C118
C576
C117
A62
R65
47U/6.3VS_8
47U/6.3VS_8
47U/6.3VS_8
47U/6.3VS_8
47U/6.3VS_8
47U/6.3VS_8
VCCGT
VCCGT
10U/6.3V_4
10U/6.3V_4
10U/6.3V_4
10U/6.3V_4
10U/6.3V_4
A66
R66
VCCGT
VCCGT
AA63
R67
VCCGT
VCCGT
AA64
R68
VCCGT
VCCGT
AA66
R69
VCCGT
VCCGT
AA67
R70
VCCGT
VCCGT
AA69
R71
VCCGT
VCCGT
AA70
T62
VCCGT
VCCGT
AA71
U65
C185
C183
C173
C172
C174
C156
VCCGT
VCCGT
C111
C142
C129
C159
C130
AC64
U68
22U/6.3V_6
22U/6.3V_6
22U/6.3V_6
22U/6.3V_6
22U/6.3V_6
22U/6.3V_6
VCCGT
VCCGT
10U/6.3V_4
10U/6.3V_4
10U/6.3V_4
10U/6.3V_4
10U/6.3V_4
AC65
U71
VCCGT
VCCGT
AC66
W63
VCCGT
VCCGT
AC67
W64
VCCGT
VCCGT
AC68
W65
VCCGT
VCCGT
AC69
W66
VCCGT
VCCGT
AC70
W67
VCCGT
VCCGT
AC71
W68
VCCGT
VCCGT
J43
W69
C148
C127
C115
C184
C137
C165
VCCGT
VCCGT
J45
W70
22U/6.3V_6
22U/6.3V_6
22U/6.3V_6
22U/6.3V_6
22U/6.3V_6
22U/6.3V_6
VCCGT
VCCGT
C141
C114
C119
C578
C109
C110
J46
W71
VCCGT
VCCGT
1U/6.3V_4
1U/6.3V_4
1U/6.3V_4
1U/6.3V_4
1U/6.3V_4
1U/6.3V_4
J48
Y62
VCCGT
VCCGT
J50
VCCGT
J52
VCCGT
J53
AK42
VCCGT
VCCGTX_AK42
J55
AK43
VCCGT
VCCGTX_AK43
J56
AK45
VCCGT
VCCGTX_AK45
J58
AK46
VCCGT
VCCGTX_AK46
J60
AK48
VCCGT
VCCGTX_AK48
C160
C92
C85
C64
C563
C131
K48
AK50
VCCGT
VCCGTX_AK50
1U/6.3V_4
1U/6.3V_4
1U/6.3V_4
1U/6.3V_4
1U/6.3V_4
1U/6.3V_4
K50
AK52
VCCGT
VCCGTX_AK52
K52
AK53
VCCGT
VCCGTX_AK53
K53
AK55
VCCGT
VCCGTX_AK55
K55
AK56
VCCGT
VCCGTX_AK56
K56
AK58
VCCGT
VCCGTX_AK58
K58
AK60
VCCGT
VCCGTX_AK60
K60
AK70
VCCGT
VCCGTX_AK70
L62
AL43
VCCGT
VCCGTX_AL43
L63
AL46
VCCGT
VCCGTX_AL46
L64
AL50
VCCGT
VCCGTX_AL50
L65
AL53
VCCGT
VCCGTX_AL53
L66
AL56
VCCGT
VCCGTX_AL56
L67
AL60
VCCGT
VCCGTX_AL60
L68
AM48
VCCGT
VCCGTX_AM48
L69
AM50
VCCGT
VCCGTX_AM50
L70
AM52
VCCGT
VCCGTX_AM52
L71
AM53
VCCGT
VCCGTX_AM53
M62
AM56
VCCGT
VCCGTX_AM56
N63
AM58
VCCGT
VCCGTX_AM58
N64
AU58
VCCGT
VCCGTX_AU58
N66
AU63
VCCGT
VCCGTX_AU63
N67
BB57
VCCGT
VCCGTX_BB57
N69
BB66
VCCGT
VCCGTX_BB66
J70
AK62
[41]
VCCGT_SENSE
VCCGT_SENSE
VCCGTX_SENSE
J69
AL61
[41]
VSSGT_SENSE
VSSGT_SENSE
VSSGTX_SENSE
PDC
*SKL_ULT
REV = 1
13 OF 20
VSSGT_SENSE VSSGTX_SENSE PDC *SKL_ULT REV = 1 13 OF 20 NB5 NB5 NB5 PROJECT : X1A

NB5

NB5

NB5

PROJECT : X1A

PROJECT : X1A

PROJECT : X1A

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

Size

Size

Size

Custom

Custom

Custom

Document Number

Document Number

Document Number

09

09 09

-- SKYPAKE 8/20 (POWER-3)

-- SKYPAKE 8/20 (POWER-3)

-- SKYPAKE 8/20 (POWER-3)

Rev

Rev

Rev

1A

1A

1A

5

4

3

2

1

Date:

Date:

Date:

Wednesday, May 13, 2015

Wednesday, May 13, 2015

Wednesday, May 13, 2015

Sheet

Sheet

Sheet

7

7 7

of

of

of

49

49

49

5 4 3 2 1 08 U17Q Need apply PN U17P Need apply PN SKL_ULT
5
4
3
2
1
08
U17Q
Need apply PN
U17P
Need apply PN
SKL_ULT
?
SKL_ULT
?
D
U17R
D
Need apply PN
GND 2 OF 3
?
SKL_ULT
GND 1 OF 3
R
AT63
BA49
VSS
VSS
A5
AL65
AT68
BA53
GND 3 OF 3
VSS
VSS
VSS
VSS
A67
AL66
AT71
BA57
F8
VSS
VSS
VSS
VSS
VSS
L18
A70
AM13
AU10
BA6
G10
VSS
VSS
VSS
VSS
VSS
VSS
L2
AA2
AM21
AU15
BA62
G22
VSS
VSS
VSS
VSS
VSS
VSS
L20
AA4
AM25
AU20
BA66
G43
VSS
VSS
VSS
VSS
VSS
VSS
L4
AA65
AM27
AU32
BA71
G45
VSS
VSS
VSS
VSS
VSS
VSS
L8
AA68
AM43
AU38
BB18
G48
VSS
VSS
VSS
VSS
VSS
VSS
N10
AB15
AM45
AV1
BB26
G5
VSS
VSS
VSS
VSS
VSS
VSS
N13
AB16
AM46
AV68
BB30
G52
VSS
VSS
VSS
VSS
VSS
VSS
N19
AB18
AM55
AV69
BB34
G55
VSS
VSS
VSS
VSS
VSS
VSS
N21
AB21
AM60
AV70
BB38
G58
VSS
VSS
VSS
VSS
VSS
VSS
N6
AB8
AM61
AV71
BB43
G6
VSS
VSS
VSS
VSS
VSS
VSS
N65
AD13
AM68
AW10
BB55
G60
VSS
VSS
VSS
VSS
VSS
VSS
N68
AD16
AM71
AW12
BB6
G63
VSS
VSS
VSS
VSS
VSS
VSS
P17
AD19
AM8
AW14
BB60
G66
VSS
VSS
VSS
VSS
VSS
VSS
P19
AD20
AN20
AW16
BB64
H15
VSS
VSS
VSS
VSS
VSS
VSS
P20
AD21
AN23
AW18
BB67
H18
VSS
VSS
VSS
VSS
VSS
VSS
P21
AD62
AN28
AW21
BB70
H71
VSS
VSS
VSS
VSS
VSS
VSS
R13
AD8
AN30
AW23
C1
J11
VSS
VSS
VSS
VSS
VSS
VSS
R6
AE64
AN32
AW26
C25
J13
VSS
VSS
VSS
VSS
VSS
VSS
T15
AE65
AN33
AW28
C5
J25
VSS
VSS
VSS
VSS
VSS
VSS
T17
AE66
AN35
AW30
D10
J28
VSS
VSS
VSS
VSS
VSS
VSS
T18
AE67
AN37
AW32
D11
J32
VSS
VSS
VSS
VSS
VSS
VSS
T2
AE68
AN38
AW34
D14
J35
VSS
VSS
VSS
VSS
VSS
VSS
T21
AE69
AN40
AW36
D18
J38
VSS
VSS
VSS
VSS
VSS
VSS
T4
AF1
AN42
AW38
D22
J42
VSS
VSS
VSS
VSS
VSS
C
C
VSS
U10
AF10
AN58
AW41
D25
J8
VSS
VSS
VSS
VSS
VSS
VSS
U63
AF15
AN63
AW43
D26
K16
VSS
VSS
VSS
VSS
VSS
VSS
U64
AF17
AP10
AW45
D30
K18
VSS
VSS
VSS
VSS
VSS
VSS
U66
AF2
AP18
AW47
D34
K22
VSS
VSS
VSS
VSS
VSS
VSS
U67
AF4
AP20
AW49
D39
K61
VSS
VSS
VSS
VSS
VSS
VSS
U69
AF63
AP23
AW51
D44
K63
VSS
VSS
VSS
VSS
VSS
VSS
U70
AG16
AP28
AW53
D45
K64
VSS
VSS
VSS
VSS
VSS
VSS
V16
AG17
AP32
AW55
D47
K65
VSS
VSS
VSS
VSS
VSS
VSS
V17
AG18
AP35
AW57
D48
K66
VSS
VSS
VSS
VSS
VSS
VSS
V18
AG19
AP38
AW6
D53
K67
VSS
VSS
VSS
VSS
VSS
VSS
W13
AG20
AP42
AW60
D58
K68
VSS
VSS
VSS
VSS
VSS
VSS
W6
AG21
AP58
AW62
D6
K70
VSS
VSS
VSS
VSS
VSS
VSS
W9
AG71
AP63
AW64
D62
K71
VSS
VSS
VSS
VSS
VSS
VSS
Y17
AH13
AP68
AW66
D66
L11
VSS
VSS
VSS
VSS
VSS
VSS
Y19
AH6
AP70
AW8
D69
L16
VSS
VSS
VSS
VSS
VSS
VSS
Y20
AH63
AR11
AY66
E11
L17
VSS
VSS
VSS
VSS
VSS
VSS
Y21
AH64
AR15
B10
E15
VSS
VSS
VSS
VSS
VSS
AH67
AR16
B14
E18
VSS
VSS
VSS
VSS
AJ15
AR20
B18
E21
VSS
VSS
VSS
VSS
AJ18
AR23
B22
E46
VSS
VSS
VSS
VSS
*SKL_ULT
REV = 1
18 OF 20
AJ20
AR28
B30
E50
VSS
VSS
VSS
VSS
AJ4
AR35
B34
E53
?
VSS
VSS
VSS
VSS
AK11
AR42
B39
E56
VSS
VSS
VSS
VSS
AK16
AR43
B44
E6
VSS
VSS
VSS
VSS
AK18
AR45
B48
E65
VSS
VSS
VSS
VSS
AK21
AR46
B53
E71
VSS
VSS
VSS
VSS
AK22
AR48
B58
F1
VSS
VSS
VSS
VSS
AK27
AR5
B62
F13
VSS
VSS
VSS
VSS
AK63
AR50
B66
F2
VSS
VSS
VSS
VSS
AK68
AR52
B71
F22
VSS
VSS
VSS
VSS
B
AK69
AR53
BA1
F23
B
VSS
VSS
VSS
VSS
AK8
AR55
BA10
F27
VSS
VSS
VSS
VSS
AL2
AR58
BA14
F28
VSS
VSS
VSS
VSS
AL28
AR63
BA18
F32
VSS
VSS
VSS
VSS
AL32
AR8
BA2
F33
VSS
VSS
VSS
VSS
AL35
AT2
BA23
F35
VSS
VSS
VSS
VSS
AL38
AT20
BA28
F37
VSS
VSS
VSS
VSS
AL4
AT23
BA32
F38
VSS
VSS
VSS
VSS
AL45
AT28
BA36
F4
VSS
VSS
VSS
VSS
AL48
AT35
F68
F40
VSS
VSS
VSS
VSS
AL52
AT4
BA45
F42
VSS
VSS
VSS
VSS
AL55
AT42
BA41
VSS
VSS
VSS
AL58
AT56
VSS
VSS
AL64
AT58
PDC
VSS
VSS
*SKL_ULT
REV = 1
16 OF 20
*SKL_ULT
REV = 1
17 OF 20
?
?
A
A
PROJECT : X1A
PROJECT : X1A
PROJECT : X1A
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
Custom
Custom
Custom
10
10 10
-- SKYPAKE 9/20 (GND-1)
-- SKYPAKE 9/20 (GND-1)
-- SKYPAKE 9/20 (GND-1)
1A
1A
1A
NB5
NB5
NB5
Date:
Date:
Date:
Friday, May 22, 2015
Friday, May 22, 2015
Friday, May 22, 2015
Sheet
Sheet
Sheet
8
8 8
of
of
of
49
49
49
5
4
3
2
1
5 4 3 2 1 +1.0V_DEEP_SUS [13,15,16,39,40] 09 +1.8V_DEEP_SUS [15,39,46] +VCCSTPLL [2,4,5,6,40,41] ? SKL_ULT
5
4
3
2
1
+1.0V_DEEP_SUS
[13,15,16,39,40]
09
+1.8V_DEEP_SUS
[15,39,46]
+VCCSTPLL
[2,4,5,6,40,41]
?
SKL_ULT
Need apply PN
U17S
CFG0-19 need Reserve TP
RESERVED SIGNALS-1
CFG0
E68
BB68
[16]
CFG0
CFG[0]
RSVD_TP_BB68
D
CFG1
B67
BB69
D
[16]
CFG1
CFG[1]
RSVD_TP_BB69
CFG2
D65
[16]
CFG2
CFG[2]
CFG3
D67
AK13
[16]
CFG3
CFG[3]
RSVD_TP_AK13
CFG4
E70
AK12
[16]
CFG4
Need apply PN
CFG[4]
RSVD_TP_AK12
CFG5
C68
[16]
CFG5
CFG[5]
?
CFG6
D68
BB2
U17T
SKL_ULT
[16]
CFG6
CFG[6]
RSVD_BB2
CFG7
C67
BA3
[16]
CFG7
CFG[7]
RSVD_BA3
CFG8
F71
SPARE
[16]
CFG8
CFG[8]
CFG9
G69
[16]
CFG9
CFG[9]
CFG10
F70
AU5
AW69
F6
[16]
CFG10
CFG[10]
TP5
RSVD_AW69
RSVD_F6
CFG11
G68
AT5
1226 Add R548, C658
for Cannonlake-U
reserved
AW68
E3
[16]
CFG11
CFG[11]
TP6
RSVD_AW68
RSVD_E3
CFG12
H70
AU56
C11
[16]
CFG12
CFG[12]
RSVD_AU56
RSVD_C11
CFG13
G71
AW48
B11
[16]
CFG13
CFG[13]
RSVD_AW48
RSVD_B11
CFG14
H69
D5
C7
A11
[16]
CFG14
CFG[14]
RSVD_D5
RSVD_C7
RSVD_A11
CFG15
G70
D4
R548
*0_4
U12
D12
[16]
CFG15
CFG[15]
RSVD_D4
+1.8V_DEEP_SUS
RSVD_U12
RSVD_D12
B2
U11
C12
RSVD_B2
RSVD_U11
RSVD_C12
CFG16
E63
C2
H11
F52
[16]
CFG16
CFG[16]
RSVD_C2
RSVD_H11
RSVD_F52
CFG17
F63
[16]
CFG17
CFG[17]
B3
C658
RSVD_B3
CFG18
E66
A3
*1U/6.3V_4
[16]
CFG18
CFG[18]
RSVD_A3
CFG19
F66
*SKL_ULT
REV = 1
20 OF 20
[16]
CFG19
CFG[19]
AW1
?
RSVD_AW1
+1.0V_DEEP_SUS
R97
49.9/F_4
CFG_RCOMP
E60
CFG_RCOMP
E1
RSVD_E1
R72
*1K_4
E8
E2
ITP_PMODE
RSVD_E2
AY2
RSVD_AY2
RSVD_BA4
BA4
AY1
BB4
RSVD_AY1
RSVD_BB4
D1
RSVD_D1
RSVD_A4
A4
C
D3
C4
C
RSVD_D3
RSVD_C4
K46
BB5
RSVD_K46
TP4
K45
RSVD_K45
A69
RSVD_A69
AL25
B69
RSVD_AL25
RSVD_B69
AL27
RSVD_AL27
AY3
R457
*0_4/S
RSVD_AY3
C71
RSVD_C71
B70
D71
RSVD_B70
RSVD_D71
C70
RSVD_C70
F60
RSVD_F60
C54
0423 change to shortpad
RSVD_C54
A52
D54
RSVD_A52
RSVD_D54
BA70
AY4
RSVD_TP_BA70
TP1
BA68
BB3
RSVD_TP_BA68
TP2
J71
AY71
R491
*0_4/S
RSVD_J71
VSS_AY71
J68
AR56
RSVD_J68
ZVM#
F65
AW71
VSS_F65
RSVD_TP_AW71
G65
AW70
VSS_G65
RSVD_TP_AW70
F61
AP56
RSVD_F61
MSM#
E61
C64
R396
*100K_4
RSVD_E61
PROC_SELECT#
+VCCSTPLL
PDC
1222 Cannonlake-U stuff, Skylake-U un-stuff
*SKL_ULT
REV = 1
19 OF 20
B
B
?
Processor Strapping
The CFG signals have a default value of '1' if not terminated on the board.
1
0
Circuit
CFG3
Disable:
Enable: Set DFX Enable in DFX interface MSR
CFG3
R387
*1K_4
(Physcial Debug Enable)
DFX Privacy
CFG4
Disable; No physical DP attached to eDP
Enable; An ext DP device is connected to eDP
CFG4
R427
1K_4
(DP Presence Strap)
A
A
PROJECT : X1A
PROJECT : X1A
PROJECT : X1A
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
Custom
Custom
Custom
13
13
13
-- SKYPAKE 12/20 (RSV-1)
-- SKYPAKE 12/20 (RSV-1)
-- SKYPAKE 12/20 (RSV-1)
1A
1A
1A
NB5
NB5
NB5
Date:
Date:
Date:
Wednesday, May 13, 2015
Wednesday, May 13, 2015
Wednesday, May 13, 2015
Sheet
Sheet
Sheet
9
9
9
of
of
of
49
49
49
5
4
3
2
1

5

4

3

2

1

D

C

5 4 3 2 1 D C D C +3V_DEEP_SUS [4,11,12,14,15,16,18] 10 +3V +3VS5

D

C

5 4 3 2 1 D C D C +3V_DEEP_SUS [4,11,12,14,15,16,18] 10 +3V +3VS5
5 4 3 2 1 D C D C +3V_DEEP_SUS [4,11,12,14,15,16,18] 10 +3V +3VS5

+3V_DEEP_SUS

[4,11,12,14,15,16,18]

10

+3V

+3VS5

[2,4,11,12,13,14,15,16,17,18,27,28,29,30,31,32,33,34,35,41,43]

[4,15,16,32,34,35,37,39,40,43,44,46]

?

SKL_ULT

U17E

Need apply PN

SPI - FLASH

SMBUS, SMLINK

SPI0_CLK

SPI0_MISO

SPI0_MOSI

SPI0_IO2

SPI0_IO3

SPI0_CS0#

SPI0_CS1#

SPI0_CS2#

GPP_C0/SMBCLK

GPP_C1/SMBDATA

GPP_C2/SMBALERT#

GPP_C3/SML0CLK

GPP_C4/SML0DATA

GPP_C5/SML0ALERT#

SPI - TOUCH

GPP_D1/SPI1_CLK

GPP_D2/SPI1_MISO

GPP_D3/SPI1_MOSI

GPP_D21/SPI1_IO2

GPP_D22/SPI1_IO3

GPP_D0/SPI1_CS#

D

GPP_C6/SML1CLK

GPP_C7/SML1DATA

GPP_B23/SML1ALERT#/PCHHOT#

LPC

GPP_A1/LAD0/ESPI_IO0

GPP_A2/LAD1/ESPI_IO1

GPP_A3/LAD2/ESPI_IO2

GPP_A4/LAD3/ESPI_IO3

GPP_A5/LFRAME#/ESPI_CS#

GPP_A14/SUS_STAT#/ESPI_RESET#

PDC

GPP_A9/CLKOUT_LPC0/ESPI_CLK

GPP_A10/CLKOUT_LPC1

GPP_A8/CLKRUN#

C LINK

CL_CLK

CL_DATA

CL_RST#

GPP_A0/RCIN#

GPP_A6/SERIRQ

*SKL_ULT REV = 1

5 OF 20

?

AY9

PCH_SPI1_CLK AV2 PCH_SPI1_SO AW3 PCH_SPI1_SI AV3 PCH_SPI_IO2 AW2 PCH_SPI_IO3 AU4 PCH_SPI_CS0# AU3 AU2 AU1
PCH_SPI1_CLK
AV2
PCH_SPI1_SO
AW3
PCH_SPI1_SI
AV3
PCH_SPI_IO2
AW2
PCH_SPI_IO3
AU4
PCH_SPI_CS0#
AU3
AU2
AU1
TP54
SPI1_CLK
M2
SIO_EXT_SMI#
M3
PCI_SERR#
J4
SPI1_IO2
V1
TP66
SPI1_IO3
V2
TP65
SPI1_CS#
M1
TP51
G3
G2
G1

AW13

SPI1_IO3 V2 TP65 SPI1_CS# M1 TP51 G3 G2 G1 AW13 AY11 R7 SMB_PCH_CLK R8 SMB_PCH_DAT R10

AY11

SPI1_IO3 V2 TP65 SPI1_CS# M1 TP51 G3 G2 G1 AW13 AY11 R7 SMB_PCH_CLK R8 SMB_PCH_DAT R10
R7 SMB_PCH_CLK R8 SMB_PCH_DAT R10 SML0ALERT# SML0ALERT# [11] R9 SMB_ME0_CLK W2 SMB_ME0_DAT W1 SML1ALERT#
R7
SMB_PCH_CLK
R8
SMB_PCH_DAT
R10
SML0ALERT#
SML0ALERT#
[11]
R9
SMB_ME0_CLK
W2
SMB_ME0_DAT
W1
SML1ALERT#
SML1ALERT#
[11]
W3
SMB_ME1_CLK
V3
SMB_ME1_DAT
AM7
GPP_B23
TP19
AY13
LAD0
[32,34,35]
BA13
LAD1
[32,34,35]
BB13
LAD2
[32,34,35]
AY12
LAD3
[32,34,35]
BA12
LFRAME#
[32,34,35]
BA11

AW9

CLK_PCI_EC_R

R171

CLK_PCI_LPC_R

R166 CLK_PCI_LPC_R

AW11 CLKRUN#

CLKRUN#
CLKRUN#

[35]

R170

R171 CLK_PCI_LPC_R R166 AW11 CLKRUN# CLKRUN# [35] R170 [35] [35] SIO_EXT_SMI# PCI_SERR# 22/F_4 22/F_4 *22/F_4

[35]

[35]

SIO_EXT_SMI#

PCI_SERR#

22/F_4

22/F_4

*22/F_4

EC25

EC21

EC22

*18P/50V_4

18P/50V_4

22/F_4 *22/F_4 EC25 EC21 EC22 *18P/50V_4 18P/50V_4 CLK_24M_KBC [35] [32,35] EC_RCIN# SERIRQ CLK_24M_DEBUG [35]

CLK_24M_KBC

[35]

[32,35]

EC_RCIN#

SERIRQ

CLK_24M_DEBUG

[35]

[34]

18P/50V_4

EMI(near PCH)[32,35] EC_RCIN# SERIRQ CLK_24M_DEBUG [35] [34] 18P/50V_4 [32] CLK_PCI_TPM EMI(near PCH) PCH SPI ROM(CLG)

[32]

CLK_PCI_TPM

EMI(near PCH)

PCH SPI ROM(CLG) +3V_DEEP_SUS SMB_PCH_CLK R91 2.2K_4 Vender Size P/N SMB_PCH_DAT R88 2.2K_4 EON 8MB
PCH SPI ROM(CLG)
+3V_DEEP_SUS
SMB_PCH_CLK
R91
2.2K_4
Vender
Size
P/N
SMB_PCH_DAT
R88
2.2K_4
EON
8MB
AKE3EZN0Q01 (EN25QH64-104HIP)
SMB_ME0_CLK
R103
499/F_4
Winbond
8MB
AKE3EFP0N07 (W25Q64FVSSIQ)
SMB_ME0_DAT
R442
499/F_4
GigaDevice
8MB
AKE3EGN0Q01 (GD25B64BSIGR)
SMB_ME1_CLK
R439
1K_4
Socket
DFHS08FS023
SMB_ME1_DAT
R436
1K_4
[35]
[35]
[35]
[35]

PCH_SPI_CS0#_R

PCH_SPI1_CLK_R

PCH_SPI1_SI_R

PCH_SPI1_SO_R

TP66-71 need place to TOP

TP43

TP78

TP75

TP44

TP40

TP67

PCH_SPI_CS0#_R

PCH_SPI1_CLK_R

PCH_SPI1_SI_R

PCH_SPI1_SO_R

BIOS_WP#

HOLD#

B

A

GPIO Pull UP

+3V

SERIRQ

R210

10K_4

CLKRUN#

R513

8.2K_4

SIO_EXT_SMI#

R431

10K_4

EC_RCIN#

R512

10K_4

PCI_SERR#

R430

10K_4

4M SPI ROM Socket U16 PCH_SPI_CS0#_R 1 8 +3VSPI CE# VDD PCH_SPI1_CLK_R 6 SCK PCH_SPI1_SI_R
4M SPI ROM Socket
U16
PCH_SPI_CS0#_R
1
8 +3VSPI
CE#
VDD
PCH_SPI1_CLK_R
6
SCK
PCH_SPI1_SI_R
5
SI
PCH_SPI1_SO_R
2
7
HOLD#
SO
HOLD#
BIOS_WP#
3
4
WP#
VSS
A25LQ32AM-F/Q

AKE3EFP0N07

91960-0084L-8P-SOCKET

U15&U16 footprint 要要要

B

A

PCH SPI ROM(CLG)

+3VS5

+3V_DEEP_SUS

U15 CE# VDD SCK SI SO HOLD# WP# VSS *GD25B64BSIGR
U15
CE#
VDD
SCK
SI
SO
HOLD#
WP#
VSS
*GD25B64BSIGR

AKE3EFP0N07

SMBus/Pull-up(CLG)

4 [18,27,35] MBCLK2 1 [18,27,35] MBDATA2 R89 4.7K_4 +3V 4 [16,17,18,27,31] SMB_RUN_DAT R87 4.7K_4 +3V
4
[18,27,35]
MBCLK2
1
[18,27,35]
MBDATA2
R89
4.7K_4
+3V
4
[16,17,18,27,31]
SMB_RUN_DAT
R87
4.7K_4
+3V
1
[16,17,18,27,31]
SMB_RUN_CLK

Q34

R87 4.7K_4 +3V 1 [16,17,18,27,31] SMB_RUN_CLK Q34 *2N7002KDW +3V 5 3 SMB_ME1_CLK 2 6 SMB_ME1_DAT Q11

*2N7002KDW

+3V 5 3 SMB_ME1_CLK 2 6 SMB_ME1_DAT
+3V
5
3
SMB_ME1_CLK
2
6
SMB_ME1_DAT

Q11

5

3

6

+3V

SMB_PCH_DAT

SMB_PCH_CLK

2SMB_ME1_DAT Q11 5 3 6 +3V SMB_PCH_DAT SMB_PCH_CLK 2N7002KDW CPU heat pipe local thermal sensor DDR

2N7002KDW

CPU heat pipe local thermal sensor

DDR thermal sensor

RTD2136

EC

Touch Pad

XDP

DDR3-L

R451 *0_4 R452 0_4 8 +3VSPI R437 1K_4 7 HOLD# R443 15/F_4 PCH_SPI_IO3 4 C583
R451
*0_4
R452
0_4
8
+3VSPI
R437
1K_4
7
HOLD#
R443
15/F_4
PCH_SPI_IO3
4
C583
0.1U/16V_4

R401/R402/R410/R438/R443/R444 close to U15 pin

PCH_SPI_CS0# R401 15/F_4 PCH_SPI_CS0#_R 1 PCH_SPI1_CLK R444 15/F_4 PCH_SPI1_CLK_R 6 PCH_SPI1_SI R438 15/F_4
PCH_SPI_CS0#
R401
15/F_4
PCH_SPI_CS0#_R
1
PCH_SPI1_CLK
R444
15/F_4
PCH_SPI1_CLK_R
6
PCH_SPI1_SI
R438
15/F_4
PCH_SPI1_SI_R
5
PCH_SPI1_SO
R402
15/F_4
PCH_SPI1_SO_R
2
3
C577
22P/50V_4
C580
1U/10V_4
+3VSPI
R409
1K_4
PCH_SPI_IO2
R410
15/F_4
BIOS_WP#

1222 change R409,R437 from 3.3K 1% to 1K 5%

15/F_4 BIOS_WP# 1222 change R409,R437 from 3.3K 1% to 1K 5% NB5 NB5 NB5 PROJECT :

NB5

NB5

NB5

PROJECT : X1A

PROJECT : X1A

PROJECT : X1A

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

Size

Size

Size

Custom

Custom

Custom

Document Number

Document Number

Document Number

15

15 15

-- SKYPAKE 14/20(SPI/LPC/SMBUS)

-- SKYPAKE 14/20(SPI/LPC/SMBUS)

-- SKYPAKE 14/20(SPI/LPC/SMBUS)

Rev

Rev

Rev

1A

1A

1A

Date:

Date:

Date:

Friday, May 22, 2015

Friday, May 22, 2015

Friday, May 22, 2015

Sheet

Sheet

Sheet

10

10 10

of

of

of

49

49

49

5

4

3

2

1

Friday, May 22, 2015 Friday, May 22, 2015 Friday, May 22, 2015 Sheet Sheet Sheet 10
5 4 3 2 1 11 Functional Strap Definitions D D DESIGN NOTE: WEAK PULL
5
4
3
2
1
11
Functional Strap Definitions
D
D
DESIGN NOTE:
WEAK PULL UP RESISTOR PRESENT ON THIS NET
+3V_DEEP_SUS
No Boot:
ACZ_SPKR
[14,29]
ACZ_SPKR
The signal has a weak internal pull-down.
0
= Enable security measures defined in the Flash
R492
Descriptor.
R458
*4.7K_4
1
*20K/F_4
TOP SWAP OVERRIDE
HIGH - TOP SWAP ENABLE
LOW-DISABLED
HIGH: LPC SELECTED FOR SYSTEM FLASH
WEAK INTERNAL PD
= Disable Flash Descriptor Security (override). This
strap should only be asserted high using external
ACZ_SDOUT
pull-up in manufacturing/debug environments ONLY.
This function is useful when running ITP/XDP.
[14]
ACZ_SDOUT
R219
1K_4
ACZ_SDOUT
[35]
GPIO33_EC
C
+3V_DEEP_SUS
C
No Boot:
The signal has a weak internal pull-down.
0
= Disable Intel ME Crypto Transport Layer Security
(TLS) cipher suite (no confidentiality).
+3V
No Boot:
The signal has a weak internal pull-down.
R95
1
= Enable Intel ME Crypto Transport Layer Security
0 = Disable No Reboot mode.
1K_4
(TLS) cipher suite (with confidentiality). Must be
1 = Enable No Reboot mode
pulled up to support Intel AMT with TLS and Intel
SBA (Small Business Advantage) with TLS.
R144
*4.7K_4
SML0ALERT#
[10]
SML0ALERT#
(PCH will disable the TCO
Timer system reboot feature).
This function is useful when running ITP/XDP.
GPP_B18
[14]
GPP_B18
R94
*20K/F_4
R143
10K_4
+3V_DEEP_SUS
No Boot:
The signal has a weak internal pull-down.
0 = LPC Is selected for EC.
B
1 = eSPI Is selected for EC.
B
R441
GSPI1_MOSI
No Boot:
*10K_4
[14]
GSPI1_MOSI
R140
*20K/F_4
The signal has a weak internal pull-down.
This field determines the destination of accesses to the
BIOS memory range. Also controllable using Boot BIOS
Destination bit (Chipset Configuration Registers: Offset
SML1ALERT#
[10]
SML1ALERT#
3410h:Bit 10). This strap is used in conjunction with Boot
BIOS Destination Selection 0 strap.
Bit 10
Boot BIOS Destination
R440
20K/F_4
0
SPI
1
LPC
A
A
PROJECT : X1A
PROJECT : X1A
PROJECT : X1A
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
Custom
Custom
Custom
16
16
16
-- SKYPAKE 15/20(HDA)
-- SKYPAKE 15/20(HDA)
-- SKYPAKE 15/20(HDA)
1A
1A
1A
NB5
NB5
NB5
Date:
Date:
Date:
Wednesday, May 13, 2015
Wednesday, May 13, 2015
Wednesday, May 13, 2015
Sheet
Sheet
Sheet
11
11
11
of
of
of
49
49
49
5
4
3
2
1
5 4 3 2 1 +3V [2,4,10,11,13,14,15,16,17,18,27,28,29,30,31,32,33,34,35,41,43] +3V_DEEP_SUS [4,10,11,14,15,16,18] ?
5
4
3
2
1
+3V
[2,4,10,11,13,14,15,16,17,18,27,28,29,30,31,32,33,34,35,41,43]
+3V_DEEP_SUS
[4,10,11,14,15,16,18]
?
12
Need apply PN
SKL_ULT
U17H
SSIC / USB3
PCIE/USB3/SATA
H8
USB30_RX1-
USB3_1_RXN
USB30_RX1-
[33]
G8
USB30_RX1+
USB3_1_RXP
USB30_RX1+
[33]
H13
C13
USB30_TX1-
[19]
PEG_RXN0
PCIE1_RXN/USB3_5_RXN
USB3_1_TXN
USB30_TX1-
[33]
USB3.0 (M/B-1)
G13
D13
USB30_TX1+
[19]
PEG_RXP0
PCIE1_RXP/USB3_5_RXP
USB3_1_TXP
USB30_TX1+
[33]
C574
0.22U/10V_4
PEG_TXN0_C
B17
[19]
PEG_TXN0
PCIE1_TXN/USB3_5_TXN
C573
0.22U/10V_4
PEG_TXP0_C
A17
J6
USB30_RX2-
[19]
PEG_TXP0
PCIE1_TXP/USB3_5_TXP
USB3_2_RXN/SSIC_1_RXN
USB30_RX2-
[33]
H6
USB30_RX2+
USB3_2_RXP/SSIC_1_RXP
USB30_RX2+
[33]
D
G11
B13
USB30_TX2-
D
[19]
PEG_RXN1
PCIE2_RXN/USB3_6_RXN
USB3_2_TXN/SSIC_1_TXN
USB30_TX2-
[33]
USB3.0 (3D CAMERA)
F11
A13
USB30_TX2+
[19]
PEG_RXP1
PCIE2_RXP/USB3_6_RXP
USB3_2_TXP/SSIC_1_TXP
USB30_TX2+
[33]
C557
0.22U/10V_4
PEG_TXN1_C
D16
[19]
PEG_TXN1
PCIE2_TXN/USB3_6_TXN
C556
0.22U/10V_4
PEG_TXP1_C
C16
J10
USB30_RX3-
[19]
PEG_TXP1
PCIE2_TXP/USB3_6_TXP
USB3_3_RXN/SSIC_2_RXN
USB30_RX3-
[30]
H10
USB30_RX3+
dGPU
USB3_3_RXP/SSIC_2_RXP
USB30_RX3+
[30]
H16
B15
USB30_TX3-
[19]
PEG_RXN2
PCIE3_RXN
USB3_3_TXN/SSIC_2_TXN
USB30_TX3-
[30]
USB3.0 Small Board
G16
A15
USB30_TX3+
[19]
PEG_RXP2
PCIE3_RXP
USB3_3_TXP/SSIC_2_TXP
USB30_TX3+
[30]
C554
0.22U/10V_4
PEG_TXN2_C
D17
[19]
PEG_TXN2
PCIE3_TXN
C555
0.22U/10V_4
PEG_TXP2_C
C17
E10
[19]
PEG_TXP2
PCIE3_TXP
USB3_4_RXN
F10
USB3_4_RXP
G15
C15
[19]
PEG_RXN3
PCIE4_RXN
USB3_4_TXN
F15
D15
[19]
PEG_RXP3
PCIE4_RXP
USB3_4_TXP
C552
0.22U/10V_4
PEG_TXN3_C
B19
[19]
PEG_TXN3
PCIE4_TXN
C553
0.22U/10V_4
PEG_TXP3_C
A19
AB9
USBP1-
[19]
PEG_TXP3
PCIE4_TXP
USB2N_1
USBP1-
[33]
AB10
USBP1+
Combo USB3.0 MB-1
USB2P_1
USBP1+
[33]
F16
[30]
PCIE_RXN5_CARD
PCIE5_RXN
E16
AD6
USBP2-
[30]
PCIE_RXP5_CARD
PCIE5_RXP
USB2N_2
USBP2-
[30]
C571
0.1U/16V_4
PCIE_TXN5_CARD_C
C19
AD7
USBP2+
Cardreader
Combo USB3.0 Small Board
[30]
PCIE_TXN5_CARD
PCIE5_TXN
USB2P_2
USBP2+
[30]
C572
0.1U/16V_4
PCIE_TXP5_CARD_C
D19
[30]
PCIE_TXP5_CARD
PCIE5_TXP
AH3
USBP3-
USB2N_3
USBP3-
[28]
G18
AJ3
USBP3+
Camera
[34]
PCIE_RXN6_WLAN
PCIE6_RXN
USB2P_3
USBP3+
[28]
F18
[34]
PCIE_RXP6_WLAN
PCIE6_RXP
C569
0.1U/16V_4
PCIE_TXN6_WLAN_C
D20
AD9
WLAN
[34]
PCIE_TXN6_WLAN
PCIE6_TXN
USB2N_4
C570
0.1U/16V_4
PCIE_TXP6_WLAN_C
C20
AD10
[34]
PCIE_TXP6_WLAN
PCIE6_TXP
USB2P_4
F20
AJ1
[34]
SATA_RXN0
PCIE7_RXN/SATA0_RXN
USB2N_5
E20
AJ2
[34]
SATA_RXP0
PCIE7_RXP/SATA0_RXP
USB2P_5
B21
HDD
USB2
[34]
SATA_TXN0
PCIE7_TXN/SATA0_TXN
A21
AF6
USBP6-
[34]
SATA_TXP0
PCIE7_TXP/SATA0_TXP
USB2N_6
USBP6-
[30]
AF7
USBP6+
Combo USB3.0 Small Board
USB2P_6
USBP6+
[30]
C
G21
C
[34]
SATA_RXN1
PCIE8_RXN/SATA1A_RXN
F21
AH1
USBP7-
[34]
SATA_RXP1
PCIE8_RXP/SATA1A_RXP
USB2N_7
USBP7-
[34]
D21
AH2
ODD
USBP7+
WLAN
[34]
SATA_TXN1
PCIE8_TXN/SATA1A_TXN
USB2P_7
USBP7+
[34]
C21
[34]
SATA_TXP1
PCIE8_TXP/SATA1A_TXP
AF8
USBP8-
USB2N_8
USBP8-
[32]
E22
AF9
USBP8+
Touch Screen
[30]
PCIE_RXN9_LAN
PCIE9_RXN
USB2P_8
USBP8+
[32]
E23
[30]
PCIE_RXP9_LAN
PCIE9_RXP
C575
0.1U/16V_4
PCIE_TXN9_LAN_C
B23
AG1
LAN
[30]
PCIE_TXN9_LAN
PCIE9_TXN
USB2N_9
C564
0.1U/16V_4
PCIE_TXP9_LAN_C
A23
AG2
[30]
PCIE_TXP9_LAN
PCIE9_TXP
USB2P_9
F25
AH7
PCIE10_RXN
USB2N_10
E25
AH8
PCIE10_RXP
USB2P_10
D23
PCIE10_TXN
C23
AB6
USB2_COMP R126
+3V
113/F_4
PCIE10_TXP
USB2_COMP
AG3
USB2_ID
PLACE 'R10387' WITHIN 500 MILS
FROM USB2_COMP PIN WITH
TRACE IMPEDANCE LESS THAN 0.5 OHMS
R56
100/F_4
F5
AG4
PCIE_RCOMPN
USB2_VBUSSENSE
E5
GPU_EVENT#
R413
*10K_4
PCIE_RCOMPP
A9
DGPU_HOLD_RST#
GPP_E9/USB2_OC0#
DGPU_HOLD_RST#
[19]
D56
C9
GPU_EVENT#
R584
100K_4
DGPU_HOLD_RST#
R400
*10K_4
[16]
XDP_PRDY#_CPU
PROC_PRDY#
GPP_E10/USB2_OC1#
D61
D9
DGPU_PWR_EN
[16]
XDP_PREQ#_CPU
PROC_PREQ#
GPP_E11/USB2_OC2#
DGPU_PWR_EN
[20,44,46]
R180
10K_4
PIRQA#
BB11
B9
DGPU_PWROK
DGPU_PWR_EN
R73
10K_4
+3V_DEEP_SUS
GPP_A7/PIRQA#
GPP_E12/USB2_OC3#
DGPU_PWROK
[20,35,44,46]
E28
J1
GC6_FB_EN
DGPU_PWROK
R414
10K_4
PCIE11_RXN/SATA1B_RXN
GPP_E4/DEVSLP0
E27
J2
DEVSLP1
PCIE11_RXP/SATA1B_RXP
GPP_E5/DEVSLP1
TP49
D24
J3
OCP_OC#
SATA_LED#
R425
10K_4
PCIE11_TXN/SATA1B_TXN
GPP_E6/DEVSLP2
TP48
C24
PCIE11_TXP/SATA1B_TXP
E30
H2
ACC_LED#
GC6_FB_EN
R424
*10K_4
PCIE12_RXN/SATA2_RXN
GPP_E0/SATAXPCIE0/SATAGP0
ACC_LED#
[34]
F30
H3
ODD_PRSNT#_R
R416
*0_4
PCIE12_RXP/SATA2_RXP
GPP_E1/SATAXPCIE1/SATAGP1
ZERO_ODD_DP#
[34]
A25
G4
SATAGP2
ODD_PRSNT#_R
R418
10K_4
PCIE12_TXN/SATA2_TXN
GPP_E2/SATAXPCIE2/SATAGP2
TP47
B25
PCIE12_TXP/SATA2_TXP
B
H1
SATA_LED#_R
R421
*0_4/S
SATA_LED#
B
GPP_E8/SATALED#
SATA_LED#
[34]
PDC
0423 change to shortpad
+3V_DEEP_SUS
*SKL_ULT
REV = 1
8 OF 20
?
ACC_LED#
R426
10K_4
PCI-E Port Mapping Table
USB3.0 Port Mapping Table
USB2.0 Port Mapping Table
PCI-E Port
Function
CLK RQ Port
Function
USB3.0
Function
USB2.0
Function
PORT-1
USB3.0 MB-1
PORT-1
Cobime USB3.0 MB-1
Port1
dGPU
Port0
Un-used
PORT-2
USB3.0 (3D CAMERA)
PORT-2
Cobime USB3.0 Smaii Board
Port2
dGPU
Port1
CardReader
PORT-3
Cobime USB3.0 Smaii Board
PORT-3
Camera
PORT-4
NC
PORT-4
NC
Port3
dGPU
Port2
WLAN
PORT-5
NC
Port4
dGPU
Port3
LAN
PORT-6
Cobime USB3.0 Smaii Board
PORT-7
WLAN
Port5
CardReader
Port4
VGA
PORT-8
Touch Screen
Port6
WLAN
Port5
Un-used
PORT-9
NC
A
PORT-10
NC
A
Port7
HDD
Port8
ODD
PROJECT : X1A
PROJECT : X1A
PROJECT : X1A
Port9
LAN
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Port10
Un-used
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
Custom
Custom
Custom
17
17 17
-- SKYPAKE 16/20 (PCIE/USB)
-- SKYPAKE 16/20 (PCIE/USB)
-- SKYPAKE 16/20 (PCIE/USB)
1A
1A
1A
NB5
NB5
NB5
Date:
Date:
Date:
Wednesday, May 13, 2015
Wednesday, May 13, 2015
Wednesday, May 13, 2015
Sheet
Sheet
Sheet
12 12
12
of
of
of
49
49
49
5
4
3
2
1
5 4 3 2 1 13 +3V_RTC [4,15,32] +1.8V_DEEP_SUS [9,15,39,46] +3V
5
4
3
2
1
13
+3V_RTC
[4,15,32]
+1.8V_DEEP_SUS
[9,15,39,46]
+3V
[2,4,10,11,12,14,15,16,17,18,27,28,29,30,31,32,33,34,35,41,43]
Need apply PN
?
SKL_ULT
U17J
CLOCK SIGNALS
CLK_GFX_N
D42
[19]
CLK_GFX_N
1222 for Cannonlake-U reserve
CLKOUT_PCIE_N0
CLK_GFX_P
C42
VGA
[19]
CLK_GFX_P
CLKOUT_PCIE_P0
+1.0V_DEEP_SUS
PCIE_CLKREQ_VGA#
AR10
RP3 install for XDP
[20]
PCIE_CLKREQ_VGA#
D
GPP_B5/SRCCLKREQ0#
D
CLK_PCIE_CRN
B42
RP3
[30]
CLK_PCIE_CRN
CLKOUT_PCIE_N1
Cardreader
CLK_PCIE_CRP
A42
F43
CK_XDP_N_R
2
1
R547
*60.4/F_4
XCLK_BIASREF
R393
2.7K/F_4
[30]
CLK_PCIE_CRP
CLKOUT_PCIE_P1
CLKOUT_ITPXDP_N
CK_XDP_N
[16]
PCIE_CLKREQ_CR#
AT7
E43
CK_XDP_P_R
4
3
[30]
PCIE_CLKREQ_CR#
GPP_B6/SRCCLKREQ1#
CLKOUT_ITPXDP_P
CK_XDP_P
[16]
CLK_PCIE_WLANN
D41
BA17
*0_4P2R_4
[34]
CLK_PCIE_WLANN
CLKOUT_PCIE_N2
GPD8/SUSCLK
CLK_PCIE_WLANP
C41
WLAN
[34]
CLK_PCIE_WLANP
CLK_REQ/Strap Pin(CLG)
CLKOUT_PCIE_P2
PCIE_CLKREQ_WLAN#
AT8
E37
XTAL24_IN
[34]
PCIE_CLKREQ_WLAN#
GPP_B7/SRCCLKREQ2#
XTAL24_IN
E35
XTAL24_OUT
XTAL24_OUT
CLK_PCIE_LANN
D40
[30]
CLK_PCIE_LANN
CLKOUT_PCIE_N3
C40
E42
+3V
LAN
CLK_PCIE_LANP
XCLK_BIASREF
[30]
CLK_PCIE_LANP
CLKOUT_PCIE_P3
XCLK_BIASREF
PCIE_CLKREQ_LAN#
AT10
[30]
PCIE_CLKREQ_LAN#
GPP_B8/SRCCLKREQ3#
AM18
RTC_X1
PCIE_CLKREQ_VGA#
R150
10K_4
RTCX1
B40
AM20
RTC_X2
TP103