USB Audio 2.0 MC Hardware Manual (1.6)

USB Audio 2.
0 Reference Design, XS1-L2 Edition Hard-

ware Manual
REV 1.6
If you intend to produce hardware designs based on the

information provided in this document, you should always check
the datasheet of the xCORE device. In the case where the
reference design and datasheet conflict, the datasheet presides.
XMOS datasheets contain additional hardware design
requirements and guidelines that are not covered in this
document, which users of XMOS hardware reference designs must
ensure are followed.
The presence of a third party device in an XMOS hardware
reference design does not make any statement about its general
availability. You must make your own arrangements to ensure
that all components can be sourced in the required volumes.
2010/06/29
XMOS © 2010, All Rights Reserved.
USB Audio 2.0 Reference Design, XS1-L2 Edition Hardware Manual 2/30
1 Introduction
The USB Audio 2.0 Reference Design, XS1-L2 Edition (hereafter "the board") is
a hardware reference design for a multi-channel USB audio interface using the
XMOS XS1-L2 dual-core event-driven processor. It contains a single XS1-L2 device
enabling implementation of a complete USB 2.0 high-speed device compliant with
release 2.0 of the USB Audio Class specification.
A block diagram of the design is shown below:
¼”
Pre-Amp Mono
Word Clock User XSYS 4Mbit GPIO TRS Jack
PLL MCLK
BNC Input LEDs Debug FLASH Header 3.5mm
Pre-Amp Mono
SYNC OUT & I2C GPIO JTAG SPI GPIO TRS Jack
I2C
3.5mm
Passive
13MHz Stereo
MCLK LPF
Oscillator TRS Jack
USB
High Speed 3.5mm
XMOS
ULPI I2S Passive
USB 480Mb/s USB Stereo
LPF
Series B Transciever 24 bit TRS Jack
Receptacle USB3318
Analog In & Out

XS1-L2-124QFN 192kHz
I2C 3.5mm
Audio Passive
Stereo
CODEC LPF
MIDI TRS Jack
CS4244 Passive 3.5mm
1.8V LDO MIDI LPF & Stereo
In/Out HP Amp TRS Jack
MCLK 3.5mm
3.3V DC-DC +3V3D Resync Passive
Stereo
LPF
TRS Jack
+5V IN
L1 Core 3.5mm
1.0V DC-DC Passive
Supply Stereo
LPF
TRS Jack
Optical Coaxial Optical Coaxial
CODEC 3.5mm
RC LP Filter Analogue Digital Digital Digital Digital Passive
Audio Rx Audio Rx Audio Tx Audio Tx Stereo
Supply LPF
TRS Jack
The XS1-L2 event-driven processor communicates with the USB host via a ULPI USB
transceiver at the 480Mb/s high-speed rate. The XS1-L2 controls the streaming of
audio data over the USB connection and direct I2 S interface to the audio CODEC,
digital streams and MIDI communications. Multiple additional functions (e.g.
Mixers/DSP etc.) can be implemented by modifications to the standard software.
REV 1.6
1.1 Feature Overview
Key features of the board are as follows:
· Support for standard sample rates - 32kHz, 44.1kHz, 48kHz, 88.2kHz, 96kHz,
176.4kHz, 192kHz
· Six channels of analogue line level input
· Eight channels of analogue line level output
· Optical and coaxial digital audio input (S/PDIF or ADAT)
· Optical and coaxial digital audio output (S/PDIF or ADAT)
· MIDI input and output
· Word (house) clock input to allow synchronization to an external clock
· Integrated instrument and microphone pre-amplifier
· Integrated headphone amplifier on analogue outputs 1/2
· Powered via USB bus or external 5V source
· XMOS XSYS debug header for easy programming/debug from the host using the
XMOS XTAG2 debug adapter
· Eight LEDs for programmable use
· Expansion header with I2 C and twelve general purpose IOs for programmable
use
· Multiple test-points to allow connection of custom ADC/DAC hardware etc
REV 1.6
1.2 Board Components
The diagram below shows the layout of the main components of the board:
D
C
B
E F
P
G
H
I A O
Q
J
L
M
K
A XS1-L2 Device J 1V0 Core Supply

B Audio CODEC K 13MHz Oscillator
C Headphone Pre-Amp L 4Mb SPI FLASH
D Instrument & Mic Pre-Amp M Power Supply Protection & Fuse
E Audio CODEC Clock Buffers N Case LED Power Connector
F PLL & Clock Distribution O 8 x User Programmable LEDs
G 4V1 Analogue Supply P PLL Auxiliary Output LED
H 3V3 Digital Supply Q USB & Power On LEDs
I USB Transceiver
The rest of this document provides a detailed description of each of the main board
components.
REV 1.6
1.3 Connectors
The diagram below shows the layout of the connectors on the board:
5 6 7 8 9 10 11 12
4
13
3
14
15
2
16
20
1 19 18 17
1 5V DC Power In 11 Analogue 5/6 OUT (Stereo 3.5mm Jack)

2 MIDI Input & Output (Via Gameport) 12 Analogue 7/8 OUT (Stereo 3.5mm Jack)
3 75Ω BNC Word Clock Input 13 Optical Digital Output
4 Instrument IN (Mono 1/4" Jack) 14 Coaxial Digital Output
5 Microphone IN (Mono 3.5mm Jack) 15 Optical Digital Input
6 Analogue 1/2 IN (Stereo 3.5mm Jack) 16 Coaxial Digital Input
7 Analogue 3/4 IN (Stereo 3.5mm Jack) 17 Expansion Header
8 Analogue 5/6 IN (Stereo 3.5mm Jack) 18 XSYS Debug Interface
9 Analogue 1/2 OUT (Stereo 3.5mm Jack) 19 USB B Connector
10 Analogue 3/4 OUT (Stereo 3.5mm Jack) 20 Push Button Power Switch
REV 1.6
2 XS1-L2 Device [A]

The board is based on a single XS1-L2 device in a 124 pin QFN package.
The XS1-L2 consists of a two XCore processors. Each XCore comprises an event-
driven multi-threaded processor with tightly integrated general purpose I/O pins,
64 KBytes of on-chip RAM and 8 KBytes of OTP (One Time Programmable) memory.
XCore processors have time-aware ports that are directly connected to the I/O pins.
Examples of how to write software that interfaces over these ports are provided in
Programming XC on XMOS Devices available from www.xmos.com.
2.1 Clocking [K]
A discrete 13MHz pierce oscillator is used to feed the XS1-L2 reference clock input
and also the USB3318 USB transceiver. The L2 has MODE1 and MODE0 pins wired
to ground which sets the internal XS1-L2 PLL multiplication factor to 30.75. This
results in a default core clock frequency of 399.75MHz and an I/O reference clock
frequency of 99.9375MHz.
2.2 Reset
A supply voltage supervisor connected to the 1V0 core supply is used to provide
a reset to the L2. This ensures the device is reset at power on and also provides
predictable behaviour under brownout conditions. The device can also be reset
over the XSYS debug interface.
2.3 Boot
The boot mode of the XS1-L2 is set by the MODE3 and MODE2 pins which are
connected together on the board.
With MODE3 and MODE2 both high (default), the device will boot from the 4Mb SPI
FLASH on the board. With MODE3 and MODE2 both low, the device will not boot
from SPI FLASH, thus instead allowing boot via JTAG using the XSYS debug link.
To allow automatic boot mode selection based on debug hardware presence the
MODE2 and MODE3 pins are connected to the TRST_N of the debug connector.
Without debug hardware connected to the XSYS interface, the board will boot
from SPI FLASH. With the XTAG2 connected to the XSYS interface, the host can
control the boot mode of the device by way of the TRST_N line. This functionality
is provided purely for developer convenience. A typical production board might
use a jumper or switch for manual boot mode selection if JTAG boot is required.
The MODE4 pin is held low on the board. This causes the second XCore to boot
from a link connected to first XCore, rather than its own SPI FLASH.
3 USB Connector and Transceiver [19 & I]

The board uses a standard USB series B receptacle for USB connectivity.
REV 1.6
The high-speed USB signals are connected to an SMSC® USB3318 USB transceiver
which provides a ULPI connection to XCore 0 of the XS1-L2.
On power-up, a pulldown resistor holds the transceiver in reset until the XS1-L2
is ready to begin USB activity. The USB transceiver reset pin is connected to port
X0P1M of the XS1-L2 in order that it can be controlled by software.
The transceiver uses the 13MHz clock provided by a discrete oscillator which
doubles as the reference clock for the XS1-L2.
4 Audio CODEC [C]

The board is equiped with a 24 bit, 192kHz multi-channel audio CODEC (Cirrus
Logic® CS42448).
The CODEC is configured via an I2 C serial configuration interface with slave address
0x48.
The CODEC can be configured to provide audio clocks (master mode) or with all
clocks being inputs (slave mode).
The CODEC has seperate LRCLK and SCLK I/Os for ADC and DAC. These are both
connected to a single I/O pin on the XCore. Clock buffers are provided for SCLK
and LRCLK I/Os to remove any potential contention issues.
The control pin (CODEC_MODE) for the buffers is mapped to bit 1 of port X1P4A
on the XS1-L2.
CODEC_MODE Clock Mode

0 Clocks Connected
1 Clocks Disconnected
When using the codec in slave mode the clocks should be connected together.
The CODEC has three internal modes depending on the sampling rate used. These
change the oversampling ratio used internally in the CODEC. The three modes are
shown below:
CODEC mode CODEC sample rate range

Single speed 4-50kHz
Double speed 50-100kHz
Quad speed 100-200kHz
The reset input to the CODEC is mapped to bit 3 of port X1P4A on the XS1-L2.
The interrupt output from the CODEC is mapped to bit 3 of port X1P4B on the
XS1-L2.
REV 1.6
4.1 Analogue Audio I/O [4 - 12]
3.5mm Tip Ring Sleeve (TRS) audio jacks are provided for stereo audio inputs and
outputs. The layout of the audio jacks is shown in the connector diagram of the
board.
A simple passive AC-coupling and low pass filter circuit is used on input and output.
The circuit is configured such that the audio output will produce approximately
0.94VRMS (-0.54dBV) for a digital full scale signal. Due to the output coupling
capacitors, the output impedance falls with frequency and is approximately 1kΩ @
35Hz falling to 576Ω @ 1kHz.
The input circuit contains an attenuator such that a 1.62VRMS (+4.2dBV) signal will
produce a full scale digital output. The input impedance is approximately 9kΩ.
The CODEC microphone and instrument inputs are AC-coupled to low noise op-amp
pre-amplifiers before being AC-coupled onto the CODEC inputs. These are set with
gains of -1 and -10 for the instrument and microphone inputs respectively.
A 3.5mm Tip Ring Sleeve (TRS) audio jack is provided for the stereo headphone
out, which is powered by a 75mW TI TPA152 stereo headphone amplifier. This is
the a capable of driving a minimum load of 32Ω. It is configured with a gain of -1.
5 Digital Audio Output [13 & 14]

Optical and coaxial digital audio transmitters are used to provide digital audio
output in formats such as IEC60958 consumer mode (S/PDIF) and ADAT. The
signals are generated from two 1-bit ports on the XS1-L2 as defined in the port
map.
The data streams from the XS1-L2 are re-clocked using the external master clock
to synchronise the data into the audio clock domain. This is achieved using simple
external D-type flip-flops.
The optical output uses a TOSLINK optical connector with an integrated LED and
differential driving circuit. The coaxial output uses an RCA connector and is
isolated via a transformer.
6 Digital Audio Input [15 & 16]

Digital audio input is provided to allow formats such as IEC60958 consumer
mode (S/PDIF) or ADAT to be connected to the device via either optical or coaxial
mediums.
The optical input uses a TOSLINK optical connector with an integrated photodiode
and receiver circuit. The coaxial input uses an RCA connector and is AC-coupled
into a 75Ω terminator.
This gives a signal level of 0.5Vp−p , which is fed into a differential line receiver.
The input signals are fed into two 1-bit ports on the processor as defined in the
port map.
REV 1.6
7 MIDI I/O [2]

Musical Instrument Digital Interface input and output is provided on the board via
a standard Gameport connector. The signals are buffered using 5V line drivers and
are then connected to 1-bit ports on the XS1-L2, via a 5V to 3.3V buffer.
10KΩ pull ups are placed on the MIDI IN signal from the connector and on the
MIDI OUT signal from the XCore. These stop glitches on startup and when no MIDI
devices are connected to the board.
The MIDI input and output signals are connected to the XS1-L2 as follows:
Port Signal
X1P1P MIDI_IN
X1P1O MIDI_OUT
Standard MIDI devices (using DIN 5/180◦ connectors) are attached using a Game-
port to dual DIN MIDI cable. This is not included in the kit, but are easily purchased
from other suppliers.
REV 1.6
8 Audio Clocking [3 & K]

In order to accommodate a multitude of clocking options, the low-jitter master
clock (e.g. 256 x fs), is generated locally using a fractional-N frequency multiplier
PLL chip.
The source for the PLL is either the SYNC_OUT signal from the XS1-L2 or the word
clock input as controlled by the SYNC_SEL signal.
The SYNC_SEL signal is mapped to bit 0 of port X1P4A on the XS1-L2 as shown in
the port map.
The behaviour of this select signal is as follows:
SYNC_SEL PLL clock source

0 XS1-L2 SYNC_OUT
1 Word Clock Input
The Cirrus Logic CS2300-CP PLL chip generates a low-jitter output of between
6-75MHz from any 50Hz-30MHz input clock.
A variety of clock sources can be used, including:
· Local crystal oscillator, via XCore clock block (which divides 13MHz down to the SYNC_OUT
signal).
· S/PDIF software recovered clock (which then drives the SYNC_OUT signal).
· Word clock input.
The SYNC_OUT signal is connected to both cores of the XS1-L2, but a DNF resistor
(R102) normally only allows XCore 1 to output the signal. Fit a 0R 0603 resistor to
enable XCore 0 to output the signal.
The audio master clock is connected to both cores of the XS1-L2 on ports X0P1L
and X1P1L, to allow the audio output streams on that XCore to be synchronized.
The CS2300-CP is configured over the I2 C bus (shared with the CODEC) at slave
address 0x47.
The CS2300-CP auxiliary output drives an LED to indicate the state of the signal.
For example, this could show if the PLL is locked or not.
A 75Ω terminated BNC input is provided for an external word clock ("house clock")
input. The input accepts a 0-5V (5Vp−p , 2.5V offset) signal, which is low-pass
filtered to remove high frequency components, and schmitt triggered to remove
problems with noise and non-monotonic edges.
This signal is also fed to a 1-bit port on the XS1-L2. This allows the application
code to detect if a word clock input signal is present.
REV 1.6
9 SPI Flash Memory [L]

A 4Mbit FLASH memory device is provided, connected via a standard Serial Periph-
eral Interface (SPI).
The FLASH is connected to four 1-bit ports as shown in the table below. These are
the standard ports the processor will try to boot from in SPI boot mode.
Port SPI Signal

X0P1A MISO
X0P1B SS
X0P1C CLK
X0P1D MOSI
The XMOS development tools include the XFLASH utility for programming compiled
programs into the flash memory via the XS1-L2. Software may also access the
FLASH memory at run-time by interfacing with the above ports.
REV 1.6
10 XSYS Interface [18]

A standard XMOS XSYS interface is provided to allow host debug of the board via
JTAG.
An XTAG2 USB debug adapter can be plugged into this port to allow running/de-
bugging code, programming the FLASH memory via the XS1-L2 and selection of
boot mode. It is not recommended to use an original (FTDI based) XTAG with the
L2 device, as this is not as fast as the XTAG2 and can have signal drive strength
issues.
A 20-way IDC header is used as the physical connector and the pinout of this is
shown below:
Signal Pin Description

TRST_N 3 JTAG Test Reset. Active low
TMS 7 JTAG Test Mode Select
TCK 9 JTAG Test Clock
TD1 5 JTAG Test Data. From debug adapter to XS1-L2
TD2 13 JTAG Test Data. From XS1-L2 to debug adapter
SRST_N 15 System Reset. Active low. Resets XS1-L2 device
DEBUG 11 XS1-L2 DEBUG Interrupt line
XMOS-LINK 6, 10, 14, 18 This is a 2-wire XMOS-Link for advanced debug
GND 4, 8, 12, 16, 20 Ground
NC 1, 2, 17, 19 These pins are not connected
As discussed in the Boot section the XS1-L2 MODE2 and MODE3 pins are connected
to the TRST_N signal.
REV 1.6
11 User LEDs [I]

The board provides eight user LEDs that can be driven by software. These are
marked on the board as LED 0 though to LED 7. The LEDs are connected to port
X1P8B, the bit mapping is shown in the table below:
Port LED
X1P8B0 LED 0
X1P8B1 LED 1
X1P8B2 LED 2
X1P8B3 LED 3
X1P8B4 LED 4
X1P8B5 LED 5
X1P8B6 LED 6
X1P8B7 LED 7
The LED connections are also shown in the port map. Setting the relevant bit high
will turn the LED on.
REV 1.6
12 Expansion Header [17]

The board provides a general purpose input/output expansion header to allow
interfacing to custom boards. For example, this could be an I2 C display, eight LEDs
and four buttons to make a user interface.
The header contains the following:
· +3V3 power pin.
· Ground pin.
· I2 C bus (as used to configure the PLL and CODEC).
· One 4-bit GPIO port (X1P4F).
· One 8-bit GPIO port, which is also shared with the LED outputs (X1P8B).
A 16-way IDC header is used as the physical connector and the pinout of this is
shown below:
Pin Port Signal

1 NA +3V3
2 X1P8B7 LED_7
3 NA GND
4 X1P8B6 LED_6
5 X1P1C0 I2C_SDA
6 X1P8B5 LED_5
7 X1P1D0 I2C_SCL
8 X1P8B4 LED_4
9 X1P4F0 GPIO_0
10 X1P8B3 LED_3
11 X1P4F1 GPIO_1
12 X1P8B2 LED_2
13 X1P4F2 GPIO_2
14 X1P8B1 LED_1
15 X1P4F3 GPIO_3
16 X1P8B0 LED_0
Each IO pin can source or sink a maximum of 4mA.
REV 1.6
13 Power [1, G, H, J, M & Q]

The board is powered from the onboard +5V DC power connector or from the USB
bus. Note that the board has not been designed as a bus-powered device due to
pre-enumeration current limits.
The two different power supplies are "ORd" together using Schottky diodes with a
maximum voltage drop of 0.34V. A 750mA resettable polyfuse and reverse polarity
protection, via a bidirectional zener diode, is provided. Ferrite beads are used on
the +5V VBus and +5V DC power input to prevent switching noise propagating
down the USB and power cables.
A latching push-button power switch is fitted to the board that activates a p-channel
MOSFET (which has an Rds(on) of approximately 80mΩ). A soft start circuit is
included to limit the inrush current.
When powered from the USB bus all the power used by the board is derived
from the nominally +5V VBus supply from the USB connector. The board will use
approximately 300mA when fully configured and operating.
The required core and IO voltages for the XS1-L2 are derived from 5V as follows:
· A low cost 1.5A buck switching regulator is used to generate the 1.0V core
supply for the XS1-L2.
· A low cost 600mA buck switching regulator is used to generate the global 3.3V
supply.
Switching regulators are used on these power supplies due to their high efficiency.
The power supplies are sequenced using a 3.0V voltage supervisor on the 3.3V
supply output, to drive the enable input on the 1.0V supply. This makes sure
that the 3.3V supply is up and stable, before the 1.0V supply comes up and also
provides predictable behaviour under brownout conditions, by causing a reset if
the supplies droop significantly.
A simple low drop out (LDO) linear regulator is used to generate the 1.8V supply
required by the USB3318 USB transceiver.
A low noise LDO regulator is used to generate the analogue supply for the Audio
CODEC. The CODEC offers higher audio performance at higher supply voltages
so the voltage for this supply is set at 4.1V. This allows some headroom between
the 4.5V minimum VBus voltage and the approx 350mV dropout of the LDO + RC
pre-filter.
When the board is correctly connected to a USB source the USB VBUS Power LED is
illuminated.
When the board is powered on the Power LED is illuminated.
REV 1.6
14 Printed Circuit Board

The PCB is a 1.6mm four layer design in a XMOS XS1-G Development Kit form factor
with dimensions of 180 x 120mm. It is made from FR4 (εr = 4.5) material and
finished in immersion gold. The mounting holes are 3.2mm in diameter.
Signal stack up is as follows:
· Top signal
· Ground plane
· Power plane
· Bottom signal
REV 1.6
15 Test Points
15.1 Test Points by ID
Test Point Port Signal

TP1 NA +5V
TP2 NA +4V1A
TP3 NA +3V3
TP4 NA +1V8
TP5 NA +1V0
TP6 NA OSC_13M
TP8 NA PLL_WCLK
TP9 NA VBUS
TP10 X0P1J0 OPTICAL_RX
TP11 X1P1N0 DAC_SD4
TP12 X1P1H0 DAC_SD3
TP13 X1P1F0 DAC_SD2
TP14 X1P1M0 DAC_SD1
TP15 X1P1I0 CODEC_SCLK
TP16 X1P1E0 CODEC_LRCK
TP17 X1P1D0 I2C_SCL
TP18 X1P1C0 I2C_SDA
TP19 X1P4A3 CODEC_RSTN
TP20 X1P1B0 ADC_SD3
TP21 X1P1A0 ADC_SD2
TP22 X1P1G0 ADC_SD1
TP23 X1P4B3 CODEC_INT
TP24 X0P1L0 & X1P1L0 XCORE_MCLK
TP25 X0P1C0 & X1P4E0 SYNC_OUT
TP26 X1P4A0 SYNC_SEL
TP27 X1P1K0 COAXIAL_TX
TP28 X1P4A1 CODEC_MODE
TP29 X1P4B1 PLL_LOCK
TP30 X0P1K0 COAXIAL_RX
TP31 X1P1J0 OPTICAL_TX
TP34 X1P1O0 MIDI_OUT
TP35 X1P1P0 MIDI_IN
REV 1.6
15.2 Test Points by Signal
15.2.1 Power
Signal Port Test Point

+1V0 NA TP5
+1V8 NA TP4
+3V3 NA TP3
+4V1A NA TP2
+5V NA TP1
VBUS NA TP9
15.2.2 XS1-L2 System

OSC_13M NA TP6
PLL_LOCK X1P4B1 TP29
15.2.3 Audio Clocking

SYNC_SEL X1P4A0 TP26
PLL_WCLK NA TP8
SYNC_OUT X0P1C0 * & X1P4E0 TP25
XCORE_MCLK X0P1L0 & X1P1L0 TP24
* Enabled via DNF resistor R102.
15.2.4 Codec Audio

ADC_SD1 X1P1G0 TP22
ADC_SD2 X1P1A0 TP21
ADC_SD3 X1P1B0 TP20
DAC_SD1 X1P1M0 TP14
DAC_SD2 X1P1F0 TP13
DAC_SD3 X1P1H0 TP12
DAC_SD4 X1P1N0 TP11
CODEC_LRCLK X1P1E0 TP16
CODEC_SCLK X1P1I0 TP15
REV 1.6
15.2.5 Codec Config/Status

CODEC_INT X1P4B3 TP23
CODEC_MODE X1P4A1 TP28
CODEC_RST X1P4A3 TP19
I2C_SCL X1P1D0 TP17
I2C_SDA X1P1C0 TP18
15.2.6 Digital Audio

OPTICAL_RX X0P1J0 TP10
OPTICAL_TX X1P1J0 TP31
COAXIAL_RX X0P1K0 TP30
COAXIAL_TX X1P1K0 TP27
15.2.7 MIDI
MIDI_OUT X1P1O0 TP34

MIDI_IN X1P1P0 TP35
Unmarked test points are connected to ground.
REV 1.6
16 Port Map
The table below provides a full description of the port to signal mappings used on
the board.
Pin Port XCore

1b 4b 8b 16b 0 1
XD0 P1A0 SPI_MISO ADC_SD2
XD1 P1B0 SPI_SS ADC_SD3
XD2 P4A0 P8A0 P16A0 SYNC_SEL
NA
XD3 P4A1 P8A1 P16A1 CODEC_MODE
XD4 P4B0 P8A2 P16A2 NA
XD5 P4B1 P8A3 P16A3 PLL_LOCK
XSYS Link
XD6 P4B2 P8A4 P16A4 WORD_CLK
XD7 P4B3 P8A5 P16A5 CODEC_INT
XD8 P4A2 P8A6 P16A6 NA
NA
XD9 P4A3 P8A7 P16A7 CODEC_RST_N
XD10 P1C0 SPI_CLK / SYNC_OUT * I2C_SDA
XD11 P1D0 SPI_MOSI I2C_SCL
XD12 P1E0 ULPI_STP CODEC_LRCK
XD13 P1F0 ULPI_NXT DAC_SD2
XD14 P4C0 P8B0 P16A8
XD15 P4C1 P8B1 P16A9
XD16 P4D0 P8B2 P16A10
XD17 P4D1 P8B3 P16A11
ULPI_DATA[0:7] LEDS[0:7]
XD18 P4D2 P8B4 P16A12
XD19 P4D3 P8B5 P16A13
XD20 P4C2 P8B6 P16A14
XD21 P4C3 P8B7 P16A15
XD22 P1G0 ULPI_DIR ADC_SD1
XD23 P1H0 ULPI_CLK DAC_SD3
XD24 P1I0 WORD_CLK CODEC_SCLK
XD25 P1J0 OPTICAL_RX OPTICAL_TX
XD26 P4E0 P8C0 P16B0 SYNC_OUT
XD27 P4E1 P8C1 P16B1 NA
XD28 P4F0 P8C2 P16B2
NA GPIO[0:3]
XD32 P4E2 P8C6 P16B6
NA
XD33 P4E3 P8C7 P16B7
XD34 P1K0 COAXIAL_RX COAXIAL_TX
XD35 P1L0 MCLK_IN MCLK_IN
XD36 P1M0 P8D0 P16B8 ULPI_RST DAC_SD1
XD37 P1N0 P8D1 P16B9 DAC_SD4
XD38 P1O0 P8D2 P16B10 MIDI_OUT
XD39 P1P0 P8D3 P16B11 MIDI_IN
XD40 P8D4 P16B12 NA
XD41 P8D5 P16B13
NA
XD42 P8D6 P16B14
XD43 P8D7 P16B15
* Enabled via DNF resistor R102.
REV 1.6
17
REV 1.6
Schematics
CODEC XS1_CORE1 +5V +4V1A
DAC_SD4 ADC_SD3 DAC_SD4 ADC_SD3 FM1

DAC_SD4 ADC_SD3 TP11 DAC_SD4 ADC_SD3 TP20 TP1
DAC_SD3 ADC_SD2 DAC_SD3 ADC_SD2
DAC_SD3 ADC_SD2 TP12 DAC_SD3 ADC_SD2 TP21
DAC_SD2 ADC_SD1 DAC_SD2 ADC_SD1
DAC_SD1 DAC_SD2 ADC_SD1 TP13 DAC_SD1 DAC_SD2 ADC_SD1 TP22 TP2
DAC_SD1 TP14 DAC_SD1 PLL_LOCK
PLL_LOCK TP29
CODEC_SCLK CODEC_SCLK SYNC_SEL +3V3 +1V8
SCLK TP15 CODEC_SCLK SYNC_SEL TP26
CODEC_LRCK CODEC_LRCK SYNC_OUT
LRCK TP16 CODEC_LRCK SYNC_OUT TP25
WORD_CLK FM2
CODEC_MCLK XCORE_MCLK WORD_CLK
MCLK TP24 MCLK_IN TP3
OPTICAL_TX
OPTICAL_TX TP31
I2C_SCL I2C_SCL COAXIAL_TX
I2C_SCL TP17 I2C_SCL COAXIAL_TX TP27 TP4
I2C_SDA I2C_SDA
I2C_SDA TP18 I2C_SDA
CODEC_MODE CODEC_MODE
CODEC_RSTN MODE CODEC_INT CODEC_RSTN CODEC_MODE CODEC_INT TP28 +1V0 VBUS
RST_N INT TP19 CODEC_RSTN CODEC_INT TP23
FM3
TP5
TP9
DIGITAL_IO CLOCKING XS1_CORE0 XS1_SYSTEM FM4

OSC_13M
TP6
DIGI_MCLK WORD_CLK
MCLK WORD_CLK SYNC_OUT WORD_CLK XL_UP1 XL_UP1
OPTICAL_RX SYNC_OUT XCORE_MCLK SYNC_OUT XL_UP0 XL_UP0 PLL_WCLK
OPTICAL_RX XCORE_MCLK MCLK_IN XL_DN0 XL_DN0 TP8
COAXIAL_RX
COAXIAL_RX DIGI_MCLK OPTICAL_RX XL_DN1 XL_DN1 FM5
OPTICAL_TX DIGI_MCLK CODEC_MCLK COAXIAL_RX OPTICAL_RX OSC_13M
COAXIAL_TX OPTICAL_TX CODEC_MCLK COAXIAL_RX OSC_13M CLK_13M OPTICAL_RX
COAXIAL_TX TP10
I2C_SCL
I2C_SCL I2C_SDA COAXIAL_RX
I2C_SDA TP30
SYNC_SEL
SYNC_SEL PLL_LOCK
PLL_LOCK FM6
PLL_WCLK
PLL_WCLK
SUB SHEETS & CODEC TPS FIDUCIALS & TPS
+5V
1K
100N
C5
VBUS POWER_ON_N
R2 +5V VBUS +5V
MBR120VLSFT
R3
1 NC
10K
1
G
D2
J1 SW1 2 POWER_ON_N JP1 D8 D13
PJ-014D-SMT FB2 MBR120VLSFT F1 PN12SHNA03QE 1 GREEN GREEN
1A 3 2
S2
D3
1B
3 330R D3 0.75A Q1
C4 1700mA C3
2 NTR4101P
1K
1K
R30
R91
SMBJ5.0A D1 MECH1
100N 100N SWITCH_CAP
USB Audio 2.0 Reference Design, XS1-L2 Edition Hardware Manual
5V DC POWER INPUT, PROTECTION, FILTERING & SWITCH POWER LEDS
MTH4
PTH_M3 +5V
TP7 TP38 TP45 TP50 TP55
MTH3
PTH_M3
TP33 TP42 TP47 TP52 TP57 Copyright (c) 2009 XMOS Ltd.
MTH2
PTH_M3
10K
R104
PROJECT NAME
MTH1
PTH_M3
XR-USB-AUDIO-2.0-MC
SIZE SHEET NAME REV
GROUND TEST POINTS MOUNTING HOLES BLEEDER R A3 TOP_LEVEL 1V2

DATE JUN 29 2010 SHEET 1 OF 1
=
21/30
REV 1.6
HEADPHONE AMP
+3V3 R50 R15 R12 R31
C52
4U7
C61
100U
I2C Chip Address is 1001000X (X is R/nW bit)
470R 20K 20K 33R
C31
1K
R13
R17
R47 2N2
4U7
C51
20K
4K7 +4V1A J8
C32
SJ-3524-SMT
C25 C14 C15 C16
U6 2
R48
4K7
J12 2N2 NC 10
SJ-3524-SMT 100N 100N 100N 2 6 3
4U7 MUTE VDD
2 1
10 NC 8 1
3 IN1- VO1
R51 R14 R29
C54
4U7
C64
100U
1 4 5
IN2- VO2
470R 20K 3 7 33R
C33 BYPASS GND
R32
4U7
C41
1K
C13 R11
20K
R10
20K
R16
2N2 TPA152
4K7 +4V1A
C40
1U
R33
4K7
2N2
C26 C17 C18 R52

C55
4U7
R36
4U7
C46
+4V1A +4V1A
470R
4K7 4U7 100N 100N R19 C34
C28
10K 2N2
R37
4K7
C21 C50
J6 2N2 J9
SJ-3524-SMT SJ-3524-SMT
2 100N 4U7 2
10 NC NC 10
3 3
1 1
+3V3 +4V1A R53

C56
4U7
R35
4U7
C47
470R
4K7 R20 C35
C27
10K 2N2
R34
4K7
U3 CS42448
4
8
6
44
2N2
VLC
VLS
46 26
VD_624
45AIN1P AOUT1P25 NC
VD_24
VA_4453
VA_53
AIN1N AOUT1N
48 27
47AIN2P AOUT2P28 NC
AIN2N AOUT2N
R55
C58
4U7
R39 50 30
4U7
C49
49AIN3P AOUT3P29 NC
AIN3N AOUT3N 470R
4K7 R22 C37
52 31
C29
51AIN4P AOUT4P32 NC
AIN4N AOUT4N
10K 2N2
R38
4K7
J7 2N2 58 34 J10
SJ-3524-SMT AIN5B 57AIN5P/AIN5A AOUT5P33 NC SJ-3524-SMT
2 AIN5N/AIN5B AOUT5N 2
10 NC 60 36 NC 10
C42 C43 C44 C45
3 AIN6B 59AIN6P/AIN6A AOUT6P37 NC 3
1 AIN6N/AIN6B AOUT6N 1
4U7 4U7 4U7 4U7 R49 39
AOUT7P38 NC
AOUT7N R54
C57
4U7
R40 4K7
4U7
C48
22 40
NC 21AUX_SDIN AOUT8P41 NC 470R
4K7 AOUT8N R21 C36
NC 20AUX_SCLK
C30 AUX_LRCK
11 10K 2N2
R41
4K7
ADC_SD3 ADC_SDOUT3
2N2 ADC_SD2 12
13ADC_SDOUT2
ADC_SD1 ADC_SCLK 9ADC_SDOUT1
+3V3 +3V3 ADC_LRCK 5ADC_SCLK
ADC_LRCK
DAC_SD4 14
DAC_SD4 DAC_SD3 15DAC_SDIN4
DAC_SD3 DAC_SD2 16DAC_SDIN3
DAC_SD2 R56
C59
4U7
DAC_SD1 17DAC_SDIN2
DAC_SD1 18DAC_SDIN1 35 NC
R45
4K7
R44
4K7
SCLK 19DAC_SCLK MUTEC 470R
LRCK DAC_LRCK R23 C38
10
MCLK MCLK 43
VQ 10K 2N2
I2C_SCL 63 J11
I2C_SCL I2C_SDA 64SCL/CCLK SJ-3524-SMT
I2C_SDA 2SDA/CDOUT 2
1AD1/CDIN 55 NC 10
AD0/CS_N FILTP_ADC 3
61 1
INT INT
+3V3 3 54 R57
RST_N RST_N FILTP_DAC
C60
4U7
DGND_62
AGND_56
470R
7
23DGND_7
62DGND_23
42
56AGND_42
C22 C62 C23 C63 C24 C53 R24 C39
R42
4K7
R43
4K7
R46
4K7
U5 +3V3 100N 100U 100N 100U 100N 4U7 10K 2N2
R18
10K
1 5
MODE OE_N VCC
2 4
SCLK ADC_SCLK
A Y
3
+3V3 +3V3
GND
NC7SZ125 VREF = 1.225V
VOUT = 1.225 * (1 + 10K/4K3) = 4.07V

C20 C19
+5V U21 +4V1A
100N 100N TPS73001
FB1 R1
1 6
U4 +3V3 IN OUT
470R 1R 3 5
C2 500mA C1 C107 EN FB C108 C110
1 5 PREAMP
2 4
R26
10K
OE_N VCC GND NR

100N 100N 4U7 100P 2U2
AIN6B
2 4 INST_IN
LRCK ADC_LRCK AIN5B
A Y MIC_IN
C109
Copyright (c) 2009 XMOS Ltd.
3
R27
4K3
GND 100N
PROJECT NAME
NC7SZ125
XR-USB-AUDIO-2.0-MC
SIZE SHEET NAME REV
ADC CLK BUFFERS 4V1A LDO REGULATOR PREAMPS A2 CODEC 1V2

=
22/30
REV 1.6
+3V3
U8
USB3318
X0D14 16 3 +1V8 VBUS
X0D15 15DATA0 VBAT4
X0D16 14DATA1 VDD3317 +3V3
U9 X0D17 13DATA2 VDDIO
XS1_L2_124LGA X0D18 11DATA3 21 1700mA
VDD18
C75
100N
X0D19 10DATA4 R68 330R

A15 X0D0 X0D20 9DATA5 2 J15
X0D0A16 X0D1 X0D21 8DATA6 VBUS
X0D1A5 NC DATA7 1K 1 +3V3
FB5
X0D2A6 NC X0D12 20 5 DM 2VBUS U10
R69
10K
X0D3A7 X0D4 X0D13 18STP DM6 DP 3DM AT25DF041A

X0D4A8 X0D5 X0D22 19NXT DP 4DP
X0D5A9 X0D6 DIR GND X0D11 5 8
X0D6A10 X0D7 X0D23 12 1 NC 5 SI VCC
X0D7A11 NC CLKOUT ID7 NC 6S1 X0D10 6
X0D8A12 NC CPEN S2 SCK 2 X0D0
X0D9A13 X0D10 24 23 3 SO
X0D10A14 X0D11 RBIAS REFCLK OSC_13M USB_B 7 WP_N
X0D11A55 X0D12 25 22 X0D36 X0D1 1 HOLD_N 4
X0D12A57 X0D13 GND RESETB CS_N GND
X0D13A58 X0D14
R67
8K06
X0D14A59 X0D15 4MBIT
X0D15A60 C74
X0D16
10K
R70
X0D16A61 X0D17
DNP
R75
X0D17A63 X0D18
X0D18A64 10N
X0D19
X0D19A65 X0D20
X0D20A66 X0D21
X0D21A56 X0D22
X0D22A62 X0D23
X0D23A54
X0D24A67 WORD_CLK
X0D25B38 NC OPTICAL_RX
X0D26B39 NC
IO_XCORE0
X0D27B40 NC
X0D28B41 NC
X0D29B44 NC
X0D30B45 NC
X0D31B46
X0D32B47
NC USB PHY SPI BOOT FLASH
NC
X0D33A4
X0D34A3 COAXIAL_RX
X0D35B48 X0D36 MCLK_IN
X0D36B49 NC
X0D37B50 NC
X0D38B51 NC
X0D39B52 NC
X0D40B53 NC
X0D41B54 NC
X0D42B55 NC
X0D43
R71
+5V U11 +1V8 +3V3 VBUS X0D4
NCP699SN18 XL_UP1
33R
R102
X0D10 1 5
SYNC_OUT VIN VOUT R72
X0D5
DNP XL_UP0
C78 C80 C79 C76 C77 C73 33R
3 4 NC R73
EN NC X0D6
100N 2U2 100N 100N 100N 1U XL_DN0
GND
33R
2
R74
X0D7
XL_DN1
33R
XCORE 1V8 LDO & DECOUPLING XSYS XMOS-LINK
PROJECT NAME
XR-USB-AUDIO-2.0-MC
SIZE SHEET NAME REV
A3 XS1_XCORE0 1V2
=
23/30
REV 1.6
+5V +1V0 +1V0 +3V3 +3V3 +1V0 +3V3
U15 U9
FAN2012 XS1_L2_124LGA
L2 U12
4 3 A2 B32 NC7SZU04
5PVIN SW A17VDDIO_A2 OTP_VDDIO 5
VIN 3U3
A36VDDIO_A17 B4 2 4
C92 C112
3V3_PG 6 A51VDDIO_A36 PCU_VDDIOB5
C96 EN PCU_VDD
B1VDDIO_A51 3
R77
1K8
2 10U 10U B14VDDIO_B1 B3 NC
10U 7PGND 1 B29VDDIO_B14 PCU_GATEB2 NC
AGND FB B42VDDIO_B29 PCU_WAKEB6 CLK_13M
R82
2R2
VDDIO_B42 PCU_CLK
A19 A38
A34VDD_A19 PLL_AVDDA37
R76
A53VDD_A34 PLL_AGND CLK_13M
POWER
R81
6K8
A68VDD_A53 A1 C81 CLK_13M
B15VDD_A68 GND_A1A18 2M2
B28VDD_B15 GND_A18A52
B43VDD_B28 GND_A52 1U
R84
470R
B56VDD_B43 PAD X1
VDD_B56 GND_PAD +3V3
13M
C99 ABLS2 C98 C83
33P 33P 100N

+3V3 U22 +5V
NCP303LSN30 U9
10K XS1_L2_124LGA
2 1 3V3_PG
INPUT RST_OUT B33
NC 5 R101 B34MODE0
CD TRST_N B35MODE1
3 4 NC B36MODE2
GND NC A35MODE3
MODE4
DEBUG B37
RST_N B8DEBUG
CLK_13M B7RST_N
CONFIG
CLK 13MHz OSCILLATOR
TDO B9
TDI B12TDO
TMS B11TDI
TCK B10TMS
TRST_N B13TCK
TRST_N
+5V +3V3
U14
NCP1521B +5V NC, So Cannot Be Powered By XTAG2
L1
1 5 J16
VIN LX NC 1 2 NC
2U2
+3V3 +1V0 +3V3 TRST_N 3 4
C95 C82 C97
TDI 5 6 XL_UP1
3 4 TMS 7 8 XL_UP1
R78
6K8
EN FB TCK 9 10 XL_UP0
4U7 330P 10U 10K XL_UP0
DEBUG 11 12
GND
2
TDO 13 14 XL_DN0
C91 C90 C88 C89 C94 C86 C87 C84 C85 C93 R80 XL_DN0
RST_N 15 16
NC 17 18 XL_DN1
NC 19 20 XL_DN1
100N 100N 100N 100N 4U7 100N 100N 100N 100N 4U7
R83
1K5
HEADER_RA
POWER SUPPLIES SYSTEM SERVICES & DECOUPLING XSYS HEADER
+3V3 +3V3 +1V0

U13
NC7WZ07 47K
U23
5 NCP303LSN09 Copyright (c) 2009 XMOS Ltd.
VCC R79
RST_N 6 1 1V0_PG 1 2
Y1 A1 RST_OUT INPUT PROJECT NAME
C111
10N
TRST_N 4 3 5
Y2 A2 CD
2
GND
NC 4
NC GND
3 XR-USB-AUDIO-2.0-MC
SIZE SHEET NAME REV
1V0 RESET SUPERVISOR A3 XS1_SYSTEM 1V2

=
24/30
REV 1.6
+3V3
U17
I2C CHIP ADDRESS = 1001110X
SYNC_SEL 6 5 +3V3 +3V3
SYNC_SEL S VCC +3V3
SYNC_OUT 3 U16 U18
SYNC_OUT I0 0
4 5 1 8
Q CLK_IN VD VCC D15
R90
PLL_WCLK 1 1
10 3 1 7 33R GREEN
I1 I2C_SDA 9SDA/CDIN CLK_OUT 1A 1Y DIGI_MCLK
I2C_SCL R89
2 8SCL/CCLK 4 3 5 33R
GND AD0/CS_N AUX_OUT PLL_LOCK 2A 2Y CODEC_MCLK
R88
6 6 2 33R
1K
3A 3Y XCORE_MCLK
R103
NC7SZ157 7FILTP 2
FILTN GND 4
C103 GND PLL_LOCK
CS2300-CP
100N NC7NZ34
PLL, INPUT SELECTION, OUTPUT BUFFERING & LOCK LED
R28
+3V3
1K
C100
100N
BAV99 +3V3
Diode drop on supply to approx. 2V5 makes switching point more central 3 D4
U19 2 NC
Signal: 2.5V p-p LP -3dB Point: 7.2MHz C104 C102 C101
5
VCC
R86
J17 2 1 6 WORD_CLK 100N 100N 100N
5-1634513-1 A1 Y1 R87 33R WORD_CLK
1K 3 4 PLL_WCLK
1A A2 Y2 R25 33R PLL_WCLK
C105
1B 2
1C GND
R85
75R
1D 22P
NC7WZ17
EXTERNAL WORD CLOCK INPUT DECOUPLING
PROJECT NAME
XR-USB-AUDIO-2.0-MC
SIZE SHEET NAME REV
A3 CLOCKING 1V2
=
25/30
REV 1.6
J18
ZDA15S
+5V NC 1 9 NC
NC 2 10 NC
NC 3 11 NC
4 12 MIDI_OUT
NC 5 13 NC
NC 6 14 NC
NC 7 15 +5V
U9 8
XS1_L2_124LGA +5V
R105 U20
16
17
A39 ADC_SD2 74HCT125
X1D0A40 ADC_SD3 ADC_SD2
X1D1A41 SYNC_SEL ADC_SD3 10K 14 +3V3
X1D2A42 CODEC_MODE SYNC_SEL 1 VCC U2
NC
X1D3A43 NC CODEC_MODE MIDI_OUT_X 21OE_N 3
X1D4A44 PLL_LOCK 1A 1Y 5
X1D5A45 WORD_CLK PLL_LOCK 4 VCC
X1D6A46 CODEC_INT WORD_CLK MIDI_IN 52OE_N 6 MIDI_IN_X 1 6 X1D39
R99
DNP
X1D7A47 CODEC_INT 2A 2Y A1 Y1 TP35
NC
X1D8A48 CODEC_RSTN 10 X1D38 3 4 MIDI_OUT_X
X1D9A49 CODEC_RSTN TP34 A2 Y2
I2C_SDA +3V3 +5V 93OE_N 8 NC
X1D10A50 I2C_SCL I2C_SDA 3A 3Y 2
X1D11A21 CODEC_LRCK I2C_SCL 13 GND
X1D12A23 DAC_SD2 CODEC_LRCK 124OE_N 11 NC
X1D13A24 X1D14 DAC_SD2 4A 4Y NC7WZ17
X1D14A25 C8 C106
X1D15 7 +3V3
X1D15A26 X1D16 GND
X1D16A27 X1D17
X1D17A29 100N 100N
X1D18 R109
X1D18A30 X1D19 X1D38
X1D19A31 X1D20
X1D20A32 X1D21 10K
X1D21A22 ADC_SD1
X1D22A28 DAC_SD3 ADC_SD1
X1D23A20 CODEC_SCLK DAC_SD3
X1D24A33 OPTICAL_TX CODEC_SCLK
IO_XCORE1
X1D25B16 SYNC_OUT OPTICAL_TX
X1D26B17 NC SYNC_OUT
X1D27B18 GPIO_0
X1D28B19 GPIO_1
X1D29B20 GPIO_2
X1D30B21
X1D31B22
GPIO_3 MIDI IO + TEST POINTS + SIGNAL PULLUPS
NC
X1D32B23 NC
X1D33B24 COAXIAL_TX
X1D34B25 MCLK_IN COAXIAL_TX
X1D35B26 DAC_SD1 MCLK_IN
X1D36B27 DAC_SD4 DAC_SD1
X1D37B30 X1D38 DAC_SD4
X1D38B31 X1D39
X1D39
X1D14 X1D15 X1D16 X1D17 X1D18 X1D19 X1D20 X1D21
+3V3
D14 D7 D6 D5 D12 D11 D10 D9 J19

GREEN GREEN GREEN GREEN GREEN GREEN GREEN GREEN 1 2 X1D21
3 4 X1D20
I2C_SDA 5 6 X1D19
I2C_SCL 7 8 X1D18
GPIO_0 9 10 X1D17
GPIO_1 11 12 X1D16
1K
1K
1K
1K
1K
1K
1K
1K
R92
R93
R94
R95
R96
R97
R98
R100
GPIO_2 13 14 X1D15
GPIO_3 15 16 X1D14
HEADER_RA
XCORE STATUS LEDS EXPANSION HEADER
PROJECT NAME
XR-USB-AUDIO-2.0-MC
SIZE SHEET NAME REV
A3 XS1_XCORE1 1V2
=
26/30
REV 1.6
+3V3 +3V3 +3V3 +3V3 +3V3
U24
FB4
6 5
C_N VCC C7 C113
470R
C10
C
100N 100N 500mA
3 D Q
4
OPTICAL_TX D Q
100N
MCLK 1 2
MCLK CP GND
J5
NC7SZ175 2
VCC
3
IN OPTICAL
1
GND
+3V3 +3V3
TOTX147PL
U1
6 5
C_N VCC
R9 T1
1 6 2 J2
C
232R
RCJ-014 COAXIAL
C9
3 D Q
4
COAXIAL_TX D Q
100N
1A
C114
3 4 NC 1B
NC 1C
R8
DA102C
107R
MCLK 1 2 47P
CP GND C11
NC7SZ175 33P
DIGITAL OUT - OPTICAL & COAXIAL
+3V3
+3V3
FB3
C12
470R
C6 100N
500mA
100N
J4
3
VCC
R7
1
OPTICAL OUT OPTICAL_RX
2 0R
GND
TORX147PL
100N
C116
J3 2
COAXIAL RCJ-014 +3V3
1A +3V3
R107
1B NC R5
91R
1C NC 3 1
PESD0603-240
D16
820R 470R R4
5
4 COAXIAL_RX
R6 R106 33R
2 U25
C119
FIN1002
470R
R108
470R
100N
PROJECT NAME
100N
C117
XR-USB-AUDIO-2.0-MC
SIZE SHEET NAME REV
DIGITAL IN - OPTICAL & COAXIAL A3 DIGITAL_IO 1V2

=
27/30
REV 1.6
J14
KLBRSS3
9 NC
8 NC
7 NC
3 NC R61 R62
4U7
C70
2
4 NC
5 NC 100K 100K
6 NC GAIN IS -(100/100) = -1
1 +4V1A
+4V1A
+4V1A
U7
8
2
V+ R66
R64
4K7
C65
4U7
C71
1
INST_IN
BIAS 3 V- 470R
C67 100N
4 LMV722
C72
2N2
R63
4K7
4U7
INSTRUMENT PRE AMP
+4V1A
R59
2K2
J13
SJ-3524-SMT R58 R60
4U7
C69
2
10 NC
3 20K 200K
1 GAIN IS -(200/20) = -10
U7
6
R65
4U7
C68
7
MIC_IN
BIAS 5 470R
C66
LMV722
2N2
MICROPHONE PRE AMP
PROJECT NAME
XR-USB-AUDIO-2.0-MC
SIZE SHEET NAME REV
A3 PREAMP 1V2
=
28/30
18 Board Revision Changes

This sections lists the changes between revisions of the PCB.
18.1 Changes From 1V0 To 1V1

· Swapped R62 and R66 silkscreen labels to correct error.
· Removed GPIO test points and added GPIO connector
· Split digital I/O to use seperate ports, rather than outputs being identical and the input
being selected by a switch.
· Added testpoints for new digital I/O signals.
· Added PLL AUX LED.
· Added power sequencing to power supplies.
· Moved R75, C75 and 13M oscillator to add power sequencing.
· Changed layout of 1V0 SMPS.
· Changed L2 footprint to improve solderability.
· General tidy up and minor track changes.
18.2 Changes From 1V1 To 1V2

· Added buffer for MIDI I/O to correct 5V going into XS1-L2 I/Os.
· Added pull ups on MIDI signals to stop startup glitches.
· Added 47pf cap to slow coax output and tidied up digital out layout.
· Redesigned coaxial input for better performance and reduced cost.
· Moved the optical input track away from the 1V0 SMPS inductor.
· Moved bulk 1V0 decoupler (C93) across to far corner of L2.
· Changed most 0402 decouplers to 0603.
· Changed layout of the 13M oscillator.
· Added 5 more ground test points (next to CLK, VBUS, MIDI, DIGITAL IN and DIGITAL OUT).
· Added silkscreen labels to all test points, apart from the codec signals in the middle of
the board.
· Added silkscreen labels for 5V DC, POWER SW, USB, XSYS and GPIO.
· Moved around R19, R52 and C34 to make it in line with other analogue outputs.
· Tidied up teardrops and changed them to curved shape.
REV 1.6
19 Related Documents
The following documents provide more information on designing with XMOS
technology:
· Programming XC on XMOS Devices: Explains how to program XMOS event-driven

processor devices using the XC language.
· XCore XS1 Architecture Tutorial: Provides an overview of the XS1 instruction set
architecture.
· XS1 XSystem-L: Provides an introduction on how to boot the XS1-L devices.
· XMOS Tools User Guide: Explains how to use the XMOS Tools to program XMOS
event-driven processor devices.
For the most up-to-date information including schematics and product datasheets,
is please visit:
· http://www.xmos.com/usbaudio2/
20 Release History
Date Version Description
28/01/10 1.0 Initial version
05/02/10 1.1 Revisions following interval review
24/02/10 1.2 Revisions for power supply sequencing
02/03/10 1.3 Revisions for board release 1V1
27/04/10 1.4 Revisions for R102
28/05/10 1.5 Revisions for MIDI, PLL & XTAG2
29/06/10 1.6 Revisions for board release 1V2
Copyright © 2010, All Rights Reserved.
Xmos Ltd. is the owner or licensee of this design, code, or Information (collectively, the “Information”) and
is providing it to you “AS IS” with no warranty of any kind, express or implied and shall have no liability in
relation to its use. Xmos Ltd. makes no representation that the Information, or any particular implementation
thereof, is or will be free from any claims of infringement and again, shall have no liability in relation to any
such claims.
XMOS and the XMOS logo are registered trademarks of Xmos Ltd. in the United Kingdom and other countries,
and may not be used without written permission. All other trademarks are property of their respective owners.
Where those designations appear in this book, and XMOS was aware of a trademark claim, the designations
have been printed with initial capital letters or in all capitals.
REV 1.6

USB Audio 2.0 MC Hardware Manual (1.6)

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USB Audio 2.

0 Reference Design, XS1-L2 Edition Hard-

If you intend to produce hardware designs based on the

A block diagram of the design is shown below:

Analog In & Out

1.1 Feature Overview

Key features of the board are as follows:

· Six channels of analogue line level input

· Eight channels of analogue line level output

· Optical and coaxial digital audio input (S/PDIF or ADAT)

· Optical and coaxial digital audio output (S/PDIF or ADAT)

· MIDI input and output

· Word (house) clock input to allow synchronization to an external clock

· Integrated instrument and microphone pre-amplifier

· Integrated headphone amplifier on analogue outputs 1/2

· Powered via USB bus or external 5V source

· Eight LEDs for programmable use

· Multiple test-points to allow connection of custom ADC/DAC hardware etc

1.2 Board Components

A XS1-L2 Device J 1V0 Core Supply

1 5V DC Power In 11 Analogue 5/6 OUT (Stereo 3.5mm Jack)

2 XS1-L2 Device [A]

2.1 Clocking [K]

3 USB Connector and Transceiver [19 & I]

4 Audio CODEC [C]

CODEC_MODE Clock Mode

CODEC mode CODEC sample rate range

4.1 Analogue Audio I/O [4 - 12]

5 Digital Audio Output [13 & 14]

6 Digital Audio Input [15 & 16]

7 MIDI I/O [2]

8 Audio Clocking [3 & K]

The behaviour of this select signal is as follows:

SYNC_SEL PLL clock source

A variety of clock sources can be used, including:

· Word clock input.

9 SPI Flash Memory [L]

Port SPI Signal

10 XSYS Interface [18]

Signal Pin Description

11 User LEDs [I]

12 Expansion Header [17]

The header contains the following:

· +3V3 power pin.

· I2 C bus (as used to configure the PLL and CODEC).

· One 4-bit GPIO port (X1P4F).

Pin Port Signal

Each IO pin can source or sink a maximum of 4mA.

13 Power [1, G, H, J, M & Q]

When the board is powered on the Power LED is illuminated.

14 Printed Circuit Board

Signal stack up is as follows:

Test Point Port Signal

15.2 Test Points by Signal

Signal Port Test Point

15.2.2 XS1-L2 System

Signal Port Test Point

15.2.3 Audio Clocking

Signal Port Test Point

* Enabled via DNF resistor R102.

15.2.4 Codec Audio

Signal Port Test Point

15.2.5 Codec Config/Status