6) Bus Systems

Bus Systems

CPU centered data transfer

– data exchange through CPU
– data exchange consumes CPU processing power
disk I/O card

CPU terminal
RAM memory
printer
clock
CPU centered organization of computer system

Bus system based data transfer

– Bus: collection of wires for interconnecting the various components of a
microcomputer for data exchange and power supply
– each unit can communicate with other unit if necessary
RAM memory clock terminal

CPU printer I/O card disk

bus
Bus organization of computer system
Bus structure
Parameters describing a bus system
– Mechanical and electrical data: board dimension, type of connector, power
consumption, cooling requirements
– Whether the bus is processor-oriented or processor independent
– Address width or addressable memory space
– Data width
– Data transfer type synchronous/asynchronous
– Data and address multiplexing
– Clock frequency
– Data transfer rate, typical and maximum
– Number of interrupts and interrupt handling
– Number of master units (that can control the data transfer)
– Additional features such as auto-configuration

1. Mechanical Construction
– Board size
– Connector types

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 6) Bus Systems

– Standard Eurocard format/IEEE 1101 standard

– Single Eurocard, size: 100  160 mm
– Double Eurocard, size: 233.35  160 mm
– Connector types
a) Edge connectors
 Edge connectors: risk of poor
electrical contact
 Cheap and simple
 Used in personal computer; ISA
(Industry Standard Architecture)
or PCI (Peripheral Component
Interface) bus Edge connector

b) Plug-in connectors
 Plug-in connectors: higher electrical
and mechanical stability
 DIN 41612 standard  Model A: 32
pins, Model B: 64 pins, Model C: 96
pins
 DIN 41612 C used in VMEbus and
Multibus II
 Used in IDE cable in personal
computer

2. Bus interface electronics

a) TTL totem pole
 High output: Q1 ON, Q2 OFF
 Low output: Q1 OFF, Q2 ON
 Two totem pole outputs connected together may result in short circuit

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 6) Bus Systems

a) b)
a) Internal structure of TTL NAND gate and b) short connection of two totem pole
outputs

b) Open collector
 TTL output
 Pull-up resister connected to output
 Outputs connected together  wired OR configuration
 Output is high only if all the transistors are high
 Output is low if one (or more) of the transistors is low
 All non communicating (idle) boards outputs high
 The communicating board output is reflected in the line
 Used for indicating readiness to send or accept data

(a) (b)
(a)Open collector configuration (b) wired OR connection

c) Tristate logic
 Three states  Logic HIGH, Logic LOW and high impedance state
 High impedance state  does not affect the state of the line, but can
monitor the state of the line
 Can be connected together. The board which does not have to write will be
in the high impedance state

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 6) Bus Systems

 Used for data and address exchange

electronics
board
logic data
output to the bus line

control line

logic data
input

3. Bus electrical interface

Bus lines can be divided into
 Address line: source or destination address of the data currently present on the
bus
 Data line: data from or to the addressed locations.
Multiplexing: Some bus, address line and data lines are shared
Memory mapped I/O: I/O port assigned unique memory address
 Control line: service signal such as: read or write operation, readiness to send or
receive data, interrupts to request special handling, clock signal
 Power line: Power to the board from power supply (many boards does not have
its own power supply)
 Spare line: not connected, reserved for future modification or user defined
application

Bus Operation
Bus Protocol: set of rules for operation of a bus
Bus Master: board which controls the bust i.e. sets address and operation to be
performed
Bus Slave: unit address by the bus master and reacts to command by the master
Slave

bus

Master

Bus Arbitration: selection of the bus master

Bus Contention: Several boards try to be bus master at the same time creating a
conflicting situation

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 6) Bus Systems

Synchronous Data Transfer: bus operation based on the timing of a reference clock
signal
Bus Cycle: reference clock period
Asynchronous Data Transfer: event based bus operation, no synchronization clock,
coordination by handshaking

1. Synchronous Data Transfer

 Operation synchronized by a common reference clock signal
 Master sets the bus address and sets control lines to indicate the address is valid
and operation to be performed (read/write)
 Read operation: slave puts the data on the bus for a fixed number of cycles
 Write operation: master puts the date on the bus for a fixed number of cycles.
Slave fetches data within the valid number of cycles
 If the addressed board is not able to decode the address and process the requested
data in time, the board asserts a WAIT line to indicate the delay

address valid address

(from
master)

data read (from master)

valid
data (from slave)
data

1 2 3 4 5 6 7 8

2. Asynchronous Data Transfer

 No reference clock
 Handshaking lines to coordinate the data transfer

Read operation
 Master sets the address lines and asserts ADDRESS_VALID line and data READ
line
 All boards decodes the address
 The addressed board puts the data in data line and asserts DATA_READY
 Master negates DATA_READY and DATA_ACKnowledge

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 6) Bus Systems

(data accepted
address no longer valid)
address valid address
(from
master) ADDRESS_VALID
(data accepted) / READ/ DATA_ACK
data read (from master)
(data no
longer valid)
valid data
data (from slave)

(data no
DATA_READY
longer valid)
data valid (from slave)

Write operation
 Master sets the address lines, puts data in the data line and asserts
ADDRESS_VALID line and data WRITE line
 All boards decodes the address
 The addressed board processes the data and asserts DATA_ACKnowledge

(address
no longer valid)
address valid address
(from
master)
(data and address ADDRESS_VALID
no longer valid) / WRITE
data write (from master)
(data no
longer valid)
valid data
data
(from slave)
(ready for
data accepted new data) DATA_ACK
data accepted
(from slave)

3. Block Transfer and Direct Memory Access (DMA)

Block Transfer: Transfer of content of memories at consecutive addresses
Start address is passed; the block of memories is transferred in succession
Direct Memory Access (DMA): transfer data directly to or from memory without the
help of CPU
DMA controller sends DMA Request to CPU. CPU grants bus access by
DMA Acknowledge. DMA controller transfer data.

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 6) Bus Systems

4. Interrupt Handling
 Interrupt: signal sent by a peripheral board to the central processor (or another
board) in order to request attention.
 The processor stops its current task and executes a service routine according to the
interrupt.
 Interrupt is event base
 Interrupt Priority: buses have several interrupt request lines and each line has
different priorities. Interrupts generated at the same time is served according to
their priority.
 Shared Interrupt: each interrupt line is shared by several boards. If a board want
to generate an interrupt, it asserts the interrupt line, the CPU identifies the interrupt
generated by polling.
 Daisy-chain connection:
 A board generates interrupt request
 Interrupt handler generates an acknowledge signal
 The acknowledge signal is daisy-chained and the line is normally closed
 The board requesting interrupt will open the connection and prevent the
acknowledge signal from traveling further.
 And the board writes its identification code in the bus
 In case of interrupt from several boards, the board closest to the interrupt
handler will get the acknowledge
 Daisy-chain line needs two pins. If no board is connected in a slot, the pins
should be shorted with jumpers.

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 6) Bus Systems

interrupt request
from this unit
Board 1 Board x Board n
jumper

to mater unit
other bus lines

 Interrupt as message: Interrupts are considered as special messages and

transferred from the source to the destination board as data transfer

5. Bus Arbitration
Bus Arbitration: selection of the bus master
Arbiter: super master, allocates bus master
 Board wishing to get bus control sends a request to the arbiter via an interrupt
on a BUS_REQUEST line
 The arbiter compares priority of the requesting board with the current bus
master and decides when the bus control has to be transferred
Bus busy line

Bus Bus
request acknowledge

Arbiter

Bus Allocation Line: common line to all boards

 Board wishing to get bus control sends a request via the bus allocation line
 The current master compares its priority to priority of the requesting board
and accordingly grants the bus control
 More than one bus allocation line for different priorities
 In case of more than one board requesting to be master unit, round-robin
(ordered in sequence) or priority allocation (base on priority) method could be
used to allocate bus master

6. Construction of a Bus System

Factors to be considered while constructing a Bus System
 Most important board closest to CPU (In case of daisy-chain connection, most
closest board has highest priority)
 Short circuit the daisy-chain connection of free boards
 Insert pull-up resistors on open collector, wired OR lines
 Check if the common power supply is adequate for all boards

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 6) Bus Systems

 Check if ventilation is sufficient

VMEbus (IEEE 1014)

– VERSA module Eurocard
– IEEE 1014
– Address length 16/24/32 bits
– Data word length 16/32 bits
– Data transfer rate: theoretical maximum: 57 Mbyte/s, practical 30-40 Mbyte/s
– Seven interrupt signals [IRQ1* – IRQ7*], wired OR line, IRQ7* highest priority
– Interrupt acknowledge line IAK* daisy–chained
– Support for multiprocessor systems, four priority levels for bus allocation
– Data block transfer, maximum block length 256 words
– Asynchronous data transfer
– Bus Master Arbitration
– 4 bus request lines BR0* – BR3*, wired OR line, BR3* highest priority
– Board in the first slot acts as master arbitration (arbiter)
– Bus busy line BBSY* indicate status of bus
– As soon as BBSY* line is released the arbiter grants the request by daisy chained
lines BGX0* – BGX3*

Multibus II
– ANSI/IEEE 1296
– Double Eurocard format 233  160 mm
– Two 96-pin DIN 41612 – C connectors called P1 and P2
– Address/Data line 32 bits multiplexed
– Synchronous data transfer, clock frequency 10 MHz
– Board in the first slot is central service module (CSM)
– CPU and RAM in same board
– Addressable range – Memory Space
– Message Space : bus system arbitration and protocols
– Interconnect Space : data and procedures for board
identification and self-testing and system auto-
configuration
– Communication by message packets up to 32 bytes
– Solicited message: sent only after an explicit request by the receiving unit
– Unsolicited message: request for data, signaling message and interrupts
– Dedicated bus interface chip, called message passing coprocessor (MPC)
– MPC: bus arbitration, division of messages into packets and their reconstruction
– Interrupts send as unsolicited message

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 6) Bus Systems

Local Bus Local Bus

other other

CPU CPU

memory memory

MPC MPC

Multibus II

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