VLSI IEEE Projects Titles – 2017-2018

LeMeniz Infotech

36, 100 feet Road, Natesan Nagar(Near Indira Gandhi Statue and Next to Fish-O-Fish),
Pondicherry-605 005

Web : www.ieeemaster.com / www.lemenizinfotech.com

Mail : info@lemenizinfotech.com / projects@lemenizinfotech.com

Phone : 9566355386 / 9962588976

S.No Title Year

LOW POWER

1 A 2.5-ps Bin Size and 6.7-ps Resolution FPGA Time-to-Digital Converter 2017
Based on Delay Wrapping and Averaging

2 Adaptive Multi-bit Crosstalk-Aware Error Control Coding Scheme for 2017

On-Chip Communication

3 Coordinate Rotation-Based Low Complexity K-Means Clustering 2017

Architecture

Low-Power Scan-Based Built-In Self-Test Based on Weighted

4 Pseudorandom Test Pattern Generation and Reseeding 2017

5 A Way-Filtering-Based Dynamic Logical–Associative Cache 2017

Architecture for Low-Energy Consumption

6 Resource-Efficient SRAM-based Ternary Content Addressable Memory 2017

7 Write-Amount-Aware Management Policies for STT-RAM Caches 2017

8 Fault Diagnosis Schemes for Low-Energy Block Cipher Midori 2017

Benchmarked on FPGA

9 High-Throughput and Energy-Efficient Belief Propagation Polar Code 2017

Decoder

10 High-Speed Parallel LFSR Architectures Based on Improved State- 2017

Space Transformations

11 Scalable Approach for Power Droop Reduction During Scan-Based 2017

Logic BIST

12 Stochastic Implementation and Analysis of Dynamical Systems Similar 2017

to the Logistic Map

HIGH SPEED DATA TRANSMISSION

1 Efficient Designs of Multi-ported Memory on FPGA 2017

2 High-Speed and Low-Latency ECC Processor Implementation Over 2017

GF(2m) on FPGA

3 An On-Chip Monitoring Circuit for Signal-Integrity Analysis of 8-Gb/s 2017

Chip-to-Chip Interfaces With Source-Synchronous Clock

4 A 2.4–3.6-GHz Wideband Sub-harmonically Injection-Locked PLL with 2017

Adaptive Injection Timing Alignment Technique

5 Hardware-Efficient Built-In Redundancy Analysis for Memory With 2017

 Various Spares

6 Fast Automatic Frequency Calibrator Using an Adaptive Frequency 2017

Search Algorithm

7 A High-Efficiency 6.78-MHz Full Active Rectifier with Adaptive Time 2017

Delay Control for Wireless Power Transmission

8 Scalable Device Array for Statistical Characterization of BTI-Related 2017

Parameters

AREA EFFICIENT/ TIMING & DELAY REDUCTION

1 VLSI Design of 64bit × 64bit High Performance Multiplier with 2017

Redundant Binary Encoding

2 A Method to Design Single Error Correction Codes with Fast Decoding 2017
for a Subset of Critical Bits

3 ENFIRE: A Spatio-Temporal Fine-Grained Reconfigurable Hardware 2017

4 Hybrid Hardware/Software Floating-Point Implementations for 2017

Optimized Area and Throughput Tradeoffs

5 Efficient Soft Cancelation Decoder Architectures for Polar Codes 2017

6 Low-Complexity Digit-Serial Multiplier Over GF(2m) Based on Efficient 2017

Toeplitz Block Toeplitz Matrix–Vector Product Decomposition

7 Hybrid LUT Multiplexer FPGA Logic Architectures 2017

8 Sign-Magnitude Encoding for Efficient VLSI Realization of Decimal 2017
Multiplication

9 FPGA Realization of Low Register Systolic All-One-Polynomial 2017

Multipliers over GF (2m) and Their Applications in Trinomial
Multipliers

10 Low-Complexity Transformed Encoder Architectures for Quasi-Cyclic 2017

Non-binary LDPC Codes Over Subfields

11 Antiwear Leveling Design for SSDs With Hybrid ECC Capability 2017

12 Energy-Efficient VLSI Realization of Binary64 Division with Redundant 2017

Number Systems

Audio, Image and Video Processing

1 A Dual-Clock VLSI Design of H.265 Sample Adaptive Offset Estimation 2017

for 8k Ultra-HD TV Encoding

2 RoBA Multiplier: A Rounding-Based Approximate Multiplier for High- 2017

Speed yet Energy-Efficient Digital Signal Processing

3 Energy-Efficient Reduce-and-Rank Using Input-Adaptive 2017

Approximations

4 Dual-Quality 4:2 Compressors for Utilizing in Dynamic Accuracy 2017

Configurable Multipliers

5 An FPGA-Based Hardware Accelerator for Traffic Sign Detection 2017

6 Soft Error Rate Reduction of Combinational Circuits Using Gate Sizing 2017
in the Presence of Process Variations

7 Time-Encoded Values for Highly Efficient Stochastic Circuits 2017

8 Design of Power and Area Efficient Approximate Multipliers 2017

VERIFICATION

1 COMEDI: Combinatorial Election of Diagnostic Vectors From Detection 2017

Test Sets for Logic Circuits

2 Reordering Tests for Efficient Fail Data Collection and Tester Time 2017
Reduction

NETWORKING

1 Multicast-Aware High-Performance Wireless Network-on-Chip 2017

Architectures

VLSI - BACK END PROJECT - TANNER(nm) / HSPICE(nm) / DSCH3 - MICROWIND(um)

1 Temporarily Fine-Grained Sleep Technique for Near- and Sub- 2017

threshold Parallel Architectures

2 Low-Power Design for a Digit-Serial Polynomial Basis Finite Field 2017

Multiplier Using Factoring Technique

3 Analysis and Design of a Low-Voltage Low-Power Double-Tail 2017

Comparator
4 10T SRAM Using Half-VDD Precharge and Row-Wise Dynamically 2017
Powered Read Port for Low Switching Power and Ultralow RBL
Leakage

5 Delay Analysis for Current Mode Threshold Logic Gate Designs 2017

6 Area and Energy-Efficient Complementary Dual-Modular Redundancy 2017

Dynamic Memory for Space Applications

7 Probability-Driven Multi-bit Flip-Flop Integration With Clock Gating 2017

8 A High-Speed and Power-Efficient Voltage Level Shifter for Dual- 2017

Supply Applications

9 A 0.1–2-GHz Quadrature Correction Loop for Digital Multiphase Clock 2017

Generation Circuits in 130-nm CMOS

10 Conditional-Boosting Flip-Flop for Near-Threshold Voltage Application 2017

11 An All-MOSFET Sub-1-V Voltage Reference With a−51-dB PSR up to 60 2017

MHz

12 A 65-nm CMOS Constant Current Source with Reduced PVT Variation 2017

13 A Fault Tolerance Technique for Combinational Circuits Based on 2017

Selective-Transistor Redundancy

14 Temporarily Fine-Grained Sleep Technique for Near- and Sub- 2017

threshold Parallel Architectures

15 A 100-mA, 99.11% Current Efficiency, 2-mVppRipple Digitally 2017

Controlled LDO with Active Ripple Suppression
16 Sense Amplifier Half-Buffer (SAHB): A Low-Power High-Performance 2017
Asynchronous Logic QDI Cell Template

17 On Micro-architectural Mechanisms for Cache Wear out Reduction 2017

18 Energy-Efficient TCAM Search Engine Design Using Priority-Decision in 2017

Memory Technology

19 A 92-dB DR, 24.3-mW, 1.25-MHz BW Sigma–Delta Modulator Using 2017

Dynamically Biased Op Amp Sharing

20 A 0.45 V 147–375 nW ECG Compression Processor With Wavelet 2017

Shrinkage and Adaptive Temporal Decimation Architectures