A Low-Energy Heterogeneous Reconfigurable DSP IC

architecture template and the model of reconfiguration.

1 INTRODUCTION
The advent of the third generation of wireless
applications creates a need for digital signal processing
platforms that simultaneously display high computational
performance, ultra low-energy consumption and a high
degree of flexibility and adaptability. The flexibility and
adaptability is a necessity in the presence of multiple and
evolving standards, and helps to increase quality-of-
service in the presence of dynamically evolving channel
conditions. (Re)configurable processors offer the
advantage of combining flexibility and low-energy [1][2]
by providing a direct spatial mapping from algorithm to
architecture, hence reducing the control overhead
typically associated with instruction-set processors.
A low power reconfigurable DSP architecture template
(Pleiades) which encapsulates heterogeneous computing
elements has been proposed [2][3] to solve the problem of
meeting the requirement of flexibility, speed and energy
efficiency at the same time (Figure. 1). The Pleiades
architecture style echoes the current trend in system-on-
a-chip design which includes a wide variety of
macromodules including core processors, DSPs,
programmable logic, embedded memory, and custom
modules [4]. The heterogeneous architecture style of
Pleiades allows better algorithm-architecture matching
,giving better power/performance than many
heterogeneous reconfigurable processors which
incorporate only a microprocessor and fine-grained
FPGAs.
In section 3 and 4, the methodology used to map
algorithms to an architecture is given and the
implementation of the architecture is discussed. Section 5
reports the testing strategy for the design and results of
the final chip.
2 HETEROGENEOUS
RECONFIGURABLE DSP
Reconfigurable architectures [5][6][7] have received
significant attention in recent years in both the general
purpose computing as well as embedded processing.
Mixing processor with fine-grain reconfigurable elements
has been the main approach attempted by the above
systems. The Pleaides reconfigurable architecture
achieves low energy consumption by providing a
computational platform with mixed programming
granularity (i.e. microprocessor, reconfigurable dataflow,
FPGA) [8]. In this section, we explain our architecture in
concept, and provide a description of the reconfiguration
and computation models used in our design methodology.
2.1 Architecture Template
The Pleiades architecture (Figure. 2) is composed of a
programmable microprocessor and heterogeneous
computing elements (referred to as satellites in the rest of
the paper). The architecture template fixes the
communication primitives between the microprocessor
dat
a ASIC or FPGA dat
a
module

c
ont
rol
c
lo
cks
In this paper, we describe the design process and f
lag
s

control
s
ig
nals
fa
lg
s

h
and
sha
ke h
and
sha
ke
implementation results of an instance of the Pleiades
c
onf
ig
re
gis
ter

architecture , Maia, targetting the speech coding domain. A Satellite

In section 2, we give a description of the Pleiades SAT SAT

Configur ation

µP
Microprocessor
ASIC Pleiades DSP Reconfigurable Interconnect

Flexibility
SAT1 SAT2 SAT3

Energy-Efficiency Reconfiguration Bus

Figure 1. Energy and Flexibility Spectrum for Different Figure 2. Heterogeneous Architecture Template
Architectures
 Architecture Instance:
3 Address Generators, 3 Memories, 1 MAC/MUL and 1 ALU
and satellites and between each satellite. For each AG AG AG AG AG
C1 C2 C’1
algorithm domain (communication, speech coding, video
MEM MEM MEM MEM MEM
coding), an architecture instance can be created (with C4
C3
known satellite types and numbers) MAC /MUL MAC/ MUL
C ’8
C5 ALU

To reduce overhead in terms of instruction fetch and glo- reconfiguration

bal control, the architecture utilizes distributed control

and configuration. To achieve distributed control, each C’8

int erco nnect

C5
satellite is equipped with an interface that enables it to : :

pat ter n
C2 C ’4
exchange data streams with other satellites efficiently, C1 C ’1
Time
without the help of a global controller. The t0 t1 t2

communication mechanism between each satellite is

dataflow driven [9]. Figure 4. Model of Reconfiguration

The control means available to the programmer are basic
satellite configurations to specify the kind of operation to
be performed by the satellite, and configurations for the
reconfigurable interconnect to build a cluster of satellites.
2.2 Model of Computation and
Reconfiguration
While multiple threads of application can be run on an
instance of the Pleiades architecture template, the
compilation of a single thread down to the reconfigurable
components is the main core of the higher level
scheduling tools that can utilize multi-threads. Therefore,
the design methodology described later in the paper aims
to support a smooth transition from a single thread
algorithm to an optimized implementation on Pleiades.
Figure. 3 illustrates the flow of computation supported by
this software methodology. As shown in the figure, a
sequential thread is first initialized on the
microprocessor. After configuration codes are executed
on the processor, the control is transferred to the Pleiades
reconfigurable satellites (the “split” point in Figure.3)
and the computation is returned back to the processor
after all satellite operations are finished (the “join”
point). Multiple split points exist within a seqeuntial
Application Thread1
split
Thread3 Thread2
on satellites
join
on programmable processor
thread and the satellites and connections have to be
reconfigured for each split point.
The main idea behind reconfigurable computing that is
advocated by the Pleiades system is to build a computa-
tional engine through spatially-programmed connections
of processing elements (satellites). The interconnect
model that needs to support such a system is depicted in
Figure. 4. On the time axis, t0, t1 and t2 indicate the time
of reconfiguration. The bars (C1, C2 etc.) in-between two
reconfiguration times represent a set of inter-satellite
connections that has to be realized simultaneously by the
reconfigurable interconnect.
3 OVERVIEW OF THE
ARCHITECTURE DESIGN
METHODOLOGY
There are two key issues to be resolved in order to make
the methodology practical to the designers. Firstly, the
architecture combines two very distinct models of
computation, control-driven computation on the general-
purpose microprocessor and data-driven computing on
the clusters of satellites. Therefore, the goal of the
architectural exploration process is to partition the
application over these two computing paradigms so that
performance and energy dissipation constraints are met
(during the compilation process). Secondly,
optimizations related to reconfigurability have to be
supported at both the architecture design as well as com-
pilation stage. Both of these issues requires careful
modeling of the algorithm and the underlying
heterogeneous architectures.

The basic flow of the design exploration methodology

Figure 3. Flow of Computation on Pleiades
[10] is presented in Figure. 5. After the introduction of
terminology, a short overview of the overall flow is given
in section 3.1.1. A more detailed description of this
methodology and tools developed can be found in [11].
Definition of Kernel - A computational intensive part of
the algorithm that often resides in nested loops.
3.1.1 Basic Methodology Flow
The methodology flow takes DSP or communication
algorithms specified in a high-level language (e.g. C) as
input. The initiation of the design process requires the
establishment of a first-order baseline model of the
algorithm complexity and bottlenecks. Such a model
allows for the selection and execution of architecture-
independent optimizations (stage 1). As architectural
choices have yet to be made, this model assumes the
presence of a “virtual architecture” with some generic
operator costs attached to it. Optimizations at this stage
only address either win-only situations or order-of-
magnitude improvements, so that absolute accuracy is not
that important.
evaluated in order of importance and mapped to satellites
for better power and performance [12]. If a hardware
implementation is deemed worthwhile, a repartitioning of
the design is established.
After all costly kernels are mapped to accelerators, a final
partition of the algorithm across different architectures is
obtained (stage 5) and memory assignment and allocation
is performed to minimized memory trasfers. While the
rest of the algorithm remains as high- level language, the
portions of the algorithm to be implemented by satellites
are specified in an intermediate form that is capable of
modeling the structure of the reconfigurable satellite
operations (i.e. as a netlist). Based on this conceptual
netlist, implementation optimizations (stage 6) [13] are
invoked to choose a good reconfigurable interconnect
architecture (during architecture design path) and to
generate efficient configuration and interface code
(during compilation and test vector generation path) [14].

Applications
After a satisfactory algorithm formulation is obtained, the
Satellites
architectural mapping and partitioning process can be
Microprocessors(s)
entered. To be meaningful, the partitioning process stage 1.
Specification
timing, power constraints
should be based on realistic bottom-up information Algorithm Architecture
regarding the cost of implementing functions and Refinement Characterization

operations on the different architectural choices. Our stage 2.

design-exploration methodology relies extensively on the Mapping to Core
stage 3.
availability of power-delay models for all components in
Kernel Ranking PDA
its architectural library (stage 2). The estimation methods models
employed in each of these models vary depending upon
Mapping to accelerators
the type of the module and the desired accuracy. While Exploration
stage 4.
the absolute accuracy of these characterizations is not
Kernel
crucial, it is important that bounds on the prediction PDA macro-model

accuracy are known. Only “Improvements” that fall

within the noise level of the estimations are accepted. Performance Evaluation

stage 5. stage 6.
The architecture partitioning and mapping process is
Partitioning
started by establishing an initial solution. Given the Interconnect
Optimization
implementation simplicity of a pure software
Compilation/Code Generation
implementation, we have adopted a “software-centric”
Reconfig. Hardware
approach that assumes that the whole algorithm is
initially mapped onto the microprocessor (stage 3). This Implementation
Optimization
establishes how close such a solution adheres to the
design specifications and helps to establish the design
Figure 5. The Software Methodology
bottlenecks. A rank ordering of the dominant compute Flow
kernels is established. In stage 4, dominant kernels are
At different phases of the design phase, it is important to
show the impact of particular design choices on the
Mem1K Mem1K
overall performance and energy of the application in
order to give meaningful design guidance. A spreadsheet-
like environment does precisely that and it is utilized in AG AG FPGA AG AG
our methodology.

Mem1K Mem1K
4 CHIP IMPLEMENTATION
Using the methodology described above, a prototype ALU ALU
MAC MAC Mem
architecture, Maia, has been designed targeting the Mem
i i
o o
domain of voice processing (CELP based speech coders
i.e. 16kb/sec VSELP, LDC-CELP etc.) for wireless AG Mem512
AG AG
Mem512
AG

devices.
Interface

The most dominant kernels in this domain are vector

computations (dot-products, FIR, IIR filters etc). After
going through stage 1 to stage 5 of the methodology, the
following specifications of the architecture are obtained.
The Maia processor (Figure. 6) combines a
microprocessor core (embedded ARM8) with 21 satellite
processors: two MACs, two ALUs, eight address
generators, eight embedded memories (4 512×16bit, 4
1K×16bit), and an embedded low-energy FPGA [15]. The
FPGA is used for infrequent functions (theta function
generation etc.) that does not justify custom ASIC
implementations.
Connections between satellites are accomplished through
a 2-level hierarchical mesh-structured reconfigurable
interconnect network. Through an interface control unit,
the ARM8 configures the satellites and communicates
data with satellites using IO interface ports and direct
memory reads/writes.
In the rest of this section, the architecture and circuit
designs of each component are described. We first
present the computational elements (microprocessor,
ASIC and FPGA designs) in section 4.1. The processor-
satellite and inter-satellite interface design are discussed
in section 4.2. Reconfigurable interconnect architecture is
described in Section 4.3.
4.1 Component Description
ARM
1 1 2 2
1 2
1 2
2 1
2 1
22 1 1
Universal Switchbox
Hierarchical Switchbox
(only cross-mesh connections are shown)
Figure 6. The Maia floorplan
4.1.1 Embedded microprocessor
The embedded ARM8 core is optimized for low-energy
operation, and can operate under variable supply voltages
[16]. The core is synthesized from VHDL with hand
optimizations on the critical path to enhance performance
and power.
4.1.2 Programmable ASIC elements
Since filter operations in the applications make frequent
use of MAC and memory units, the cores of both MAC
and memory are custom designed ICs. The ALU and
address generator are synthesized from VHDL.
Both the dual-stage pipelined MAC (including
shift/round/saturate functions) and the ALU can be
configured to handle a range of operations. The address
generators and embedded memories are distributed to
supply multiple parallel data streams to the
computational elements. The address generator features a
small local instruction memory, and can be programmed Out
n
I Processor
to support various types of addressing patterns and nested In

Reconfigurable
Module
Req in

Network
loops with loop counters and stride counters. It behaves Clk Done Clk
as the local controller of data-flow kernels by initiating Req
in
delay clk
Req
out Enable Done
the data-flow threads, and by signaling the end of the
data-flow threads to the ARM8.
(a) Globally asynchronous - locally synchronous signaling

1 1
4.1.3 Embedded FPGA MPY1 MPYn
1 n

Commercial FPGAs are often notorious for their energy
consumption and most of them can not be embedded in a
system-on-a-chip. Therefore, we make use of an in-house
low-energy embedded FPGA [15].
n Data associated with an end-of-vector token
MAC1
n Regular data
(b) Control tokens differentiate and delineate data streams and data structures (scalar,
vector, matrix)

The embedded FPGA contains a 4×8 array of 5-input 3-
output CLBs, optimized for arithmetic operations and
data-flow control functions. Its energy-efficiency has
been measured to be 70 times higher than equivalent
commercial solutions. This energy efficient FPGA design
is realized by combining both architectural and circuit
level modifications which are outlined below.
Logic block  The logic block is designed to improve
the interconnect utilization, and hence the interconnect
energy. It is made up of a cluster of 3 input look-up-
tables. It can be used to implement 5 input random logic,
or 2 bit arithmetic operations.
Low-swing circuit  Low-swing interconnect circuit
improves the energy by a factor of 2 as compared to a full
swing circuit. The logic blocks operate on 1.5V while the
low-swing signal lines have a 0.8V swing.
Interconnect Architecture  The interconnect is made
up of 3 levels of connectivity. Each level is targeted at
providing low energy connections for specific path
lengths. The Level0 structure is targeted at connections
between nearest neighbors. Each logic block can connect
to 8 of it’s immediate neighbors. The Level1 structure is
the traditional symmetric mesh architecture, and is good
for intermediate length wires. The Level3 structure is
used for implementing connections that span a
significant fraction of the chip. The connectivity of each
of these structures has been optimized using architecture
evaluation tools to obtain energy efficiency.
Clock Distribution  More than 80% of the clock
energy is dissipated in the clock distribution network.
Double-edge-triggered Flip-Flops are used to reduce the
clock activity by factor of 2, and hence a proportional
reduction in energy. The clock distribution network also
uses the low-swing technique for energy reduction.
Figure 7. Data-flow driven globally synchronous locally
asynchronous communication protocal
4.2 Communication Interface Description
4.2.1 Inter- satellites Communication Interface
The data-flow driven synchronization between the
processing elements employs a 2-phase self-timed
handshaking scheme with REQUEST and
ACKNOWLEDGE signals (Figure 7a), realized in a
globally asynchronous locally synchronous
implementation fashion. This approach not only reduces
power consumption by ensuring that a module is only
activated when data is ready, but also allows various
modules to operate at different and dynamically varying
rates. Data links combine 16-bit fixed-width data words
with 2-bit control tokens that serve as tags for different
data structures (scalar, vector, or matrix) that are
supported by the network (Figure 7b). Each module
includes a network interface controller to coordinate
communication and synchronization.
4.2.2 Communication Interface between the
Microprocessor and Satellites
This interface control unit coordinates synchronization
and communication between the synchronous ARM8 core
and the asynchronous reconfigurable data-paths, most
importantly helping the core perform the reconfiguration
of satellites by mapping all the configuration memories to
the ARM8 memory space.

The interface logic controls the strobe generation for
configuration reads/writes, handshakes, network reset,
start requests for the address generators and IO ports.
The acknowledge signals for the address generators and
IO ports are used to detect the end of kernel and the
ARM8 core is interrupted. Interrupt mask registers and
control registers are used to synchronize ARM8 with the
asynchronous satellite array.
The system supports two modes of operation: TEST and
SYSTEM modes. As part of the test strategy, the TEST
mode allows us to bypass the ARM8 processor and
execute individual kernels through the interface. In the
SYSTEM mode, instead of an on-chip cache for the
embedded ARM8, an external SRAM (with zero bus
turnaround) serves as the memory for the processor. In
order to meet the 40MHz performance for the
application, the off-chip memory is clocked twice as fast
as the core. The interface is designed to meet this
bandwidth.
4.3 Reconfigurable Interconnect
Architecture
Keeping the energy of the reconfigurable interconnect
network as low as possible while still meeting the
flexibility requirement is crucial to the success of out
approach of heterogeneous reconfigurable architecture.
This is realized by a combination of architecture and
circuit optimizations.
4.3.1 Hierarchical Interconnect Network
Architecture
Energy-efficient architecture must take advantages of the
locality and regularity of computation. Exploiting locality
by identifying natural isolated clusters of operations, can
be used to guide hardware partitioning resulting in the
minimization of global busses, thus reducing the
interconnect power. Although the underlying system is
heterogeneous, the DSP algorithms usually have
inherently repetitive computation patterns. Partitioning
the hardware by preserving such regularity will lead to
simpler interconnect structure with reduced fan-ins and
fan-outs. Especially for reconfigurable architectures,
more regular interconnect architecture achieve better
routability and less reconfiguration overhead. There is
trade-off between flexibility and energy-efficiency. For
instance, the crossbar network has the most flexibility,
but also the least energy efficiency. In stage 6 of the
design methodology, cross-bar, mesh and hierarchical
mesh structures are evaluated, and a 2-level hierarchical
mesh is decided for this implementation.
VDD
clk P5 clk
REF
in P3
d P2 P4
P1
REF GND
out
in
n1 n2 1V
GND d 0.4V
P6 P7
B A B
A
clk
N3 N1 N2 N4 clk out
Figure 8: Pseudo-differential low-swing interconnect
circuitry
The implemented hierarchical interconnect mesh
network can provide the optimum energy-efficiency with
right degree of flexibility within the application domain
of interest. Several clusters of tightly connected modules
are formed based on the communication locality. Each
cluster has a local mesh with 2 buses per channel, and a
universal switchbox at every intersection point (Figure
6). Global interconnections are supported by a 2nd level
larger-granularity mesh (implemented on the higher
metal layers) with 2 buses per channel and hierarchical
switchboxes, located at the key connection points. The
hierarchical switchbox (Figure 6) contains a universal
switchbox for each mesh-level, as well as a number of
cross-level interconnect switches. This hierarchical
network architecture requires only a limited number of
buses to achieve sufficient connection flexibility for our
target applications, and cuts the interconnect energy cost
by a factor of 7 compared to a straightforward crossbar
network implementation.
4.3.2 Low-swing Interconnect Interface Circuits
Communication energy is further reduced by employing a
low-swing (0.4V) pseudo-differential signaling scheme
(Figure 8). The wire capacitance loads are also reduced
by simplifying the switch network with NMOS-only
switches. The circuit employs an NMOS-only push-pull
driver with a very low voltage supply. The receiver is a
clocked sense amplifier with low input-offset and good
sensitivity followed by a static flip-flop. It contains
double pairs of input transistor, with the gates of P1 and
P3 connected to d, while the gates of P4 and P2 biased at
GND and REF respectively. Figure. 8 shows the
signaling waveforms. Based on our asynchronous
clocking protocol, the clock signal is generated from the
handshaking signals. The low-swing signaling reduces
the interconnect energy by a factor of 3.4 compared to a
full-swing CMOS implementation [17].
5 RESULTS AND STATISTICS
Maia is a 210-pin chip that contains 1.2 million Table 2 shows the performances of different chip
transistors and measures 5.2×6.7mm2 in a 0.25 µm 6- components (based on a per-block analysis) from
metal CMOS technology. Figure 9 shows the die photo PowerMill simulation.
of the Maia chip and Table 1. summarizes all the
implementation statistics of the chip. Figure 10 (see the end of the paper, after references)
illustrates the signals that are available at the I/O pins.
During the TEST mode, all satellites and the
Technology 0.25 µm 6-level metal reconfigurable interconnect can be configured by writing
CMOS to Taddr and Tdata pins (to the ConfigAdd and
Main Supply Voltage 1V ConfigData buses) and the result of the computation can
Additional Voltages 0.4 V, 1.5 V be read on the Tdata and FIQ pins (from ReadData and
Die Size 5.2 mm x 6.7 mm ACK buses). In addition, simple programs can also be
Transistor Count 1.2 Million transistors fed to ARM8 via Tdata pins to test satellite configuration
Average Cycle Speed 40 MHz reading and writing. The current test set-up supports the
Average Power Dissipation 1.5 - 2 mW test mode described above and a board to verify the
SYSTEM mode is being designed. The HP 16702A logic
analysis system was used for generating the test vectors
Table 1: Chip Characteristics (derived from Timemill simulations) for the TEST mode.
Pattern acquisition was used for verifying the results of
Hardware Pipeline Energy Area the computations after detecting end of kernel using an
modules speed consumptio (mm2) external interrupt signal.
(ns) n per
operation Energy and performance of all kernels are tested in the
(PJ) TEST mode. Based on this information, the estimated
MAC 24 21 0.25 energy dissipation of the processor when programmed for
ALU 20 8 0.09 a VCELP voice coder (with 1.8mW total power
Memory (1K x 14 8 0.32 consumption) is presented in Table 3, including a
16) breakdown of the energy over the major functions.
Memory (512 x 11 7 0.16 Dominant kernels are directly mapped onto hardware
16)
satellites, and their run-time reconfiguration is performed
Address generator 20 6 0.12
by the ARM core. Therefore, the kernel energy presented
Interconnect 10 1* NA
in the table incorporate contributions from both satellite
network
FPGA 25 18** 2.76 and ARM8 configuration. The program control part of
the algorithm is completely mapped to the software. The
total energy efficiency is a factor of 8 better than the best
Table 2: Performances of hardware modules reported in literature [18].
*This number is the average energy consumption per
connection
**This number is the average energy consumption across
various arithmetic functions
 MEM MEM

AGU AGU AGU AGU

FPGA
MEM MEM

ALU ALU
MAC MAC
MEM MEM

Interconnect Network
AGU MEM AGU AGU MEM AGU

Interface

ARM8 Core

Figure 9. Maia die photo

Functionality Energy consumption (mJ) for 1 sec

of VCELP speech processing
Dot product 0.738
FIR filter 0.131
IIIR filter 0.021
Vector sum with scalar multiply 0.042
Kernels Compute code 0.011
Covariance matrix compute 0.006
Program control 0.838
Total 1.787
Table 3. VSELP energy breakdown
current trend in system-on-a-chip design which contains
6 CONCLUSION embedded components of various flexibility and
In this paper, Pleiades, a heterogeneous reconfigurable reconfigurability (microprocessor, ASICs, FPGA). The
architecture template is introduced and a design heterogeneity and reconfigurability of the architecture
methodology to map algorithms to architectures is proves to be very energy efficient when compared to
summarized. The details of the design and state-of-the-art programmable processors.
implementation of an instance of the Pleiades
architecture is presented. The implementation echoes the
7 ACKNOWLEDGEMENTS
We would like to acknowledge DARPA’s support for the
Pleiades project (DABT-63-96-C-0026). The authors
would like to thank Seno Katsunori and Yuji Ichikawa
for their early work on the Pleiades prototype and
evaluation. We would like to acknowledge other
members on the Maia design team.
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SYSTEM MODE TEST MODE
Off-chip Logic Analyzer
SRAM
Taddr<15:0>
Addr<31:0> Tdata<31:0>
Dq<31:0> Test,TRwn,TClk,FIQ etc.
Other controls
IO Pins

Wdata 32
Rdata 32 ConfigAdd 16

ARM8 VAddress 32 ConfigData 32

Core Requests Interface ReadData 32
Responses Strobe 22 Satellites
Interrupt Start
ACKs 10

Figure 10. Maia chip testing strategy