2> m V

(Invited)
High-Performance III-V devices for future logic applications
1,2 1 1 1 2 3 3 4 4
D.-H. Kim , T.-W. Kim , RH. Baek , P. D. Kirsch , W. Maszara , J. A. del Alamo , D. A. Antoniadis , M. Urteaga , B. Brar ,
5 5 5 6 6 6 7
HM. Kwon , C.-S. Shin , W.-K. Park , Y.-D. Cho , SH. Shin , DH. Ko and K.-S. Seo
1 2 3 4 5 6 7
SEMATECH, GLOBALFOUNDRIES, MIT, Teledyne Scientific, KANC, Yonsei University and Seoul National University
E-mail: Dae-Hyun.Kim@sematech.org

Abstract: High-mobility III-V transistors are poised to Pt

take the lead on future high performance logic operation. If
this happens, indium-rich InxGa1-xAs is the most promising T-gate
n-channel material. Indeed, remarkable progress has been
S Ti
made, including III-V gate-stacks with ALD-grown gate Drain
dielectrics. This paper reviews the evolution of high-
InGaAs/InAlAs InAlAs tins = 4 nm
performance III-V devices for future logic applications and InP (6 nm) a
discuss a possible path forward to further improve their logic Lg InGaAs
figure-of-merits.
InAlAs (11 nm) tins
InGaAs/InAs/InGaAs tch = 10 nm InAlAs
Introduction: In early 2000s, indium-rich InxGa1-xAs
(x>0.53) has recently emerged as the most promising non-Si InAlAs Buffer
n-channel material for post Si CMOS logic applications [1].
Fig. 1 Cross-sectional schematic of state-of-the-art InGaAs
This is thanks to the outstanding electron transport
HEMT [4].
characteristics, excellent interfacial quality of the high-
k/InGaAs gate stack by ALD and co-integration of InGaAs-
-2
based heterostructures with Si [1-2]. Recently, significant 10 1.5
progress has been made on a variety of GaAs and InGaAs DIBL = 120 mV/V
-3
MOSFETs by many different groups. This paper reviews 10 SS = 90 mV/dec.
high-performance III-V devices for future logic applications, gm,max > 2.5 mS/μm
-4
covers recent advances in some of the key enabling 10 1.0

ID [mA/μm]
technology of InGaAs MOSFETs, and finally discusses
ID [A/μm]

-5
options to further improve the performance of InGaAs 10
MOSFETs.
-6
10 0.5
How good are III-V’s for future logic applications?: As a
-7
way to assess the prospects for a future III-V MOSFET 10
technology with gate lengths in the sub-10 nm range, we VDS = 0.5 V
started our research in 2005 on state-of-the-art III-V High- 10
-8
0.0
Electron-Mobility-Transistors (HEMTs). The HEMT in -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6
itself a device with near THz capabilities, was an excellent VGS [V]
prototype Field-Effect-Transistor (FET) for future logic. The Fig. 2 Subthreshold and transfer characteristics of Lg = 30
HEMT is a FET with a “medium-k” gate barrier and nm InGaAs HEMT with tins = 4 nm [4-5].
outstanding carrier transport properties. From 2005 to 2009,
we investigated the logic characteristics of scaled-down Evaluation of III-V Gate Stack: The key enabling
InGaAs HEMTs [3-5]. From this time, Figs. 1 and 2 show technology for InGaAs MOSFETs is a high-quality
cross-sectional schematic and typical subthreshold/transfer oxide/semiconductor interface by ALD. During ALD, a kind
characteristics of Lg = 30 nm In0.7Ga0.3As HEMTs with tins = 4 of ‘self-cleaning effect’ or ‘clean-up effect’ takes places such
nm at VDS = 0.5 V [4-5]. DIBL, S and gm_max are 120 mV/V, that III-V surface oxides are effectively removed [7]. Many
90 mV/dec. and > 2.5 mS/•m at VDS = 0.5 V, respectively, different groups have demonstrated excellent Al2O3/InGaAs
which outperform today’s state-of-the-art Si nMOSFETs interfaces and surface-channel III-V MOSFETs. However,
with equivalent gate length [6]. An ION/IOFF ratio in excess of this is insufficient for future scaled CMOS. In particular, a
4
10 in well-designed devices, even with supply voltage of 0.5 dielectric with higher k is required. Also, in a surface-
V is obtained. The device exhibits ION = ~ 0.62 mA/μm at an channel design, interface roughness scattering severely
ILeak = 100 nA/μm. This is the highest ION in any III-V FET on degrades the mobility (Fig. 3). The pressing need for the 7-
any material system, to date. This is about 20% higher ION nm technology node and/or beyond is for an ultra-scaled
than state-of-the-art high-performance 22 nm nMOSFET surface-channel design with total EOT well below 1 nm
with comparable physical gate length and ILeak at VDD = 0.5 V while maintaining excellent transport properties. We have
[6]. It was data like these that showed that InGaAs-channel been investigating a composite Al2O3/HfO2 gate stack, where
HEMTs prototyped in a university environment could a thin Al2O3 interfacial layer serves as passivation. This leads
outperformance state-of-the-art Si nMOSFETs of similar to a far better mobility-EOT trade-off, while maintaining
gate length at VDD = 0.5 V that strongly highlighted the lower Dit on InGaAs which is confirmed by our device
potential of InGaAs MOSFETs for logic. results (Fig. 4) [8].

978-1-4799-8001-7/14/$31.00 ©2014 IEEE 25.2.1 IEDM14-578

 6000
InGaAs MOSFET
with Al2O3/HfO2
Progress and Prospects of InGaAs MOSFETs: Starting
from III-V MOSFETs with state-of-the-art characteristics, it
μeff @3e12cm (cm /V-s)

is very useful to benchmark InGaAs MOSFETs against

InGaAs HEMTs [9]. Figs. 5 (a), (b) and (c) show the
2

4000
evolution of transconducntace (gm), on-resistance (Ron) and
the current-gain cut-off frequency (fT) of InGaAs MOSFETs
-2

as well as InGaAs HEMTs for the last three decades. InGaAs

MOSFETs have now matched the gm of HEMTs and
2000 ZrO2 MOSHEMT
surpassed the Ron of HEMTs. The high gm behavior in
Al2O3 MOSFET InGaAs MOSFETs stems from the ability to scale the
ZrO2 MOSFET effective oxide thickness in the MOS gate stack as well as
Surface-Channel MOSFETs the excellent interface-state density (Dit, shown in the inset
0 of Fig. 4). These are also responsible for the very low Ron.
0 2 4 6 8 10 The excellent parasitic resistance characteristics in InGaAs
CET (nm) MOSFETs arise from the absence of an energy barrier under
Fig. 3 μeff at ns = 3×10 cm vs. CET for planar InGaAs QW
12 -2
the S/D contracts, which is the bottleneck in InGaAs
MOSFET with Al2O3/HfO2 [8] and other reports on various HEMTs. Recently, several groups have successfully
types of III-V MOSFETs. Inset is the cross-sectional TEM demonstrated sub-100 nm InGaAs MOSFETs with record
image for Al2O3/HfO2 gate stack on InGaAs [8]. Ron and gm behavior, approaching gm_max = 3 mS/μm at VDS =
Fig. 4 Subthreshold characteristics of long-channel InGaAs 0.5 V [10-12].
-4
10 Figs. 6 and 7 exhibit microwave and high frequency
VDS = 0.5 V
SS < 70 mV/dec. noise-figure characteristics of an Lg = 35 nm In0.7Ga0.3As
MOSFET with Al2O3/HfO2 bilayer gate stack. Excellent
-5 high-frequency characteristics can be observed in this
10
VDS = 0.05 V device, such as current-gain cutoff frequency (fT) = 440
GHz, maximum oscillation frequency (fmax) = 305 GHz and
ID [A/μm]

-6 13 minimum noise-figure (NFmin) < 0.5 dB at 26 GHz. The

Dit [cm eV ]

10 10
-1

results are record values for fT and fmax, and the lowest NFmin
at 26 GHz of any III-V MOSFET. It is interesting to see that
-2

-7
today’s InGaAs HEMTs still exhibit a far better fT than
10 Al2O3/HfO2: EOT ~ 0.7nm
InGaAs MOSFETs. This is mostly due to low-parasitic
12
10 capacitance design employed in InGaAs HEMTs, such as T-
-0.1 0.0 0.1 gate. With the introduction of low parasitic capacitance
-8 VGS - VT [V]
10 MOSFET designs, it is expected that InGaAs MOSFETs that
0.0 0.2 0.4 0.6 0.8 match or exceed the high-frequency characteristics of
VGS [V] InGaAs HEMTs will be developed.
MOSFET with Al2O3/HfO2 at VDS = 0.05/0.5 V. Inset is
extracted Dit for Al2O3/HfO2 on InGaAs channel. EOT < 1
12 2
nm, SS < 70 mV/dec., and Dit ~ 2 × 10 /cm eV [8].

(a) Transconductance (gm) (b) ON-resistance (Ron) (c) Cut-off Frequency (fT)
Fig. 5 Benchmarking of Inversion-type InGaAs MOSFETs against InGaAs HEMTs, as a function of year [9].

IEDM14-579 25.2.2
 60 characteristics in our previous report [17], coupled with
12 -
Lg = 35 nm TCAD simulation, we preliminary extract Dit ~ 4 x 10 eV
1 -2
cm at the sidewall gate stack interface between Al2O3 and
VDS = 0.5 V etched InGaAs fin, which is about 2 times larger than planar
2
|h21| gate stack.
40
8000
Gains [dB]

Ug
Al2O3/HfO2 = 0.7/3 nm
fT = 440 GHz

μn,eff [cm /V-sec]

20 MAG 6000

fmax = 305 GHz 4000

2
0
9 10 11 12
10 10 10 10
Frequency [Hz] 2000
Fig. 6 RF gains (h21, MAG and unilateral gain) against
frequency for Lg = 35 nm In0.7Ga0.3As MOSFETs with
Al2O3/HfO2 at VDS = 0.5 V. The device shows a record value
of fT = 440 GHz.
0
1 2 3 4 5
12 2
1.0 30 nS (x10 /cm )
Fig. 8 Effective mobility (μn,eff) as a function of carrier
0.8 density (ns) for InGaAs MOSFET with epitaxial selectively-
regrown S/D contact. This allows a gate-last integration
20 scheme that prevents degradation of III-V gate-stack. This
Ga
0.6 leads to a record μn,eff behavior, in excess of 5,500 cm /V-s at
2
NFmin [dB]

Ga [dB]

300K [14].

0.4
NFmin 10 -3 VDS =
10 Symbols: measured
0.5V
0.2 Lines: VS model
VDS = 0.5 V 0.05V
-4
ID = 0.1 mA/μm 10
Wfin = 30 nm
0.0 0
0 5 10 15 20 25 30
Hfin = 20 nm

-5
10
ID [A/μm]

Freq. [GHz]
Fig. 7 High-frequency minimum noise-figure (NFmin) and -6
InGaAs
associated gain (Ga) against frequency for Lg = 35 nm 10
In0.7Ga0.3As MOSFETs with Al2O3/HfO2 at VDS = 0.5 V.
-7
10 InAlAs
Alternative MOSFET designs are being pursued. Epitaxial
selectively-regrown S/D contacts (Fig. 8) have recently Lg = 50 nm
-8
yielded record Ron and effectively mobility (μn,eff) behavior in 10
0.0 0.2 0.4 0.6 0.8
InGaAs MOSFETs [13-14]. This allows the introduction of
tensile strain to boost performance [15] and enables a gate- VGS [V]
last integration scheme that prevents degradation of the III-V Fig. 9 Subthreshold characteristics of Lg = 50 nm InGaAs
gate stack [14]. Sub-10 nm MOSFETs will require 3D MOSFET with Wfin/Hfin = 30/20 nm. At VDS = 0.5 V, the
device architectures, such as Tri-gate FETs [16-17] or Gate- device exhibits SS < 80 mV/dec, DIBL < 20 mV/V, gm_max =
all-around FETs [18]. In Tri-gate FETs, how to define an 1.5 mS/μm and ION = 380 mA/μm [8].
InGaAs fin on Si is a major concern. For this, we have been
investigating RIE in combination with post wet treatment.
Fig. 9 exhibits subthreshold characteristics of the state-of- Fig. 10 highlights TCAD simulation result on the impact
the-art Tri-gate InGaAs MOSFET with Lg/Wfin/Hfin = of Dit onto subthreshold-swing in double-gate (DG) InGaAs
50/30/20 nm [17]. A concern in Tri-gate MOSFETs is the MOSFETs with Lg = 100 nm and EOT = 1 nm. Appropriate
sidewall MOS interface. From the subthreshold surface treatment and/or post-etch annealing process should

25.2.3 IEDM14-580
 be explored to further improve the sidewall MOS gate stack
behavior. Finally, Fig. 11 plots benchmarking of ION against
Lg for the state-of-the-art InGaAs HEMT [5] and recently
published InGaAs MOSFETs. Well-designed InGaAs
MOSFETs exhibit a peak gm of 2.7 mS/μm and a record ION ~
0.4 mA/μm at IOFF = 100 nA/mm and VDD = 0.5 V.
120
still remain. This paper reviews high-performance III-V
transistor technology for future logic applications.
Ackonwledgement: The portion of KANC’s research was
supported by a grant from the R&D Program for Industrial
Core Technology funded by the Ministry of Trade, Industry
and Energy, Republic of Korea (Grant No. 10045216), and
internal R/D program at KANC

100 Reference:
SS [mV/dec]

[1] G. Dewey et al., VLSI Tech. Dig., p. 45 (2012).

[2] N. Waldron et al., ECS Trans., Vol. 45, p. 115 (2012).
[3] R.S. Chau et al., SSDM Ext. Abst., p. 68 (2003).
80 [4] D.-H. Kim et al., IEDM Tech. Dig., p. 133 (2007).
[5] D.-H. Kim et al., IEDM Tech. Dig., p. 765 (2011).
[6] C.-H. Jan et al., IEDM Tech. Dig., p. 44 (2012).
2 [7] J. A. del Alamo, Nature, p. 317 (2011).
60 Dit=5E11 /eVcm
2
[8] T.-W. Kim et al., APEX, p. 074201 (2014).
Dit=1E12 /eVcm [9] J. A. del Alamo et al. IEDM Tech. Dig., p. 24 (2013).
Lg=100 nm Dit=5E12 /eVcm
2
[10] J. Lin et al., IEDM Tech. Dig., p. 421 (2013).
40 [11] SH. Lee et al., APL, p. 233503 (2013).
0 10 20 30 40 50 [12] SW. Chang et al. IEDM Tech. Dig., p. 417 (2013).
Tbody [nm] [13] G. Zhou et al., IEDM Tech. Dig., p. 773 (2012).
Fig. 10 Impact of Dit onto subthreshold-swing (SS) behavior [14] C.-S. Shin et al., VLSI Tech. Dig., p. 36 (2014).
in double-gate (DG) InGaAs MOSFETs with Lg = 100 nm [15] H. C. Chin et al., IEEE EDL, pp. 805 (2009).
and EOT = 1 nm, as a function of body thickness (Tbody). Tbody [16] M. Radosavljevic et al., IEDM Tech. Dig., p. 765
corresponds to fin width (Wfin) in tri-gate configuration. (2011).
[17] T.-W. Kim et al., IEDM Tech. Dig., p. 425 (2013).
[18] J. J. Gu et al., IEDM Tech. Dig., p. 633 (2012).
800
InGaAs HEMT [5]
HP 22nm Si nFET [6]
Planar [10]
600 MOSFET Planar [16]
Trigate [8]
ION [μA/μm]

400

200
VDD = 0.5 V
IOFF = 100 nA/μm
0
0 50 100 150 200
Lg [nm]
Fig. 11 Benchmarking of ION against Lg for state-of-the-art
InGaAs HEMTs [5] and recent InGaAs MOSFETs with
planar [10, 16] and non-planar architecture [8]. For all
devices, IOFF = 100 nA/mm and VDD = 0.5 V.

Summary: CMOS might be about to take the disruptive

step of replacing Si in the channel. If this happens, InGaAs is
the most promising new channel material for n-MOSFETs.
Remarkable progress has taken place, but many challenges

IEDM14-581 25.2.4