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5, MAY 2011
It should be noted that h is a suitable hysteresis band, whose To implement the logic for correct voltage-level selection,
size is determined by the maximum allowable switching fre- various schemes available in the literature have been described
quency of the switching devices, as well as the maximum per- in the following sections on the basis of a single-phase five-level
mitted level of current distortion. A low value of h may lead to inverter. In Section II, the multiband (MB) MHM scheme is
increased switching actions, henceforth, larger switching losses, presented, which has the feature of floating voltage levels at the
while a large value of h may result in increased distortion in the boundaries of the band with symmetric inner bands placement.
controlled current. Therefore, a tradeoff is always required in In Section III, the multioffset-band (MOB) approach is pre-
designing the hysteresis band size. sented, which allots fixed voltage levels at the band boundaries
As only two dc voltage levels are available, the two-level hys- and needs to check the slope as well as the band region of the
teresis control is relatively straightforward with each hysteresis current error. A modification to this approach is also presented,
boundary being mapped essentially to one converter-phase-leg so that it can be easily extended for higher level inverter systems
switched state. However, for multilevel converters, as a larger and tracks the reference more efficiently. Further, a time-based
number of output voltage levels are available, the task is to select (TB) approach for MHM is presented in Section IV, which can
a particular voltage-level output to force the control variable to be used to put a limit on maximum switching frequency as well
zero on an instantaneous basis once it exceeds certain bound- as to achieve improved performances. The detailed simulation
ing limits. Therefore, a multilevel hysteresis modulator (MHM) and experimental results for all these schemes have been pre-
requires additional logic to select the appropriate voltage level sented to validate their functioning. Furthermore, a comparative
at any time instant so as to confine the control signal within a evaluation of these schemes has been also presented.
specified hysteresis band.
The starting point toward the design of an adequate MHM
could be the following: according to the instantaneous value II. MB HYSTERESIS MODULATION
of the controlled system variable (uc ), the controller should The MB hysteresis modulation scheme for the multilevel con-
suggest what is the most suitable voltage level required. At any verters uses symmetrical hysteresis bands to control the switch-
instant, when uc exceeds a hysteresis limit, the next higher (or ing so that the inner band causes switching between adjacent
lower) voltage level should be selected in an attempt to force it levels, while the outer band causes an additional switching level
within the specified limits. However, this new converter voltage change whenever necessary. The process, first proposed in [15]
level may not be adequate to return uc to the specified limits. and later used in [22], [26], [31], [32], is shown in Fig. 3 in the
When this happens, the converter should switch to the next form of current regulation. Whenever the current error crosses
higher (or lower as appropriate) voltage level, and the process the inner boundary B, the inverter output is decreased or in-
should cease only when the correct voltage level is selected creased by one level (depending on which hysteresis boundary
that reverses the direction of uc . To exemplify it further, one has just been crossed). Generally, this voltage change will cause
of the standard multilevel inverter topologies, the single-phase- the current error to reverse its direction without reaching the
leg five-level configurations of which are shown in Fig. 2, can next outer band. However, if the error does not reverse, it will
be considered [14]. For a five-level inverter, van in (1) may be continue through the boundary of B to the next outer boundary
defined as van = nVdc , where n = 1/2, 1/4, 0, −1/4, and −1/2, (placed at ΔB out of B). At this point, next higher or lower level
as a five-level inverter may select between voltage levels Vdc /2, voltage will be switched. This process continues as discussed
Vdc /4, 0, −Vdc /4, and −Vdc /2 for the net dc-link voltage of earlier until the current error direction reverses. It is important
Vdc . Then, in a similar manner as described earlier, ce can be to note that if the voltage level applied at a boundary crossing of
kept limited to a specified band by selecting a higher or lower the current error is insufficient to force the error back, no next
voltage level than its present output depending on the polarity voltage level is applied as the error again crosses this boundary
of ce [15]–[34]. next time after the previous voltage level change with the same
1398 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 5, MAY 2011
slope. The error in that case is allowed to go until the next volt-
age level change at next higher or lower boundary crossing of
the error to force it back as is evident from Fig. 3. Fig. 5. Transient performance of MB scheme. (a) Current error and hysteresis
band plots. (b) Reference and measured load current. (c) Inverter output voltage.
To further illustrate the principle of MB scheme, simulation
studies are performed on a five-level inverter, supplying an RL
load of R = 35 Ω and L = 30 mH with the dc-link voltage of
80 V. The back EMF voltage (vback ) is taken as zero and the
inverter devices are assumed nearly ideal. The output current
of inverter (ia ) is controlled using the MB hysteresis scheme
(see Fig. 3) to follow a sinusoidal reference having peak-to-
peak values of ±1.0 A. Corresponding to Fig. 3, the hysteresis
band sizes are taken to be B = 0.04 A and B1 = B2 = 0.02 A.
These values are taken for simplicity by following the consid-
erations presented in [16]. All the simulation results presented
in this paper for hysteresis modulation have been obtained by
using the same set of parameters for a five-level inverter. Fig. 4
shows the simulation results obtained with the MB scheme. It
is evident that the error is contained within the allotted bands
by the corresponding voltage levels appearing at the output of
the inverter. The error trajectory can be similarly followed by
referring it from Fig. 3.
Fig. 5 shows the simulation results obtained under the same
load conditions as earlier, but imposing a current reference of Fig. 6. Overall structure of the experimental setup.
halved amplitude at 45 ms in the simulation run, and thus,
testing it for a transient condition. If the rms value of the current
transient response of the current regulator can be appreciated
required is lower (the load being the same), the rms value of the
from the results shown in Fig. 5(b).
voltage must be lower. Fig. 5 shows that the control technique
is self-adapting in an automatic and natural way; therefore, the
A. Experimental Setup
converter feeds the load by using the lower voltages levels only
[±Vdc /4 and 0, Fig. 5(c)]. It is also seen from Fig. 5(c) that An experimental setup is used to test the MHM schemes dis-
as soon as the step reference change occurs, the corresponding cussed in this paper. A prototype of a single-phase five-level
extreme voltage level (−Vdc /2) appears at output of the inverter insulated gate bipolar transistor (IGBT)-based diode-clamped
to rapidly force the current error back within the specified bands. inverter is built in the laboratory. The overall structure of the
It should be noted that if the change in reference is not that large, experimental setup is shown in Fig. 6. The main power cir-
following a step change in the demanded current, the controller cuits consist of a single-phase five-level voltage source diode-
will remain in the corresponding switching state required to clamped inverter, load, and dc-link circuit. The inverter dc bus is
follow the reference as closely as possible until the current supported by a separately controllable dc supply obtained from
error reaches the hysteresis band. Hence, the advantages of a a single-phase transformer and diode rectifier circuit. The dc-
multilevel topology are fully exploited by this scheme. The fast- link voltage and load parameters of the inverter are kept same as
SHUKLA et al.: HYSTERESIS MODULATION OF MULTILEVEL INVERTERS 1399
Fig. 12. MMOB five-level hysteresis modulation. (a) Current error and the
hysteresis band plots. (b) Inverter output voltage.
gible phase lag between the load current and its reference may
occur [15]. To counteract this dc offset, an offset compensation
strategy to ensure zero average current error within each switch-
Fig. 14. Experimental results showing the MOB hysteresis modulation per- ing period is required for improved performance. Usually, this is
formances. (a) Inverter output voltage and current error with the MOB method.
(b) Inverter output voltage and current error with the MMOB method. (c) Load achieved by adding a compensating factor of half the hysteresis
current with the MMOB method. (d) Inverter output voltage and load current band offset magnitude to the load current reference [15], [17].
with halved hysteresis band sizes and with the MMOB method. This technique is robust, but has the general limitation of requir-
ing increasingly complex analog circuitry for implementing the
multiple hysteresis bands and offset compensation as the num-
The experimental investigations are carried out to validate the ber of voltage level increases. Therefore, the MOB hysteresis
MOB and MMOB schemes with the same experimental setup method has not found wide applications.
as discussed in the previous section. The system parameters are
same as considered in the simulation studies presented earlier. IV. TB HYSTERESIS MODULATION
Fig. 14(a) shows the performance of MOB modulation. As ex-
As discussed earlier, although the MOB schemes are easy
pected and described earlier corresponding to the simulation
to implement [15], it requires offset compensation signals to
results in Fig. 10, though the controller is able to keep the cur-
be added to the controlled system variable, since the bands are
rent error in the defined hysteresis bands, it suffers from poor
not symmetric about zero. The MB scheme, presented earlier
inverter output voltage due to skipping of the intermediate volt-
in Section II, does not suffer from this steady-state-tracking
age levels. Fig. 14(b) and (c) shows the performance of MMOB
error problem, but may still not have evenly symmetric current
modulator with the same parameters. In Fig. 14(d), the results
error waveform, especially for nonsinusoidal current references.
show the performance of MMOB modulator with halved values
In the following, a TB MHM is first described, which works
of B and ΔB. Its better performance can be appreciated from
on the principle of controlling the system variable within a
the results shown and can be justified from the discussions pre-
single band so that any type of current offset can be avoided.
sented earlier. It should be noted that the load current shown
Then, a modified TB approach for MHM is discussed, which
in Fig. 14(c) is almost same with both the MOB and MMOB
shows much better performances in terms of tracking as well as
methods as both are able to limit the error within the specified
can be used with a limit on the maximum allowable switching
bands. The experimental results confirm the correctness of sim-
frequency.
ulation and validate the similar behaviors described previously
in the simulated cases. It should also be noted that since in both
A. TB Multilevel Hysteresis Modulation
the conditions, the current error is bounded between the allotted
limits, the controlled current waveform in all the cases resem- A TB multilevel hysteresis control scheme was proposed
bles with the one presented in Fig. 14(c). Further, the tracking in [15] to use only one hysteresis band to detect an out-of-
of the reference load current in the two cases can be confirmed bounds current error. Digital logic is used to select the “correct”
by looking at the current errors presented in Fig. 14(a) and (b). voltage level in response. Upon detecting the error exceeding the
As can be seen from Figs. 8–14, one disadvantage of this upper (or lower) hysteresis limit, the inverter output is switched
scheme is that the offset placements of the hysteresis bands about down (or up) one voltage level so as to return the error back to
zero error introduce a steady-state tracking error. In steady state, zero, as earlier. But if the new inverter switched state is inad-
the average value of the current error in Fig. 12(a) approaches equate to reverse the error back to zero, the output is switched
zero only if the fundamental periods are considered. It does further down (or up) until the current-error direction reverses. A
not increase the total harmonic distortion (THD) value of the possible current error trajectory and inverter switched output for
current, but causes a decrease in the fundamental harmonic com- a five-level inverter are shown in Fig. 15. Referring to Fig. 15,
ponent. This problem may become a severe one if more than the objective of this method is to force the current error in a
five voltage levels are to be employed in which case a nonnegli- manner so that it remains within band B. It is evident that the
SHUKLA et al.: HYSTERESIS MODULATION OF MULTILEVEL INVERTERS 1403
Fig. 16. TB five-level hysteresis modulation. (a) Current error and the hys-
teresis band plots. (b) Inverter output voltage.
Fig. 19. Modified TB five-level hysteresis current control. (a) Current error
and hysteresis band plots. (b) Inverter switched output voltage.
Fig. 20. Control details of modified TB scheme. (a) Current error and hystere-
at the crossing points. This is because, in these regions, the sis band plots. (b) Inverter output voltages. (c) Time interval between consecutive
control signal is heading toward zero line, which implies that switching instants (in microsecond).
the error between the controlled current and its reference value is
reducing with the present output voltage level. Hence, no voltage
transition is required for this. Another point to be noted is that, no applied to have a TB control. Further, the tuning of t1 along with
exact evaluation is needed for the current error slope, as only the B and ΔB should be properly done to have a good harmonic
sign of the current error slope is needed at its crossing points with spectrum of the controlled current and voltage, while also taking
the band limits. At each sampling instant in the measurement into consideration the maximum allowable switching frequency.
process, the current value of the error is compared with its This TB control applied to control the current in this scheme
previous value. A positive value of this difference indicates a can also be applied to the other schemes discussed in previous
positive slope, while the negative value indicates a negative sections.
slope [16]. Therefore, this scheme does not suffer from noise To look into detail, the functioning of this scheme and observe
amplification problem as in [20]. its operation under a transient condition, another simulation
To get further insight into the modified TB scheme of Fig. 18 study is performed with the same parameters and a small-step
and exemplify its working, simulation studies are performed on change in the reference current magnitude at instant 8.4 ms. (say,
a five-level inverter with the current reference and inverter, and tt ) in the simulation run. The value of t1 is taken 40 μs. The
load parameters being the same as considered earlier and with corresponding results are shown in Fig. 20. It can be seen that
hysteresis band sizes of B = 0.04 A and ΔB = 0.02 A. The as the current error comes out of the outermost boundary fol-
value t1 (delay in the TB control) is taken to be 200 μs. This value lowing a step change in reference magnitude, the corresponding
of t1 is purposely taken to be almost equal to the minimum time extreme voltage level −Vdc /2 is switched to rapidly force the
interval between two consecutive switching decisions under the error within the band limits. However, the next higher voltage
given system conditions to have a better viewing of the controller level −Vdc /4 switched at tu is insufficient to force the error
performance. The simulated waveforms are shown in Fig. 19. back. Therefore, it keeps on increasing and crosses the next
The current error variation across the hysteresis bands can be boundary at tv . However, no other voltage-level switching takes
followed from the discussions presented earlier corresponding place at tv as the time interval between tu and tv is less that
to Fig. 18. It is evident that at tq , the error touches the upper t1 = 40 μs [see Fig. 20(c)]. Therefore, the error keeps on in-
boundary of B and the voltage level +Vdc /4 is switched at the creasing and even the next higher voltage level 0, switched at
output of inverter to force the error in the opposite direction. tw , is insufficient to force the error back toward B. As a result,
However, at tr , when the error crosses the lower boundary of the error touches the next allotted boundary at tx and here, the
B, the next higher voltage level is not switched as the time switched voltage +Vdc /2 forces it back toward B. After this,
interval between the instants tq and tr is less than t1 = 200 μs. the consecutive control actions are processed as detailed earlier.
Therefore, the error crosses B at tr and is forced back in the In this way, the n number of output voltage levels control the
opposite direction at ts , i.e., at ΔB from the lower boundary current to track its reference using the allotted hysteresis band
of B, where voltage level +Vdc /2 is switched. In this way, the regions. It should again be noted that the relatively larger val-
current is controlled to follow its reference by using the four ues of t1 in these simulation studies are correspondingly taken
bands for a five-level inverter and a five-level output voltage to highlight the TB control. In practice, its minimum possible
waveform is obtained [see Fig. 19(b)] for a sinusoidal reference value is limited only by the factors discussed earlier.
current. Fig. 21 shows the simulation results, obtained under the same
It is evident from Fig. 19(a) that the TB control is also oper- transient condition, as considered in the previous sections with
ative in this scheme, e.g., between tq and tr . It should be noted the same inverter and load parameters. It is again evident from
that in this scheme, the time differences between two consecu- Fig. 21 that the control technique is self-adapting in an automatic
tive switching is checked each time before a next voltage level is and natural way in the same manner as discussed earlier. Hence,
1406 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 5, MAY 2011
Fig. 21. Transient performance of modified TB scheme. (a) Current error and
the hysteresis band plots. (b) Reference and measured load current. (c) Inverter
output voltage.
Fig. 23. Experimental results of TB five-level hysteresis modulation with
larger band sizes. (a) Inverter output voltage and current error. (b) Inverter
output voltage and load current. (c) Inverter output voltage and time interval
between consecutive switchings.
than t1 . Hence, the error had to cross B and next voltage level
change takes place at pZ , i.e., at ΔB from the lower boundary
of B. The corresponding time intervals between consecutive
switching instants are shown in Figs. 22(c) and 23(c). As detailed
earlier, this value is checked each time before a next voltage level
is applied to have a TB control. By comparing the experimental
results of Fig. 22 with those of the simulation results presented in
the previous section, it can be said that the experimental results
matches closely with the simulation results as expected.
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regulation and capacitor voltage balancing schemes for flying capacitor Anshuman Shukla (S’04–M’09) received the
multilevel inverter,,” IEEE Trans. Power Electron., vol. 23, no. 2, pp. 518– B.Sc. Eng. degree in electrical engineering from
529, Mar. 2008. Muzaffarpur Institute of Technology, Muzaffarpur,
[17] G. H. Bode and D. G. Holmes, “Implementation of three level hysteresis India, in 2001, and the M.Tech. and Ph.D. degrees in
current control for a single phase voltage source inverter,” in Proc. IEEE electrical engineering from Indian Institute of Tech-
PESC, 2000, pp. 33–38. nology Kanpur, Kanpur, India, in 2003 and 2008,
[18] G. H. Bode, D. N. Zmood, P. C. Loh, and D. G. Holmes, “A novel hysteresis respectively.
current controller for multilevel single phase voltage source inverters,” in Since September 2008, he has been with ABB
Proc. IEEE PESC’01, pp. 1845–1850. Corporate Research, Vasteras, Sweden. In 2008, he
[19] A. Shukla, A. Ghosh, and A. Joshi, “Hysteresis current control operation was a Research Associate in the Department of Elec-
of flying capacitor multilevel inverter and its application in shunt compen- trical Engineering, University of South Carolina,
sation of distribution Systems,” IEEE Trans. Power Del., vol. 22, no. 1, Columbia. His current research interests include modulation and control of
pp. 396–405, Jan. 2007. power electronic converters and new converter topologies.
SHUKLA et al.: HYSTERESIS MODULATION OF MULTILEVEL INVERTERS 1409
Arindam Ghosh (S’80–M’83–SM’93–F’06) re- Avinash Joshi received the Ph.D. degree in electrical
ceived the Ph.D. degree in electrical engineering from engineering from the University of Toronto, Toronto,
the University of Calgary, Calgary, AB, Canada, in ON, Canada, in 1979.
1983. He is currently a Professor of electrical engineer-
He is currently a Professor of power engineering ing at the Indian Institute of Technology Kanpur,
with Queensland University of Technology, Brisbane, Kanpur, India. From 1970 to 1973, he was with the
Australia. From 1985 to 2006, he was with the De- General Electric Company of India Ltd., Calcutta,
partment of Electrical Engineering, Indian Institute India. His research interests include power electron-
of Technology Kanpur, Kanpur, India. His research ics, circuits, digital electronics, and microprocessor
interests include control of power systems and power systems.
electronic devices.
Dr. Ghosh is a Fellow of the Indian National Academy of Engineering.